Claire Xenia Wolf
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72787f52fc
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Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
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2021-06-08 00:39:36 +02:00 |
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Eddie Hung
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7cd3f4a79b
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abc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
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2020-05-14 10:33:56 -07:00 |
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Eddie Hung
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7b543fdb0c
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xilinx: consider DSP48E1.ADREG
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2020-03-04 12:04:02 -08:00 |
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Eddie Hung
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512596760b
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xilinx: cleanup DSP48E1 handling for abc9
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2020-03-04 11:31:12 -08:00 |
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Eddie Hung
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78d4fff69d
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xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
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2020-03-04 11:31:12 -08:00 |
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Eddie Hung
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3ea5506f81
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abc9_ops: use TimingInfo for -prep_{lut,box} too
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2020-02-27 10:17:29 -08:00 |
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Eddie Hung
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8408c13405
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Update xilinx for ABC9
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2020-02-27 10:17:29 -08:00 |
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Eddie Hung
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12d70ca8fb
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xilinx: improve specify functionality
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2020-02-27 10:17:29 -08:00 |
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Eddie Hung
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0e7c55e2a7
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Auto-generate .box/.lut files from specify blocks
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2020-02-27 10:17:29 -08:00 |
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Eddie Hung
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f2576c096c
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Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
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2020-01-27 12:29:28 -08:00 |
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Eddie Hung
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da134701cd
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Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
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2020-01-22 14:22:03 -08:00 |
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Eddie Hung
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b2259a9201
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Add abc9_ops -check, -prep_times, -write_box for required times
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2020-01-10 11:45:41 -08:00 |
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Eddie Hung
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98ee8c14df
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2020-01-06 15:02:44 -08:00 |
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Eddie Hung
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db04161eca
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Rework abc9's DSP48E1 model
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2020-01-01 17:30:26 -08:00 |
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Eddie Hung
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b4663a987b
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Fix attributes on $__ABC9_ASYNC[01] whitebox
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2019-12-31 11:14:11 -08:00 |
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Eddie Hung
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979bf36fb0
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Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
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2019-12-19 11:23:41 -08:00 |
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Eddie Hung
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af3055fe83
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Add blackbox model for $__ABC9_FF_ so that clock partitioning works
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2019-11-20 14:30:56 -08:00 |
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Eddie Hung
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3879ca1398
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Do not require changes to cells_sim.v; try and work out comb model
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2019-10-05 22:55:18 -07:00 |
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Eddie Hung
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7a45cd5856
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Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
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2019-10-04 16:58:55 -07:00 |
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Eddie Hung
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aae2b9fd9c
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Rename abc_* names/attributes to more precisely be abc9_*
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2019-10-04 11:04:10 -07:00 |
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