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Author	SHA1	Message	Date
Clifford Wolf	5f9c7fc6ea	Improved handling of techmap special wires	2013-11-23 16:49:58 +01:00
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	532091afcb	Added more generic _TECHMAP_ wire mechanism to techmap pass	2013-11-23 15:58:06 +01:00
Clifford Wolf	9ab850e45e	Making prograss on Appnote 010	2013-11-23 05:46:51 +01:00
Clifford Wolf	3c023054bc	Progress on AppNote 010	2013-11-22 19:08:29 +01:00
Clifford Wolf	bf501b9ba3	Started to write on AppNote 010: Verilog to BLIF	2013-11-22 17:33:59 +01:00
Clifford Wolf	7b9ca46f8d	Updated command-reference-manual.tex	2013-11-22 15:02:40 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	c854ad2e7e	Some driver changes/fixes	2013-11-22 14:53:57 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	058ceda6a0	Added more performance measurement infrastructure	2013-11-22 14:08:10 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	18d003254c	Massive performance improvement from refactoring RTLIL::SigSpec::optimize()	2013-11-22 04:41:20 +01:00
Clifford Wolf	8e58bb330d	Added SigBit struct and refactored RTLIL::SigSpec::extract	2013-11-22 04:07:13 +01:00
Clifford Wolf	7b01ba384f	Improved make rules for profiling and debugging	2013-11-22 04:05:30 +01:00
Clifford Wolf	1c4a6411af	Updated abc	2013-11-21 22:39:10 +01:00
Clifford Wolf	40d9542647	Implemented $_DFFSR_ expression generator in verilog backend	2013-11-21 21:52:30 +01:00
Clifford Wolf	95c94a02fc	Fixed async proc detection in mem2reg	2013-11-21 21:26:56 +01:00
Clifford Wolf	09471846c5	Major improvements in mem2reg and added "init" sync rules	2013-11-21 13:49:00 +01:00
Clifford Wolf	84ced2bb8e	Fixed a bug in "add -global_input"	2013-11-21 03:01:20 +01:00
Clifford Wolf	64a5f8f75e	Added "proc_arst -global_arst" feature	2013-11-20 21:00:43 +01:00
Clifford Wolf	08ceb3729e	Fixed ilang parser: memory width	2013-11-20 19:55:52 +01:00
Clifford Wolf	2279b2a196	Added "add" command (only wires for now)	2013-11-20 19:37:40 +01:00
Clifford Wolf	65ad556f3d	Another name resolution bugfix for generate blocks	2013-11-20 13:57:40 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	c4c299eb5a	Do not allow memory bit select on the left side of an assignment	2013-11-20 12:18:46 +01:00
Clifford Wolf	0f04738f40	Added "synthesis" in (synopsys|synthesis) comment support	2013-11-20 11:44:09 +01:00
Clifford Wolf	ac2be2d892	Fixed name resolution of local tasks and functions in generate block	2013-11-20 11:05:58 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	d248419fe0	Updated TODOs in README file	2013-11-20 02:10:48 +01:00
Clifford Wolf	e340532ce5	Added init= attribute for fpga-style reset values	2013-11-20 01:49:37 +01:00
Clifford Wolf	a1353ec61b	Added "make config-sudo"	2013-11-19 23:13:41 +01:00
Clifford Wolf	0c91f890c9	Install simlib in datdir	2013-11-19 23:05:46 +01:00
Clifford Wolf	7ea7342c18	Large improvements in yosys-config	2013-11-19 23:04:27 +01:00
Clifford Wolf	0dfdbd991a	Fixed parsing of module arguments when one type is used for many args	2013-11-19 20:35:31 +01:00
Clifford Wolf	63285b300c	Renamed temp module generated by "abc" pass from "logic" to "netlist"	2013-11-19 01:03:57 +01:00
Clifford Wolf	c5e26f839c	Added additional mem2reg testcase	2013-11-18 19:55:39 +01:00
Clifford Wolf	4f2edcf2f9	Fixed two bugs in mem2reg functionality in AST frontend	2013-11-18 19:55:12 +01:00
Clifford Wolf	79910a5547	Added dumping of attributes in AST frontend	2013-11-18 19:54:36 +01:00
Clifford Wolf	2a25e3bca3	Fixed parsing of default cases when not last case	2013-11-18 16:10:50 +01:00
Clifford Wolf	de03184150	Fixed mem2reg for reg usage outside always block	2013-11-18 12:35:41 +01:00
Clifford Wolf	97f2979bba	Added commented-out osu025 maping commands to cmos techmap example	2013-11-18 12:01:00 +01:00
Clifford Wolf	7d52eb0ddb	Added -v<level> option and some minor driver cleanups	2013-11-17 13:26:31 +01:00
Clifford Wolf	2df5cd87b2	Renamed ABCHGPULL to ABCPULL in Makefile	2013-11-16 15:17:32 +01:00
Clifford Wolf	f3345bd3b4	Improved building of yosys-abc	2013-11-13 15:49:42 +01:00
Clifford Wolf	a694324a75	Fixed abc pass blif parser for constant bits	2013-11-13 15:46:28 +01:00
Clifford Wolf	63060dcd2e	Fixed parsing of "parameter integer"	2013-11-13 15:30:23 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	0fd3ebdb23	Added information on all internal cell types to internal checker	2013-11-11 00:13:18 +01:00
Clifford Wolf	378cc509cd	Call internal checker more often	2013-11-10 23:24:21 +01:00