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13586 commits

Author SHA1 Message Date
Krystine Sherwin
0fb511905a
docs: more tidying
Fix 010 pdf link.
Swap yosys script code blocks for literal includes.
Fix broken example code.
2023-11-16 09:46:47 +13:00
Krystine Sherwin
bb7ebec38c
guidelines: fix paths to moved files 2023-11-16 09:11:53 +13:00
Krystine Sherwin
2b270b2270
docs: Tidying image generation
Makefiles now have `clean` target.
Also fixed top level makefile calls to images directory.
More yosys scripts instead of inline yosys commands in makefiles (which also means they can be included in the accompanying document when talking about the image generated).
Fixed another couple image generators that were still outputting pdf directly.
Fixed some hanging image references which hadn't been updated.
Adjusted some text related to images, and included a couple more intermediate images on `memdemo`.
2023-11-16 09:08:22 +13:00
N. Engelhardt
032fab1f54
Merge pull request #4032 from YosysHQ/lofty/gowin-abc9-oopsie
gowin: fix typo
2023-11-15 11:07:49 +01:00
github-actions[bot]
7eea047793 Bump version 2023-11-15 00:15:49 +00:00
Lofty
309558767d gowin: fix typo 2023-11-14 22:37:29 +00:00
N. Engelhardt
5fb1264db5 verific: don't try to import attributes from nullptr 2023-11-14 15:05:24 +01:00
Krystine Sherwin
b6e61c16b1
docs: restructuring images directory
see also previous commit
Also updates `scripting_intro.rst` to use literal includes, and uses individual image outputs to avoid the intermediary `.tex` file to join them all.
2023-11-14 18:54:16 +13:00
Catherine
c11744b4ef
Fix WASI compilation flags for abc. 2023-11-14 03:33:35 +00:00
Catherine
726c501e7e Update WASI compilation flags to include required libraries 2023-11-14 02:05:39 +00:00
github-actions[bot]
46408b5da3 Bump version 2023-11-14 00:15:32 +00:00
Krystine Sherwin
dbc38d72cf
docs: moving code examples
Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.
2023-11-14 12:55:39 +13:00
N. Engelhardt
8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 17:29:57 +01:00
N. Engelhardt
52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work
MachXO3 QoR improvements
2023-11-13 16:56:06 +01:00
N. Engelhardt
3fef81b537
Merge pull request #4028 from povik/cmp2softlogic
synth_lattice: Optionally do constant comparisons in soft logic
2023-11-13 16:53:04 +01:00
Jannis Harder
6cf50d16a8
Merge pull request #3973 from anonkey/master
cli(tcl): add ability to pass argument to tcl script from cli
2023-11-13 16:29:05 +01:00
Lofty
7ae4041e20 ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
N. Engelhardt
04083b4f15
Merge pull request #4027 from YosysHQ/achronix_typo
Fix typo in help message (Acrhonix -> Achronix)
2023-11-13 16:04:24 +01:00
Martin Povišer
3ffa4b5e5d synth_lattice: Wire up cmp2softlogic as an option 2023-11-13 10:42:12 +01:00
Martin Povišer
f7d4a855c6 techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
Krystine Sherwin
83d2f4f334
techlibs: fix typo in help message 2023-11-13 16:29:52 +13:00
Krystine Sherwin
3d70867809
docs: remove synth_machxo2, add _lattice 2023-11-13 16:27:10 +13:00
github-actions[bot]
5691cd0958 Bump version 2023-11-08 00:15:30 +00:00
Martin Povišer
fed2720999 synth_lattice: Optimize flip-flop memories better
After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
2023-11-07 16:29:56 +01:00
Martin Povišer
ee3a4ce14d synth_lattice: Merge NOT gates on DFF control signals
`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
2023-11-07 16:21:39 +01:00
N. Engelhardt
63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd
peepopt: Add `shiftadd` pattern
2023-11-07 10:42:15 +01:00
Miodrag Milanovic
8808da243b Next dev cycle 2023-11-07 08:47:34 +01:00
Miodrag Milanovic
cc31c6ebc4 Release version 0.35 2023-11-07 08:45:31 +01:00
Jannis Harder
d415b4d98a cli: Cleanups for tcl argument handling
* Keep the previous behavior when no tcl script is used
* Do not treat "-" as a flag but as a positional argument
* Keep including <unistd.h> as it's also used for other functions (at
  least for the emscripten build)
* Move the custom getopt implementation into the Yosys namespace to
  avoid potential collisions
2023-11-06 16:40:13 +01:00
phsauter
3618294bac peepopt: Add assert of consistent shiftadd data 2023-11-06 16:35:00 +01:00
N. Engelhardt
93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr
memory_libmap: look for ram_style attributes on surrounding signals
2023-11-06 16:25:38 +01:00
Miodrag Milanović
c58fec636f
Merge pull request #4015 from YosysHQ/log_verific
Change Verific log callback API
2023-11-06 16:22:30 +01:00
phsauter
c3b8de54da test: add tests for shiftadd and shiftmul
This expands the part-select tests with one additional module.
It specifically tests the different variants of the `peepopt`
optimizations `shiftadd` and `shiftmul`.
Not all these cases are actually transformed using `shiftadd`,
including them also checks if the correct variants are rejected.
2023-11-06 14:01:37 +01:00
Philippe Sauter
b6df900bcc peepopt: Describe shiftadd rule in help message 2023-11-06 14:01:37 +01:00
phsauter
9ca57d9f13 peepopt: fix and refactor shiftadd
- moved all selection and filtering logic to the match block
- applied less-verbose code suggestions
- removed constraint on number of bits in shift-amount
- added check for possible wrap-arround in the operation
2023-11-06 14:01:37 +01:00
Philippe Sauter
72c6a01e67 peepopt: Add initial shiftadd pattern 2023-11-06 14:01:37 +01:00
github-actions[bot]
6f1ca68712 Bump version 2023-11-04 00:14:46 +00:00
Lofty
1260766d91
Merge pull request #4020 from YosysHQ/revert-4019-lofty/abc9-by-default
Revert "ice40, ecp5: enable ABC9 by default"
2023-11-03 14:53:15 +00:00
Lofty
b8b47f7c6c
Revert "ice40, ecp5: enable ABC9 by default" 2023-11-03 14:52:52 +00:00
Lofty
deebb82e85
Merge pull request #4019 from YosysHQ/lofty/abc9-by-default
ice40, ecp5: enable ABC9 by default
2023-11-03 14:12:56 +00:00
anonkey
ea91f189a3
cli(tcl): add ability to pass argument to tcl script from cli 2023-11-03 12:21:35 +01:00
Lofty
32082477b5 ice40, ecp5: enable ABC9 by default 2023-11-03 08:52:54 +00:00
Miodrag Milanovic
f06d56d224 Handling non-existing location in verific logs 2023-11-03 08:06:16 +01:00
Miodrag Milanovic
4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
Krystine Sherwin
a283595798
docs: call make resources before make all
Should fix the issue where `make all` in the images directory can't wildcard files that don't exist yet.
2023-11-01 13:29:40 +13:00
Krystine Sherwin
8fad77bd0f
Merge branch 'master' into krys/docs
Fix failing verific tests
2023-11-01 13:17:51 +13:00
Krystine Sherwin
2b10bd5070
docs: update images makefile
Correct path to 011 source.
Also path for resources target.
Set timezone to 'Z' for faketime.

Not sure how to avoid needing to `make resources` before `make all` (or running
`make all` twice) in order to properly generate the presentation images.
2023-11-01 10:48:04 +13:00
Krystine Sherwin
8e07030fee
docs: update auxiliary programs
Now includes usage output, (hopefully) generated by the tool during the docs build process so it will always be up to date.
Included in makefile as `docs/usage` target.
Also some updates/additions to the description text, esp `yosys-filterlib` and `yosys-smtbmc`.
2023-11-01 10:15:58 +13:00
N. Engelhardt
f9ab6e147a mem: only import attributes from ports if the memory doesn't have them yet 2023-10-30 16:31:53 +01:00
Krystine Sherwin
74c1fc1cdd
docs: Reference chapters with doc tag
Fix some formatting.
2023-10-30 22:38:47 +13:00