Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Eddie Hung
d7ada66497
Add "synth_xilinx -dff" option, cleanup abc9
2019-12-30 14:13:16 -08:00
Eddie Hung
79448f9be0
Update doc that "-retime" calls abc with "-dff -D 1"
2019-12-30 13:28:29 -08:00
Eddie Hung
aa6d06c1b5
Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""
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This reverts commit 6008bb7002
2019-12-30 13:28:29 -08:00
Miodrag Milanovic
8c3de1d4bd
Merge remote-tracking branch 'origin/master' into iopad_default
2019-12-28 16:23:31 +01:00
Marcin Kościelnicki
666c6128a9
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
Miodrag Milanovic
436fea9e69
Addressed review comments
2019-12-21 20:23:23 +01:00
Miodrag Milanovic
1937091f62
iopad no op for compatibility with old scripts
2019-12-21 13:21:45 +01:00
Miodrag Milanovic
2fcf683af4
Make iopad option default for all xilinx flows
2019-12-21 11:56:41 +01:00
Eddie Hung
10e82e103f
Revert "Optimise write_xaiger"
2019-12-20 12:05:45 -08:00
Eddie Hung
94f15f023c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-19 10:29:40 -08:00
Eddie Hung
df626ee7ab
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
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Optimise write_xaiger
2019-12-19 12:24:03 -05:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
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This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
dd7d2d8db6
Duplicate tribuf call, credit to @mwkmwkmwk
2019-12-13 08:51:05 -08:00
Eddie Hung
3bd623bb05
synth_xilinx: error out if tristate without '-iopad'
2019-12-12 14:33:33 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
98c9ea605b
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
2019-12-06 17:05:02 -08:00
Eddie Hung
02786b0aa0
Remove clkpart
2019-12-05 17:25:26 -08:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. ( #1528 )
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Fixes #1225 .
2019-12-04 09:44:00 +01:00
Eddie Hung
0add5965c7
techmap abc_unmap.v before xilinx_srl -fixed
2019-12-03 14:27:45 -08:00
Eddie Hung
b1ab7c16c4
clkpart -unpart into 'finalize'
2019-11-28 12:59:43 -08:00
Eddie Hung
df8dc6d1fb
ean call after abc{,9}
2019-11-27 09:10:34 -08:00
Eddie Hung
739f530906
Move 'clean' from map_luts to finalize
2019-11-26 14:51:39 -08:00
Eddie Hung
eb11c06a69
For abc9, run clkpart before ff_map and after abc9
2019-11-23 10:18:22 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
c4bd318e76
synth_xilinx: Merge blackbox primitive libraries.
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
David Shah
3506eaf290
xilinx: Add URAM288 mapping for xcup
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:44 +01:00
David Shah
6769d31ddb
xilinx: Add support for UltraScale[+] BRAM mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
Marcin Kościelnicki
7b350cacd4
xilinx: Support multiplier mapping for all families.
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This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
N. Engelhardt
3b405d985e
Call memory_dff before DSP mapping to reserve registers ( fixes #1447 )
2019-10-17 21:33:54 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
1dc22607c3
Remove -D_ABC9
2019-10-07 12:21:52 -07:00
Eddie Hung
6c5e1234e1
Add comment on why partial multipliers are 18x18
2019-10-04 22:31:04 -07:00
Eddie Hung
b47bb5c810
Fix typo in check_label()
2019-10-04 21:43:50 -07:00
Eddie Hung
a2ef93f03a
abc -> abc9
2019-10-04 17:56:38 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary abc9 -nomfs and use for synth_xilinx -abc9
2019-10-04 17:35:43 -07:00
Eddie Hung
d4212d128b
Use read_args for read_verilog
2019-10-04 17:27:05 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
b3d8a60cbd
Re-order
2019-09-27 14:32:07 -07:00
Eddie Hung
143f82def2
Missing an '&'
2019-09-26 11:13:08 -07:00
Eddie Hung
033aefc0f4
Typo
2019-09-26 10:34:14 -07:00
Eddie Hung
781dda6175
select once
2019-09-26 10:15:05 -07:00
