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Code Activity
13564 commits 93 branches 53 tags 44 MiB
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720 commits

Author SHA1 Message Date
Clifford Wolf
92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range 
Give error instead of asserting for invalid range, fixes #947
 2019-05-27 13:26:12 +02:00
Miodrag Milanovic
84ffb21708 Give error instead of asserting for invalid range, fixes #947 2019-05-27 12:25:18 +02:00
Miodrag Milanovic
34417ce55f Added support for unsized constants, fixes #1022 
Includes work from @sumit0190 and @AaronKel
 2019-05-27 11:42:10 +02:00
Stefan Biereigel
85de9d26c1 fix assignment of non-wires 2019-05-23 17:55:56 +02:00
Stefan Biereigel
fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel
075a48d3fa implementation for assignments working 2019-05-23 13:57:27 +02:00
Stefan Biereigel
9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Clifford Wolf
752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf
d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf
87426f5a06 Improve write_verilog specify support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 08:46:24 +02:00
Eddie Hung
d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Udi Finkelstein
ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf
6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 10:01:54 +02:00
Clifford Wolf
3b6a02d3a7 Fix width detection of memory access with bit slice, fixes #974 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:57:26 +02:00
Clifford Wolf
59d74a3348 Re-enable "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:02:39 +02:00
Clifford Wolf
e35fe1344d Disabled "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 20:22:50 +02:00
Clifford Wolf
9af825e31e Add final loop variable assignment when unrolling for-loops, fixes #968 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:03:32 +02:00
Clifford Wolf
71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
012c6af088 Allow $specify[23] cells in blackbox modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
b232e027bf Checking and fixing specify cells in genRTLIL 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf
4ad0ea5c3c Determine correct signedness and expression width in for loop unrolling, fixes #370 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 18:19:02 +02:00
Clifford Wolf
b40af877f3
Merge pull request #909 from zachjs/master 
support repeat loops with constant repeat counts outside of constant functions
 2019-04-22 08:51:34 +02:00
Clifford Wolf
5b7fea5245 Add "noblackbox" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:09 +02:00
Clifford Wolf
fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Clifford Wolf
f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Zachary Snow
5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Clifford Wolf
638be461c3 Fix mem2reg handling of memories with upto data ports, fixes #888 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:21:17 +01:00
Clifford Wolf
da42f10765 Improve "read_verilog -dump_vlog[12]" handling of upto ranges 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:20:16 +01:00
Clifford Wolf
9b0e7af6d7 Improve read_verilog debug output capabilities 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 20:52:29 +01:00
Zachary Snow
a5f4b83637 fix local name resolution in prefix constructs 2019-03-18 20:43:20 -04:00
Clifford Wolf
17caaa3fa8 Improve handling of "full_case" attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-14 17:51:21 +01:00
Clifford Wolf
d25a0c8ade Improve handling of memories used in mem index expressions on LHS of an assignment 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:12:02 +01:00
Clifford Wolf
a4ddc569b4 Remove outdated "blocking assignment to memory" warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:10:55 +01:00
Clifford Wolf
ab5b50ae3c Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:09:47 +01:00
Clifford Wolf
cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels 
Add support for using SVA labels in yosys-smtbmc console output
 2019-03-09 11:14:57 -08:00
Clifford Wolf
a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 22:44:37 -08:00
Clifford Wolf
22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf
52f80718a7
Merge pull request #848 from YosysHQ/clifford/fix763 
Fix error for wire decl in always block, fixes 763
 2019-03-02 16:32:58 -08:00
Clifford Wolf
ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf
3a51714451 Fix error for wire decl in always block, fixes #763 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 11:56:44 -08:00
Clifford Wolf
ce6695e22c Fix $global_clock handling vs autowire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 10:38:13 -08:00
Clifford Wolf
5d93dcce86 Fix $readmem[hb] for mem2reg memories, fixes #785 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 09:58:20 -08:00
Clifford Wolf
7cfae2c52f Use mem2reg on memories that only have constant-index write ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 13:35:09 -08:00
Clifford Wolf
1816fe06af Fix handling of defparam for when default_nettype is none 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:09:41 +01:00
Clifford Wolf
23148ffae1 Fixes related to handling of autowires and upto-ranges, fixes #814 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 18:40:11 +01:00
Clifford Wolf
974927adcf Fix handling of expression width in $past, fixes #810 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:55:33 +01:00
Clifford Wolf
28fba903c5 Fix segfault in printing of some internal error messages 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:40:52 +01:00
Clifford Wolf
807b3c7697 Fix sign handling of real constants 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-13 12:36:47 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
Clifford Wolf
fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00