mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 00:26:40 +00:00
Code Activity
9484 commits 94 branches 53 tags 44 MiB
Commit graph

54 commits

Author SHA1 Message Date
David Shah
85672a6c1f memory_bram: Fix ignorance of valid, matched rules 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-10 21:48:04 +01:00
whitequark
93ef516d91
Merge pull request #1603 from whitequark/ice40-ram_style 
ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
 2020-04-10 14:51:01 +00:00
Eddie Hung
956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
whitequark
60f047f136 memory_bram: add attr_icase option. 
Some vendor toolchains use case insensitive matching for values of
attributes that control BRAM inference.
 2020-02-06 14:58:20 +00:00
Eddie Hung
dccd7eb39f Cleanup 2019-12-17 00:25:08 -08:00
Eddie Hung
33e6d05585 Enforce non-existence 2019-12-16 17:06:30 -08:00
Eddie Hung
187e1c46e6 Update doc 2019-12-16 14:48:53 -08:00
Eddie Hung
4158ce4eda More sloppiness, thanks @dh73 for spotting 2019-12-16 13:56:45 -08:00
Eddie Hung
6b384861e4 Oops 2019-12-16 13:31:05 -08:00
Eddie Hung
503d1db551 Implement 'attributes' grammar 2019-12-16 12:58:13 -08:00
Diego H
87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
Diego H
b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Diego H
266993408a Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific 2019-12-13 15:43:24 -06:00
Eddie Hung
ab3917d079 Error out if enable > dbits 2019-07-13 03:39:23 -07:00
David Shah
2bf3ca6443 memory_bram: Fix multiport make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-07 16:56:31 +01:00
David Shah
6acbc016f4 memory_bram: Consider read enable for address expansion register 
Signed-off-by: David Shah <dave@ds0.me>
 2019-04-02 19:47:50 +01:00
David Shah
60594ad40c memory_bram: Reset make_transp when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-27 17:19:14 +00:00
David Shah
ac6cc88db3 memory_bram: Fix multiclock make_transp 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 16:21:36 +00:00
Graham Edgecombe
4fef9689ab memory_bram: Fix initdata bit order after shuffling 
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.

This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).

This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
 2018-12-11 21:02:49 +00:00
David Shah
3420ae5ca5 memory_bram: Reset make_outreg when growing read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2018-10-19 14:46:31 +01:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf
23afeadb5e Fixed handling of transparent bram rd ports on ROMs 2016-08-27 17:06:22 +02:00
Clifford Wolf
ffcdc53a18 Don't sign-extend memory bram initialization data 2016-05-15 00:05:30 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf
4864736167 Bugfix in bram read-enable code 2015-09-25 14:22:33 +02:00
Clifford Wolf
924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf
3501f8e364 Fixed memory_bram for ROMs in BRAMs with write-enable inputs 2015-09-24 11:37:15 +02:00
Clifford Wolf
84bf862f7c Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
7319951145 Added memory_bram "make_outreg" feature 2015-04-09 16:08:54 +02:00
Clifford Wolf
21a1cc1b60 Added support for "file names with blanks" 2015-04-08 12:14:34 +02:00
Clifford Wolf
169d1c4711 Added support for initialized brams 2015-04-06 17:06:15 +02:00
Clifford Wolf
dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Ruben Undheim
49649d6ef0 Fixed typos found by lintian 2015-02-01 21:49:55 +01:00
Clifford Wolf
8d295730e5 Refactoring of memory_bram and xilinx brams 2015-01-18 19:05:29 +01:00
Clifford Wolf
b26590f8ab memory_bram hotfix for memories with width 1 2015-01-06 23:59:53 +01:00
Clifford Wolf
da72050107 removed old debug code 2015-01-06 16:08:04 +01:00
Clifford Wolf
9474928672 Towards Xilinx bram support 2015-01-06 15:26:33 +01:00
Clifford Wolf
081e1a49f8 Towards Xilinx bram support 2015-01-06 14:26:51 +01:00
Clifford Wolf
9ea2511fe8 Towards Xilinx bram support 2015-01-05 13:59:04 +01:00
Clifford Wolf
8898897f7b Towards Xilinx bram support 2015-01-04 14:23:30 +01:00
Clifford Wolf
daae35319b Added memory_bram "shuffle_enable" feature 2015-01-04 13:14:30 +01:00
Clifford Wolf
5d631f0ea7 Removed left over debug code from memory_bram 2015-01-04 11:46:04 +01:00
Clifford Wolf
a7fe87f888 Added memory_bram 'or_next_if_better' feature 2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04 memory_bram transp support 2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9 Progress in memory_bram 2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703 Added proper clkpol support to memory_bram 2015-01-02 22:57:08 +01:00
Clifford Wolf
bbf89c4dc6 Progress in memory_bram 2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede Progress in memory_bram 2015-01-02 00:07:44 +01:00