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Code Activity
8442 commits 93 branches 53 tags 44 MiB
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5 commits

Author SHA1 Message Date
Eddie Hung
c4d37813cb Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q 2019-12-16 10:41:13 -08:00
Eddie Hung
c3262d6075 Disable RAM16X1D match rule; carry-over from LUT4 arches 2019-12-13 08:59:17 -08:00
Eddie Hung
8925bf4b96 Add RAM32X6SDP and RAM64X3SDP modes 2019-12-12 18:52:28 -08:00
Eddie Hung
7a9d1be97d Add memory rules for RAM16X1D, RAM32M, RAM64M 2019-12-12 17:44:59 -08:00
Eddie Hung
b97fe6e866 Work in progress for renaming labels/options in synth_xilinx 2019-07-18 14:20:43 -07:00
Renamed from techlibs/xilinx/drams.txt (Browse further)