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Code Activity
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268 commits

Author SHA1 Message Date
Eddie Hung
d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
 2020-04-03 16:28:25 -07:00
Eddie Hung
7b38cde2df cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp 2020-04-03 14:28:22 -07:00
Eddie Hung
7b09a20c0c cmp2lcu: fail if `LUT_WIDTH < 2 2020-04-03 14:28:22 -07:00
Eddie Hung
34c9b83854 synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
Eddie Hung
5b87720b16 synth: use +/cmp2lcu.v in generic 'synth' too 2020-04-03 14:28:22 -07:00
Eddie Hung
2bf03c6ae0 Cleanup +/cmp2lut.v 2020-04-03 14:28:22 -07:00
Eddie Hung
99a32432aa +/cmp2lcu.v to work efficiently for fully/partially constant inputs 2020-04-03 14:28:22 -07:00
Eddie Hung
f68d723cdc Refactor +/cmp2lcu.v into recursive techmap 2020-04-03 14:28:22 -07:00
Eddie Hung
8e851badc4 Cleanup 2020-04-03 14:28:22 -07:00
Eddie Hung
da880d5016 Cleanup cmp2lcu.v 2020-04-03 14:28:22 -07:00
Eddie Hung
9b63700678 techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu 2020-04-03 14:28:22 -07:00
Eddie Hung
fffe42d4c1 cmp2lut: comment out unused since 362f4f9 2020-04-03 14:28:04 -07:00
Marcin Kościelnicki
0ed1062557 simcells.v: Generate the fine FF cell types by a python script. 
This makes adding more FF types in the future much more manageable.

Fixes #1824.
 2020-04-02 18:37:15 +02:00
Miodrag Milanovic
acb341745d Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
N. Engelhardt
0ec971444b
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc 
Add -flowmap option to `synth{,_ice40}`
 2020-03-03 19:15:41 +01:00
Dan Ravensloft
d7987fec12 Add -flowmap to synth and synth_ice40 2020-02-28 14:29:57 +00:00
Eddie Hung
ac24a23e31 Create +/abc9_model.v for $__ABC9_{DELAY,FF_} 2020-02-27 10:17:29 -08:00
Eddie Hung
affae35847 techmap: fix shiftx2mux decomposition 2020-02-07 11:02:48 -08:00
Eddie Hung
4c1d3a126d shiftx2mux: fix select out of bounds 2020-02-05 16:41:09 -08:00
Eddie Hung
b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
Eddie Hung
72e4540ca9 Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00
Eddie Hung
152dfd3dd4 Fix tests -- when Y_WIDTH is non-pow-2 2020-01-21 15:19:41 -08:00
Eddie Hung
8d1b736c4f Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
Eddie Hung
7977574995 New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC 2020-01-21 15:19:41 -08:00
Eddie Hung
5a63c19747 abc9_ops: -write_box is empty, output a dummy box to prevent ABC error 2020-01-15 13:14:48 -08:00
Clifford Wolf
362f4f996d Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-11-11 15:07:29 +01:00
Sean Cross
82f60ba938 Makefile: don't assume python is called python3 
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-10-19 14:04:52 +08:00
Eddie Hung
90236025b7 Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
Eddie Hung
27e5bf5aad Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00
Eddie Hung
35aaa8d73a mul2dsp.v slice names 2019-09-25 22:58:55 -07:00
Eddie Hung
34aa3532fb Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit 2019-09-25 17:26:47 -07:00
Eddie Hung
a4238637ac Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" 
This reverts commit 234738b103.
 2019-09-25 17:25:44 -07:00
Eddie Hung
f4387e817c Revert "No need for $__mul anymore?" 
This reverts commit 1d875ac76a.
 2019-09-25 17:24:11 -07:00
Eddie Hung
234738b103 Remove _TECHMAP_CELLTYPE_ check since all $mul 2019-09-25 16:51:31 -07:00
Eddie Hung
1d875ac76a No need for $__mul anymore? 2019-09-25 14:06:21 -07:00
Eddie Hung
ab46d9017b Fix signedness bug 2019-09-20 10:11:36 -07:00
Eddie Hung
f2d030a70f Be sensitive to signedness 2019-09-10 15:14:55 -07:00
Eddie Hung
76eedee089 Really get rid of 'opt_expr -fine' by being explicit 2019-09-10 14:26:12 -07:00
Eddie Hung
e742478e1d Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-05 13:01:27 -07:00
Eddie Hung
295c18bd6b Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp 2019-08-30 09:50:20 -07:00
David Shah
6919c0f9b0 Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
Eddie Hung
c4e5310823 Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
Eddie Hung
076af2e617 Missing newline 2019-08-20 20:37:52 -07:00
Eddie Hung
e35dfc5ab5 Only swap ports if $mul and not $__mul 2019-08-13 16:52:15 -07:00
Eddie Hung
2a1b98d478 Add DSP_A_MAXWIDTH_PARTIAL, refactor 2019-08-13 10:21:24 -07:00
Eddie Hung
f890cfb63b Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-12 11:32:10 -07:00
Eddie Hung
041defc5a6 Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
Eddie Hung
acfb672d34 A bit more on where $lcu comes from 2019-08-09 09:50:47 -07:00
Eddie Hung
5aef998957 Add more comments 2019-08-09 09:48:17 -07:00
Eddie Hung
dae7c59358 Add a few comments to document $alu and $lcu 2019-08-08 10:05:28 -07:00