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Code Activity
9183 commits 94 branches 53 tags 44 MiB
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21 commits

Author SHA1 Message Date
Clifford Wolf
2c7fe42ad1 Add "rename -output" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 13:47:42 +01:00
Clifford Wolf
d351b7cb99 Improve "rename" help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-27 13:33:26 +01:00
Scott Mansell
62c90c4e17 Rename cells based on the wires they drive. 2019-01-06 19:00:16 +13:00
whitequark
a9baee4b24 rename: add -src, for inferring names from source locations. 2018-12-05 20:35:13 +00:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes. 
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
 2018-07-20 23:51:06 -07:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
caa274ada6 Added design->rename(module, new_name) 2015-06-30 01:37:59 +02:00
Clifford Wolf
99100f367d Added "rename -top new_name" 2015-06-17 09:38:56 +02:00
Clifford Wolf
f889e3d385 Fixed iterator invalidation bug in "rename" command 2015-02-09 00:18:36 +01:00
Clifford Wolf
a6c96b986b Added Yosys::{dict,nodict,vector} container types 2014-12-26 10:53:21 +01:00
Clifford Wolf
d92fb5b35e Added missing fixup_ports() calls to "rename" command 2014-11-08 12:38:48 +01:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
084685f480 Implemented "rename -enumerate -pattern" 2014-08-26 12:51:08 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf
456ae31a8a Added "rename -hide" command 2014-01-02 20:23:34 +01:00
Clifford Wolf
e729857647 Improved handling of private names in opt_clean and rename commands 2013-08-07 18:39:49 +02:00
Clifford Wolf
a6aeb3dbf0 Added renaming of wires and cells to "rename" command 2013-06-19 16:55:43 +02:00
Clifford Wolf
95e937438f Added "rename" command 2013-06-10 12:37:22 +02:00