Eddie Hung
dd7d2d8db6
Duplicate tribuf call, credit to @mwkmwkmwk
2019-12-13 08:51:05 -08:00
Eddie Hung
8925bf4b96
Add RAM32X6SDP and RAM64X3SDP modes
2019-12-12 18:52:28 -08:00
Eddie Hung
50e0c83560
Fix RAM64M model to have 6 bit address bus
2019-12-12 18:52:03 -08:00
Eddie Hung
7a9d1be97d
Add memory rules for RAM16X1D, RAM32M, RAM64M
2019-12-12 17:44:59 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
9ab1feeaf1
abc9_map.v: fix Xilinx LUTRAM
2019-12-12 14:56:52 -08:00
Eddie Hung
3eed8835b5
abc9_map.v: fix Xilinx LUTRAM
2019-12-12 14:56:15 -08:00
Eddie Hung
3bd623bb05
synth_xilinx: error out if tristate without '-iopad'
2019-12-12 14:33:33 -08:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Diego H
ab6ac8327f
Merge https://github.com/YosysHQ/yosys into bram_xilinx
2019-12-12 13:40:05 -06:00
Eddie Hung
49c2e59b2a
Fix comment
2019-12-09 15:44:19 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
98c9ea605b
techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
2019-12-06 17:05:02 -08:00
Eddie Hung
c767525441
Remove creation of $abc9_control_wire
2019-12-06 16:23:09 -08:00
Eddie Hung
ec0acc9f85
abc9 to use mergeability class to differentiate sync/async
2019-12-06 00:12:37 -08:00
Eddie Hung
02786b0aa0
Remove clkpart
2019-12-05 17:25:26 -08:00
Eddie Hung
864bff14f1
Revert "Special abc9_clock wire to contain only clock signal"
...
This reverts commit 6a2eb5d8f9
2019-12-05 11:11:53 -08:00
Eddie Hung
0d248dd7ba
Missing wire declaration
2019-12-04 23:04:40 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Eddie Hung
258a34e6f1
Oh deary me
2019-12-04 20:33:24 -08:00
Eddie Hung
b43986c5a1
output reg Q -> output Q to suppress warning
2019-12-04 16:34:34 -08:00
Eddie Hung
31ef4cc704
abc9_map.v to do `zinit' and make INIT = 1'b0
2019-12-04 16:11:02 -08:00
Marcin Kościelnicki
fcce94010f
xilinx: Add tristate buffer mapping. ( #1528 )
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Fixes #1225 .
2019-12-04 09:44:00 +01:00
Marcin Kościelnicki
10014e2643
xilinx: Add models for LUTRAM cells. ( #1537 )
2019-12-04 06:31:09 +01:00
Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
Eddie Hung
f98aa1c13f
Revert "Add INIT value to abc9_control"
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This reverts commit 19bfb41958
2019-12-03 15:40:44 -08:00
Eddie Hung
0add5965c7
techmap abc_unmap.v before xilinx_srl -fixed
2019-12-03 14:27:45 -08:00
Eddie Hung
19bfb41958
Add INIT value to abc9_control
2019-12-02 14:17:06 -08:00
Marcin Kościelnicki
2badaa9adb
xilinx: Add missing blackbox cell for BUFPLL.
2019-11-29 16:56:27 +01:00
Eddie Hung
b1ab7c16c4
clkpart -unpart into 'finalize'
2019-11-28 12:59:43 -08:00
Diego H
3a5a65829c
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
2019-11-27 12:05:04 -06:00
Eddie Hung
df8dc6d1fb
ean call after abc{,9}
2019-11-27 09:10:34 -08:00
Eddie Hung
f6c0ec1d09
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
2019-11-27 01:03:33 -08:00
Eddie Hung
739f530906
Move 'clean' from map_luts to finalize
2019-11-26 14:51:39 -08:00
Marcin Kościelnicki
0466c48533
xilinx: Add simulation models for IOBUF and OBUFT.
2019-11-26 08:15:20 +01:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Eddie Hung
6a2eb5d8f9
Special abc9_clock wire to contain only clock signal
2019-11-25 12:36:13 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Eddie Hung
eb11c06a69
For abc9, run clkpart before ff_map and after abc9
2019-11-23 10:18:22 -08:00
Eddie Hung
5a30e3ac3b
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 16:15:25 -08:00
Eddie Hung
af3055fe83
Add blackbox model for $__ABC9_FF_ so that clock partitioning works
2019-11-20 14:30:56 -08:00
Eddie Hung
df63d75ff3
Fix INIT values
2019-11-20 11:26:59 -08:00
Eddie Hung
344619079d
Do not drop async control signals in abc_map.v
2019-11-19 16:57:07 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
7a9081440c
xilinx: Add simulation models for MULT18X18* and DSP48A*.
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This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
2019-11-19 01:00:58 +01:00
Marcin Kościelnicki
c4bd318e76
synth_xilinx: Merge blackbox primitive libraries.
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
David Shah
3506eaf290
xilinx: Add URAM288 mapping for xcup
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:44 +01:00
David Shah
6769d31ddb
xilinx: Add support for UltraScale[+] BRAM mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
Marcin Kościelnicki
7b350cacd4
xilinx: Support multiplier mapping for all families.
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This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
