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32 commits

Author SHA1 Message Date
Marcelina Kościelnicka
cf60699884 synth_ice40: Use opt_dff.
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.

The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
2020-07-30 22:26:20 +02:00
Marcelina Kościelnicka
1fc8c3a0d1 ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
Eddie Hung
4a10c87ae1 ice40: split out cells_map.v into ff_map.v 2020-05-14 10:33:56 -07:00
Eddie Hung
fb60d82971 ice40: move over to specify blocks for -abc9 2020-02-27 10:17:29 -08:00
Sean Cross
82f60ba938 Makefile: don't assume python is called python3
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`.  The build system assumes
that python is called `python3`, which breaks under this architecture.

There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS.  Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.

Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Eddie Hung
aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung
9fef1df3c1 Panic over. Model was elsewhere. Re-arrange for consistency 2019-10-04 10:48:44 -07:00
Eddie Hung
b7a48e3e0f Merge remote-tracking branch 'origin/master' into xc7dsp 2019-08-20 20:18:17 -07:00
Eddie Hung
12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
2019-08-12 12:06:45 -07:00
David Shah
f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung
2c0be7aa5d Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing 2019-08-08 12:56:05 -07:00
Eddie Hung
ea8ac8fd74 Remove ice40_unlut 2019-08-07 16:29:38 -07:00
Eddie Hung
9278192efe Also update Makefile.inc 2019-04-18 09:58:34 -07:00
Eddie Hung
8fd455c910 Update Makefile.inc too 2019-04-17 15:19:48 -07:00
Eddie Hung
6f3e5297db Add "-device" argument to synth_ice40 2019-04-17 15:04:46 -07:00
Eddie Hung
1eade06671 Also update Makefile.inc 2019-04-17 12:27:02 -07:00
Eddie Hung
7980118d74 Add ice40 box files 2019-04-16 16:39:30 -07:00
Sylvain Munaut
e71055cfe8 ice40: Add ice40_braminit pass to allow initialization of BRAM from file
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2019-03-08 00:15:46 +01:00
whitequark
1719aa88ac Extract ice40_unlut pass from ice40_opt.
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Clifford Wolf
6fe3d5a1cf Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Clifford Wolf
0793f1b196 Added ice40_ffinit pass 2015-11-26 18:11:06 +01:00
Clifford Wolf
c475deec6c Switched to Python 3 2015-08-22 09:59:33 +02:00
Clifford Wolf
9596fe74de Another bugfix for ice40 and xilinx brams_init make rules 2015-08-16 21:39:34 +02:00
Clifford Wolf
aedcfd6fd3 Fixed Makefile rules for generated share files 2015-08-16 21:15:07 +02:00
Clifford Wolf
e4ef000b70 Adjust makefiles to work with out-of-tree builds
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
61512b6f41 Verific build fixes 2015-05-17 08:19:52 +02:00
Clifford Wolf
8d4a675f91 Added iCE40 const folding support for SB_CARRY 2015-04-27 08:38:14 +02:00
Clifford Wolf
752851954b Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Clifford Wolf
d6f7698f59 Added ice40 bram support 2015-04-24 00:06:50 +02:00
Clifford Wolf
f78fa718be Added ice40 SB_CARRY support 2015-04-18 09:33:08 +02:00
Clifford Wolf
661b647559 Added mapping of synchronous set/reset to iCE40 flow 2015-04-17 11:54:25 +02:00
Clifford Wolf
42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00