Merge branch 'main' into nella/latch-toggle

tests/various/attrib05_port_conn.v

@@ -18,4 +18,3 @@ module foo(clk, rst, inp, out);
 
   bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
 endmodule
-

tests/various/attrib07_func_call.v

@@ -18,4 +18,3 @@ module foo(clk, rst, inp_a, inp_b, out);
     else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
 
 endmodule
-

tests/various/bug1531.ys

@@ -6,7 +6,7 @@ module top (y, clk, w);
    always @(posedge clk)
      // If the constant below is set to 2'b00, the correct output is generated.
      //       vvvv
-     for (i = 1'b0; i < 2'b01; i = i + 2'b01) 
+     for (i = 1'b0; i < 2'b01; i = i + 2'b01)
        y <= w || i[1:1];
 endmodule
 EOT

tests/various/bug1745.ys

@@ -3,6 +3,6 @@ read_verilog <<EOT
 module inverter(input a, output y);
 
    assign y = (a == 1'b0? 1'b1 : 1'b0);
-   
+
 endmodule // inverter
 EOT

tests/various/bug3515.ys

@@ -28,4 +28,3 @@ hierarchy -top mod_and_or
 opt
 extract -map ./bug3515.v
 select -assert-count 2 t:$and
-

tests/various/bug4865.ys

@@ -14,7 +14,7 @@ module \main
   wire width 12 $delete_wire$514
 
   wire width 4 $test
-  
+
   attribute \module_not_derived 1
   cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
     parameter \A_REG 1'0

tests/various/bug4909.ys

@@ -41,4 +41,3 @@ EOF
 
 prep
 splitcells
-

tests/various/check_4.ys

@@ -12,7 +12,7 @@ module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
 	wire arst = !data[0];
 
 	always @(posedge arst, posedge clk) begin
-		if (arst)		
+		if (arst)
 			data <= 4'hx;
 		else
 			data <= mem[addr];

tests/various/deminout_unused.ys

@@ -11,4 +11,3 @@ proc
 tribuf
 deminout
 select -assert-count 1 i:x o:x %i
-

tests/various/dynamic_part_select.ys

@@ -87,7 +87,7 @@ design -copy-from gate -as gate gate
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero equiv
 
-#### Double loop (part-select, reset) ### 
+#### Double loop (part-select, reset) ###
 design -reset
 read_verilog ./dynamic_part_select/reset_test.v
 proc
@@ -143,7 +143,7 @@ miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
 sat -prove-asserts -show-public -verify -set-init-zero equiv
 
 ###
-## Part select with obvious latch, expected to fail due comparison with old shift&mask AST transformation    
+## Part select with obvious latch, expected to fail due comparison with old shift&mask AST transformation
 design -reset
 read_verilog ./dynamic_part_select/latch_002.v
 hierarchy -top latch_002; prep; async2sync

tests/various/dynamic_part_select/latch_002.v

@@ -5,7 +5,7 @@ module latch_002
    input wire [7:0]  vect;
    input wire [7:0]  sel;
    input wire        st;
-   
+
    always @(*) begin
       if (st)
 	dword[8*sel +:8] <= vect[7:0];

tests/various/dynamic_part_select/latch_1990_gate.v

@@ -3,4 +3,3 @@ module latch_1990_gate
   (output wire [1:0] x);
    assign x = 2'b10;
 endmodule // latch_1990_gate
-

tests/various/dynamic_part_select/multiple_blocking.v

@@ -5,7 +5,7 @@ module multiple_blocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW
     input wire [DINW-1:0]  din,
     input wire [SELW-1:0]  sel,
     output reg [WIDTH-1:0] dout);
-   
+
    localparam SLICE = WIDTH/(SELW**2);
    reg [CTRLW:0] 	   a;
    reg [SELW-1:0] 	   b;

tests/various/dynamic_part_select/nonblocking.v

@@ -5,11 +5,11 @@ module nonblocking #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SE
     input wire [DINW-1:0]  din,
     input wire [SELW-1:0]  sel,
     output reg [WIDTH-1:0] dout);
-   
+
    localparam SLICE = WIDTH/(SELW**2);
    always @(posedge clk) begin
       dout <= dout + 1;
       dout[ctrl*sel+:SLICE] <= din ;
    end
-   
+
 endmodule

tests/various/dynamic_part_select/reset_test.v

@@ -6,7 +6,7 @@ module reset_test  #(parameter WIDTH=32, SELW=1, CTRLW=$clog2(WIDTH), DINW=2**SE
     input wire [DINW-1:0]  din,
     input wire [SELW-1:0]  sel,
     output reg [WIDTH-1:0] dout);
-   
+
    reg [SELW:0] 		   i;
    wire [SELW-1:0] 	   rval = {reset, {SELW-1{1'b0}}};
    localparam SLICE = WIDTH/(SELW**2);

tests/various/dynamic_part_select/reversed.v

@@ -5,10 +5,9 @@ module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW)
     input wire [DINW-1:0]  din,
     input wire [SELW-1:0]  sel,
     output reg [WIDTH-1:0] dout);
-   
+
    localparam SLICE = WIDTH/(SELW**2);
    always @(posedge clk) begin
       dout[(WIDTH-ctrl*sel)-:SLICE] <= din;
    end
 endmodule
-

tests/various/equiv_opt_undef.ys

@@ -24,7 +24,7 @@ module \top
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $b 
+    connect \A $b
     connect \B 1'x
     connect \Y \Q
   end

tests/various/fsm-arst.ys

@@ -55,7 +55,7 @@ module semi_self_rs_fsm (
                 reset_test = reset_test + 1;
         end
     end
-    
+
 
     always @(*) begin
         next_state = current_state;
@@ -108,7 +108,7 @@ opt_clean
 check
 opt -nodffe -nosdff
 
-fsm_detect 
+fsm_detect
 fsm_extract
 
 cd non_self_rs_fsm

tests/various/muxcover_index.ys

@@ -0,0 +1,87 @@
+# https://github.com/YosysHQ/yosys/issues/964
+
+read_verilog -formal <<EOT
+module mux_index_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+	assign o = i[s*W+:W];
+endmodule
+EOT
+
+prep
+design -save gold
+
+opt
+peepopt
+techmap
+opt
+muxcover -mux8
+clean
+opt_expr -mux_bool
+
+select -assert-count 2 t:$_MUX8_
+select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_
+select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_
+
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts miter
+
+design -reset
+read_verilog -formal <<EOT
+module mux_index_8_3 #(parameter N=8, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+	assign o = i[s*W+:W];
+endmodule
+EOT
+
+prep
+design -save gold
+
+opt
+peepopt
+techmap
+opt
+muxcover -mux8
+clean
+opt_expr -mux_bool
+
+select -assert-count 3 t:$_MUX8_
+select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_
+select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_
+
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts miter
+
+design -reset
+read_verilog -formal <<EOT
+module mux_index_8_4 #(parameter N=8, parameter W=4) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+	assign o = i[s*W+:W];
+endmodule
+EOT
+
+prep
+design -save gold
+
+opt
+peepopt
+techmap
+opt
+muxcover -mux8
+clean
+opt_expr -mux_bool
+
+select -assert-count 4 t:$_MUX8_
+select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_
+select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_
+
+techmap -map +/simcells.v t:$_MUX8_
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts miter

tests/various/muxpack.v

@@ -20,8 +20,8 @@ endmodule
 
 module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
 always @*
-    if (s != 0) 
-	   	if (s != 1) 
+    if (s != 0)
+	   	if (s != 1)
 			if (s != 2)
 				if (s != 3)
 					if (s != 4) o <= i[4*W+:W];

tests/various/reg_wire_error.sv

@@ -71,4 +71,3 @@ begin
 end
 
 endmodule
-

tests/various/scopeinfo.ys

@@ -107,4 +107,4 @@ select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module
 select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i
 select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i
 select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i
-select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i
+select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i

tests/various/shregmap.v

@@ -16,7 +16,7 @@ module $__SHREG_DFF_P_(input C, D, output Q);
 parameter DEPTH = 2;
 parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
 reg [DEPTH-1:0] r = INIT;
-always @(posedge C) 
+always @(posedge C)
     r <= { r[DEPTH-2:0], D };
 assign Q = r[DEPTH-1];
 endmodule

tests/various/sim_const.ys

@@ -10,4 +10,3 @@ EOT
 proc
 sim -clock clk -n 1 -w top
 select -assert-count 1 a:init=2'b10 top/q %i
-

tests/various/stat.ys

@@ -72,7 +72,7 @@ end
 EOT
 logger -expect log "Chip area for top module '\\top': 112.492800" 1
 logger -expect log "of which used for sequential elements: 94.348800" 1
-logger -expect log "2   18.144 cells" 1 
+logger -expect log "2   18.144 cells" 1
 logger -expect log "4  112.493 cells" 1
 logger -expect log "2   94.349   sg13g2_dfrbp_1" 1
 logger -expect-no-warnings

tests/various/stat_hierarchy.ys

@@ -52,11 +52,9 @@ module \child
 
 end
 EOT
-logger -expect log "4  112.493        2   18.144 cells" 2 
+logger -expect log "4  112.493        2   18.144 cells" 2
 logger -expect log "2   18.144        2   18.144   sg13g2_and2_1" 2
 logger -expect log "2   94.349        -        -   sg13g2_dfrbp_1" 2
 logger -expect log "2   94.349        2        - submodules" 2
 logger -expect-no-warnings
 stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top -hierarchy
-
-

tests/various/stat_high_level.ys

@@ -88,5 +88,3 @@ logger -expect log "2       51        -        -   \$reduce_xor" 2
 logger -expect log "8       66        2        5 cells" 2
 logger -expect-no-warnings
 stat -liberty ./stat_area_by_width.lib -top \top -hierarchy
-
-

tests/various/stat_high_level2.ys

@@ -87,5 +87,3 @@ logger -expect log "3     37.5        3     37.5 cells" 1
 logger -expect log "8       80        2        5 cells" 2
 logger -expect-no-warnings
 stat -liberty ./stat_area_by_width.lib -top \top -hierarchy
-
-