From cdc728b6f009ba9faa9829e26332f428896a0b77 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 20 Feb 2026 09:33:51 -0800 Subject: [PATCH 001/101] Suggest use of YW when possible --- passes/sat/sim.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 27d6d12c1..5392cd9e5 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2624,6 +2624,7 @@ struct SimPass : public Pass { log(" -r \n"); log(" read simulation or formal results file\n"); log(" File formats supported: FST, VCD, AIW, WIT and .yw\n"); + log(" Yosys witness (.yw) replay is preferred when possible.\n"); log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -width \n"); From b454582f540753343524d33e7d2e3ad8ca95972b Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Fri, 20 Feb 2026 11:00:59 -0800 Subject: [PATCH 002/101] Detect undriven and error/warn --- passes/sat/sim.cc | 81 ++++++++++++++++++++++++++++++++--- tests/sim/undriven_replay.v | 7 +++ tests/sim/undriven_replay.vcd | 15 +++++++ tests/sim/undriven_replay.ys | 10 +++++ 4 files changed, 108 insertions(+), 5 deletions(-) create mode 100644 tests/sim/undriven_replay.v create mode 100644 tests/sim/undriven_replay.vcd create mode 100644 tests/sim/undriven_replay.ys diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 5392cd9e5..bd723f5f1 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -26,6 +26,7 @@ #include "kernel/yw.h" #include "kernel/json.h" #include "kernel/fmt.h" +#include "kernel/drivertools.h" #include @@ -125,6 +126,8 @@ struct SimShared bool serious_asserts = false; bool fst_noinit = false; bool initstate = true; + bool undriven_check = true; + bool undriven_warning = false; }; void zinit(Const &v) @@ -426,7 +429,7 @@ struct SimInstance Const value = builder.build(); if (shared->debug) - log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value)); + log("[%s] get %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); return value; } @@ -445,7 +448,7 @@ struct SimInstance } if (shared->debug) - log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value)); + log("[%s] set %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); return did_something; } @@ -1192,6 +1195,54 @@ struct SimInstance child.second->addAdditionalInputs(); } + // Preconditions / assumptions: + // 1) fst_handles is populated for this instance (0 handle means not in trace). + // 2) fst_inputs is finalized (top-level inputs + addAdditionalInputs() for $anyseq). + // 3) module has no processes (sim enforces proc-lowered input before this point). + // 4) sigmap is valid for per-bit queries on this instance. + // 5) shared->fst is active, i.e. this is called from FST/VCD replay flow. + int checkUndrivenReplaySignals() + { + int issue_count = 0; + bool has_replay_candidates = false; + + for (auto &item : fst_handles) + if (item.second != 0 && !fst_inputs.count(item.first)) { + has_replay_candidates = true; + break; + } + + if (has_replay_candidates) { + DriverMap drivermap(module->design); + drivermap.add(module); + + for (auto &item : fst_handles) { + Wire *wire = item.first; + if (item.second == 0 || fst_inputs.count(wire)) + continue; + + SigSpec undriven; + for (auto bit : sigmap(wire)) + if (bit.wire != nullptr && drivermap(DriveBit(bit)).is_none()) + undriven.append(bit); + + undriven.sort_and_unify(); + if (undriven.empty()) + continue; + + issue_count++; + std::string wire_name = scope + "." + RTLIL::unescape_id(wire->name); + log_warning("Input trace contains undriven signal `%s` (%s); values for this signal are not replayed from FST/VCD input.\n", + wire_name.c_str(), log_signal(undriven, true)); + } + } + + for (auto child : children) + issue_count += child.second->checkUndrivenReplaySignals(); + + return issue_count; + } + bool setInputs() { bool did_something = false; @@ -1248,7 +1299,7 @@ struct SimInstance } else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X for(int i=0;isim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X for(int i=0;iaddAdditionalInputs(); + if (undriven_check) { + int issue_count = top->checkUndrivenReplaySignals(); + if (issue_count > 0 && !undriven_warning) + log_cmd_error("Found %d undriven signal%s in the replay trace. Use -undriven-warn to continue or -no-undriven-check to disable this check.\n", + issue_count, issue_count == 1 ? "" : "s"); + } uint64_t startCount = 0; uint64_t stopCount = 0; @@ -2627,6 +2684,12 @@ struct SimPass : public Pass { log(" Yosys witness (.yw) replay is preferred when possible.\n"); log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); + log(" -no-undriven-check\n"); + log(" skip undriven-signal checks for FST/VCD replay\n"); + log("\n"); + log(" -undriven-warn\n"); + log(" downgrade undriven-signal replay errors to warnings\n"); + log("\n"); log(" -width \n"); log(" cycle width in generated simulation output (must be divisible by 2).\n"); log("\n"); @@ -2844,6 +2907,14 @@ struct SimPass : public Pass { worker.fst_noinit = true; continue; } + if (args[argidx] == "-no-undriven-check") { + worker.undriven_check = false; + continue; + } + if (args[argidx] == "-undriven-warn") { + worker.undriven_warning = true; + continue; + } if (args[argidx] == "-x") { worker.ignore_x = true; continue; diff --git a/tests/sim/undriven_replay.v b/tests/sim/undriven_replay.v new file mode 100644 index 000000000..501f438a1 --- /dev/null +++ b/tests/sim/undriven_replay.v @@ -0,0 +1,7 @@ +module undriven_replay ( + input wire in, + output wire out, + output wire undrv +); + assign out = in; +endmodule diff --git a/tests/sim/undriven_replay.vcd b/tests/sim/undriven_replay.vcd new file mode 100644 index 000000000..e9cc35ae5 --- /dev/null +++ b/tests/sim/undriven_replay.vcd @@ -0,0 +1,15 @@ +$version Yosys $end +$scope module undriven_replay $end +$var wire 1 ! in $end +$var wire 1 " out $end +$var wire 1 # undrv $end +$upscope $end +$enddefinitions $end +#0 +b0 ! +b0 " +b1 # +#10 +b1 ! +b1 " +b0 # diff --git a/tests/sim/undriven_replay.ys b/tests/sim/undriven_replay.ys new file mode 100644 index 000000000..9766a8d60 --- /dev/null +++ b/tests/sim/undriven_replay.ys @@ -0,0 +1,10 @@ +read_verilog undriven_replay.v +prep -top undriven_replay + +logger -expect error "Found 1 undriven signal in the replay trace" 1 +sim -r undriven_replay.vcd -scope undriven_replay -q + +logger -expect warning "Input trace contains undriven signal" 1 +sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn + +sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check From c0f1654028736cd88d2fa7cae5b0335371e8e866 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 23 Feb 2026 10:27:36 -0800 Subject: [PATCH 003/101] Expand test into three tests for three cases (1) no check, (2) check with warning, (3) check with error. Previously the single test was not testing all cases, as it was exiting after the first error. --- tests/sim/undriven_replay.ys | 5 ----- tests/sim/undriven_replay_nocheck.ys | 4 ++++ tests/sim/undriven_replay_warn.ys | 5 +++++ 3 files changed, 9 insertions(+), 5 deletions(-) create mode 100644 tests/sim/undriven_replay_nocheck.ys create mode 100644 tests/sim/undriven_replay_warn.ys diff --git a/tests/sim/undriven_replay.ys b/tests/sim/undriven_replay.ys index 9766a8d60..854a40049 100644 --- a/tests/sim/undriven_replay.ys +++ b/tests/sim/undriven_replay.ys @@ -3,8 +3,3 @@ prep -top undriven_replay logger -expect error "Found 1 undriven signal in the replay trace" 1 sim -r undriven_replay.vcd -scope undriven_replay -q - -logger -expect warning "Input trace contains undriven signal" 1 -sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn - -sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check diff --git a/tests/sim/undriven_replay_nocheck.ys b/tests/sim/undriven_replay_nocheck.ys new file mode 100644 index 000000000..dcb1cfc92 --- /dev/null +++ b/tests/sim/undriven_replay_nocheck.ys @@ -0,0 +1,4 @@ +read_verilog undriven_replay.v +prep -top undriven_replay + +sim -r undriven_replay.vcd -scope undriven_replay -q -no-undriven-check diff --git a/tests/sim/undriven_replay_warn.ys b/tests/sim/undriven_replay_warn.ys new file mode 100644 index 000000000..ca3b1937c --- /dev/null +++ b/tests/sim/undriven_replay_warn.ys @@ -0,0 +1,5 @@ +read_verilog undriven_replay.v +prep -top undriven_replay + +logger -expect warning "Input trace contains undriven signal" 1 +sim -r undriven_replay.vcd -scope undriven_replay -q -undriven-warn From 366f98ae25bf45be94a6ea8118abe431eb676bdf Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 23 Feb 2026 11:51:54 -0800 Subject: [PATCH 004/101] ADd clarification --- passes/sat/sim.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index bd723f5f1..ddc256384 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2685,7 +2685,7 @@ struct SimPass : public Pass { log(" VCD support requires vcd2fst external tool to be present\n"); log("\n"); log(" -no-undriven-check\n"); - log(" skip undriven-signal checks for FST/VCD replay\n"); + log(" skip undriven-signal checks for FST/VCD replay (can be expensive for large designs)\n"); log("\n"); log(" -undriven-warn\n"); log(" downgrade undriven-signal replay errors to warnings\n"); From 7d3e56523bf93fb3c63fc19de843278f38e43012 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 13 May 2026 16:25:15 +0200 Subject: [PATCH 005/101] Preserve param signedness across overrides. --- kernel/rtlil.cc | 9 +++++++++ kernel/rtlil.h | 2 ++ passes/cmds/setattr.cc | 1 + passes/hierarchy/hierarchy.cc | 8 ++++++-- tests/verilog/issue5745.ys | 18 ++++++++++++++++++ 5 files changed, 36 insertions(+), 2 deletions(-) create mode 100644 tests/verilog/issue5745.ys diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a99f0803e..1a7dc6b41 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -615,6 +615,15 @@ int RTLIL::Const::as_int_saturating(bool is_signed) const return as_int(is_signed); } +void RTLIL::Const::tag_bare_integer_const(const std::string &value) +{ + if (value.empty() || value.find('\'') != std::string::npos) + return; + size_t start = (value[0] == '-' || value[0] == '+') ? 1 : 0; + if (start < value.size() && std::all_of(value.begin() + start, value.end(), ::isdigit)) + flags |= RTLIL::CONST_FLAG_SIGNED; +} + int RTLIL::Const::get_min_size(bool is_signed) const { if (empty()) return 0; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b32f9ea76..e55caf35a 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1091,6 +1091,8 @@ public: // over/underflow, otherwise the max/min value for int depending on the sign. int as_int_saturating(bool is_signed = false) const; + void tag_bare_integer_const(const std::string &value); + std::string as_string(const char* any = "-") const; static Const from_string(const std::string &str); std::vector to_bits() const; diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 25d8fd34c..ef9bd0d34 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -41,6 +41,7 @@ struct setunset_t if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value)) log_cmd_error("Can't decode value '%s'!\n", set_value); value = sig_value.as_const(); + value.tag_bare_integer_const(set_value); } } }; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 416997bee..34cedfd34 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -985,7 +985,9 @@ struct HierarchyPass : public Pass { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) log_cmd_error("Can't decode value '%s'!\n", para.second); - top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + RTLIL::Const c = sig_value.as_const(); + c.tag_bare_integer_const(para.second); + top_parameters[RTLIL::escape_id(para.first)] = c; } } @@ -1073,7 +1075,9 @@ struct HierarchyPass : public Pass { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) log_cmd_error("Can't decode value '%s'!\n", para.second); - top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); + RTLIL::Const c = sig_value.as_const(); + c.tag_bare_integer_const(para.second); + top_parameters[RTLIL::escape_id(para.first)] = c; } top_mod = design->module(top_mod->derive(design, top_parameters)); diff --git a/tests/verilog/issue5745.ys b/tests/verilog/issue5745.ys new file mode 100644 index 000000000..938ead63a --- /dev/null +++ b/tests/verilog/issue5745.ys @@ -0,0 +1,18 @@ +# Issue #5745: chparam values are unsigned when using read_verilog frontend +# +# When chparam overrides a parameter value, the signed attribute is lost, +# causing signed comparisons to silently use unsigned logic. +# +# m = -32 (signed 9-bit), p2 = 11. Correct signed semantics: -32 < 11, so k = 1. +# Bug: chparam strips the signed attribute from p2. The $lt cell gets A_SIGNED=0, +# B_SIGNED=0, so the comparison treats m as unsigned (480 > 11), giving k = 0. + +read_verilog < Date: Wed, 13 May 2026 16:52:07 +0200 Subject: [PATCH 006/101] Make sure to apply correct signedness to loop vars. --- backends/verilog/verilog_backend.cc | 11 ++--- frontends/ast/simplify.cc | 29 ++++++++----- tests/verilog/for_loop_signed_index.ys | 56 ++++++++++++++++++++++++++ tests/verilog/issue4402.ys | 32 +++++++++++++++ 4 files changed, 112 insertions(+), 16 deletions(-) create mode 100644 tests/verilog/for_loop_signed_index.ys create mode 100644 tests/verilog/issue4402.ys diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 73ffcbf3e..d5f83aefc 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -456,21 +456,22 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) if (wire->attributes.count(ID::single_bit_vector)) range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset); } + std::string sign = wire->is_signed ? " signed" : ""; if (wire->port_input && !wire->port_output) - f << stringf("%s" "input%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "input%s%s %s;\n", indent, sign, range, id(wire->name)); if (!wire->port_input && wire->port_output) - f << stringf("%s" "output%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "output%s%s %s;\n", indent, sign, range, id(wire->name)); if (wire->port_input && wire->port_output) - f << stringf("%s" "inout%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "inout%s%s %s;\n", indent, sign, range, id(wire->name)); if (reg_wires.count(wire->name)) { - f << stringf("%s" "reg%s %s", indent, range, id(wire->name)); + f << stringf("%s" "reg%s%s %s", indent, sign, range, id(wire->name)); if (wire->attributes.count(ID::init)) { f << stringf(" = "); dump_const(f, wire->attributes.at(ID::init)); } f << stringf(";\n"); } else - f << stringf("%s" "wire%s %s;\n", indent, range, id(wire->name)); + f << stringf("%s" "wire%s%s %s;\n", indent, sign, range, id(wire->name)); #endif } diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 48a4291d2..3012a4ccf 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2619,21 +2619,27 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str); auto resolved = current_scope.at(init_ast->children[0]->str); - if (resolved->range_valid) { - int const_size = varbuf->range_left - varbuf->range_right; - int resolved_size = resolved->range_left - resolved->range_right; - if (const_size < resolved_size) { - for (int i = const_size; i < resolved_size; i++) - varbuf->bits.push_back(resolved->is_signed ? varbuf->bits.back() : State::S0); - varbuf->range_left = resolved->range_left; - varbuf->range_right = resolved->range_right; - varbuf->range_swapped = resolved->range_swapped; - varbuf->range_valid = resolved->range_valid; + auto apply_loop_var_type = [&resolved](std::unique_ptr &value) { + if (resolved->range_valid) { + int const_size = value->range_left - value->range_right; + int resolved_size = resolved->range_left - resolved->range_right; + if (const_size < resolved_size) { + for (int i = const_size; i < resolved_size; i++) + value->bits.push_back(resolved->is_signed ? value->bits.back() : State::S0); + value->range_left = resolved->range_left; + value->range_right = resolved->range_right; + value->range_swapped = resolved->range_swapped; + value->range_valid = resolved->range_valid; + } } - } + value->is_signed = resolved->is_signed; + }; + + apply_loop_var_type(varbuf); varbuf = std::make_unique(location, AST_LOCALPARAM, std::move(varbuf)); varbuf->str = init_ast->children[0]->str; + varbuf->is_signed = resolved->is_signed; AstNode *backup_scope_varbuf = current_scope[varbuf->str]; current_scope[varbuf->str] = varbuf.get(); @@ -2708,6 +2714,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (buf->type != AST_CONSTANT) input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type)); + apply_loop_var_type(buf); varbuf->children[0] = std::move(buf); } diff --git a/tests/verilog/for_loop_signed_index.ys b/tests/verilog/for_loop_signed_index.ys new file mode 100644 index 000000000..a2bde3395 --- /dev/null +++ b/tests/verilog/for_loop_signed_index.ys @@ -0,0 +1,56 @@ +# Regression test: when procedural for-loops are unrolled, the constant +# replacement for the loop variable must keep the variable's declared +# signedness. + +read_verilog < y=0 +# Post-synthesis (unfixed): wire0 loses signed, 1<=0 false -> y=1 (BUG) +# Post-synthesis (fixed): wire0 retains signed, -1<=0 true -> y=0 + +! mkdir -p temp + +read_verilog < Date: Tue, 19 May 2026 12:16:29 +0200 Subject: [PATCH 007/101] Don't repeat VCD warnings + fixups. --- passes/sat/sim.cc | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index ddc256384..2b2982ceb 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -429,7 +429,7 @@ struct SimInstance Const value = builder.build(); if (shared->debug) - log("[%s] get %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); + log("[%s] get %s: %s\n", hiername(), log_signal(sig), log_signal(value, true)); return value; } @@ -448,7 +448,7 @@ struct SimInstance } if (shared->debug) - log("[%s] set %s: %s\n", hiername(), log_signal(sig, true), log_signal(value, true)); + log("[%s] set %s: %s\n", hiername(), log_signal(sig), log_signal(value, true)); return did_something; } @@ -1201,7 +1201,7 @@ struct SimInstance // 3) module has no processes (sim enforces proc-lowered input before this point). // 4) sigmap is valid for per-bit queries on this instance. // 5) shared->fst is active, i.e. this is called from FST/VCD replay flow. - int checkUndrivenReplaySignals() + int checkUndrivenReplaySignals(bool &any_undriven_found) { int issue_count = 0; bool has_replay_candidates = false; @@ -1231,14 +1231,14 @@ struct SimInstance continue; issue_count++; + any_undriven_found = true; std::string wire_name = scope + "." + RTLIL::unescape_id(wire->name); - log_warning("Input trace contains undriven signal `%s` (%s); values for this signal are not replayed from FST/VCD input.\n", - wire_name.c_str(), log_signal(undriven, true)); + log_warning("Input trace contains undriven signal `%s` (%s).\n", wire_name.c_str(), log_signal(undriven)); } } for (auto child : children) - issue_count += child.second->checkUndrivenReplaySignals(); + issue_count += child.second->checkUndrivenReplaySignals(any_undriven_found); return issue_count; } @@ -1550,7 +1550,10 @@ struct SimWorker : SimShared top->addAdditionalInputs(); if (undriven_check) { - int issue_count = top->checkUndrivenReplaySignals(); + bool any_undriven_found = false; + int issue_count = top->checkUndrivenReplaySignals(any_undriven_found); + if (any_undriven_found) + log_warning("Values for the undriven signal(s) listed above are not replayed from FST/VCD input.\n"); if (issue_count > 0 && !undriven_warning) log_cmd_error("Found %d undriven signal%s in the replay trace. Use -undriven-warn to continue or -no-undriven-check to disable this check.\n", issue_count, issue_count == 1 ? "" : "s"); From f69a5fc0779ba91eb92a6152dc33d29523e43347 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 29 Apr 2026 11:21:26 +0200 Subject: [PATCH 008/101] Elim equiv bits. --- passes/opt/opt_dff.cc | 284 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 283 insertions(+), 1 deletion(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 709b5fc4c..cc669f902 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -919,6 +919,286 @@ struct OptDffWorker return did_something; } + + struct EqBit { + Cell *cell; + int idx; + SigBit q; + }; + + struct SigKey { + enum Flag : uint16_t { + InitOne = 1u << 0, + InitX = 1u << 1, + PolClk = 1u << 2, + PolCe = 1u << 3, + PolSrst = 1u << 4, + PolArst = 1u << 5, + PolAload = 1u << 6, + PolClr = 1u << 7, + PolSet = 1u << 8, + CeOverSrst = 1u << 9, + }; + + SigBit clk, ce, srst, arst, aload, clr, set; + IdString cell_type; // for SR + uint16_t flags; + + bool operator==(const SigKey &o) const { + return flags == o.flags && clk == o.clk && ce == o.ce && srst == o.srst && arst == o.arst + && aload == o.aload && clr == o.clr && set == o.set && cell_type == o.cell_type; + } + + Hasher hash_into(Hasher h) const { + h.eat(flags); + h.eat(clk); + h.eat(ce); + h.eat(srst); + h.eat(arst); + h.eat(aload); + h.eat(clr); + h.eat(set); + h.eat(cell_type); + return h; + } + }; + + bool is_def(State s) { + return s == State::S0 || s == State::S1; + } + + int sat_mux(QuickConeSat &qcsat, int s, int a, int b) { + return qcsat.ez->OR(qcsat.ez->AND(s, a), qcsat.ez->AND(qcsat.ez->NOT(s), b)); + } + + int sat_const(QuickConeSat &qcsat, State v) { + return v == State::S1 ? qcsat.ez->CONST_TRUE : qcsat.ez->CONST_FALSE; + } + + bool run_eqbits() + { + std::vector bits; + std::vector keys; + dict ff_for_cell; + + // Collect FF bits eligible for merging + for (auto cell : module->selected_cells()) { + if (!cell->is_builtin_ff()) + continue; + + FfData ff(&initvals, cell); + if (!ff.has_clk && !ff.has_gclk) + continue; + + ff_for_cell.emplace(cell, ff); + + for (int i = 0; i < ff.width; i++) { + // X value + if (ff.has_srst && !is_def(ff.val_srst[i])) continue; + if (ff.has_arst && !is_def(ff.val_arst[i])) continue; + + // Missing anchor + bool def_init = is_def(ff.val_init[i]); + if (!def_init && !ff.has_srst && !ff.has_arst) + continue; + + SigKey k = {}; + + // Flags + if (def_init && ff.val_init[i] == State::S1) + k.flags |= SigKey::InitOne; + else if (!def_init) + k.flags |= SigKey::InitX; + + if (ff.has_clk) { + k.clk = ff.sig_clk; + if (ff.pol_clk) k.flags |= SigKey::PolClk; + } + if (ff.has_ce) { + k.ce = ff.sig_ce; + if (ff.pol_ce) k.flags |= SigKey::PolCe; + } + if (ff.has_srst) { + k.srst = ff.sig_srst; + if (ff.pol_srst) k.flags |= SigKey::PolSrst; + if (ff.ce_over_srst) k.flags |= SigKey::CeOverSrst; + } + if (ff.has_arst) { + k.arst = ff.sig_arst; + if (ff.pol_arst) k.flags |= SigKey::PolArst; + } + if (ff.has_aload) { + k.aload = ff.sig_aload; + if (ff.pol_aload) k.flags |= SigKey::PolAload; + } + if (ff.has_sr) { + k.clr = ff.sig_clr[i]; + k.set = ff.sig_set[i]; + k.cell_type = cell->type; + if (ff.pol_clr) k.flags |= SigKey::PolClr; + if (ff.pol_set) k.flags |= SigKey::PolSet; + } + + bits.push_back({cell, i, ff.sig_q[i]}); + keys.push_back(k); + } + } + + if (GetSize(bits) < 2) + return false; + + // Group bits by control signature + dict> buckets; + for (int i = 0; i < GetSize(bits); i++) + buckets[keys[i]].push_back(i); + + std::vector> classes; + classes.reserve(GetSize(buckets)); + for (auto &kv : buckets) + if (GetSize(kv.second) >= 2) + classes.push_back(std::move(kv.second)); + + if (classes.empty()) + return false; + + ModWalker modwalker(module->design, module); + QuickConeSat qcsat(modwalker); + std::vector q_lit(bits.size(), -1); + std::vector n_lit(bits.size(), -1); + + // Per candidate SAT for its next state, model difference + for (auto &cls : classes) { + for (int idx : cls) { + const EqBit &eb = bits[idx]; + const FfData &ff = ff_for_cell.at(eb.cell); + q_lit[idx] = qcsat.importSigBit(eb.q); + int n = qcsat.importSigBit(ff.sig_d[eb.idx]); + + if (ff.has_aload) { + int al = qcsat.importSigBit(ff.sig_aload); + if (!ff.pol_aload) al = qcsat.ez->NOT(al); + int ad = qcsat.importSigBit(ff.sig_ad[eb.idx]); + n = sat_mux(qcsat, al, ad, n); + } + if (ff.has_arst) { + int ar = qcsat.importSigBit(ff.sig_arst); + if (!ff.pol_arst) ar = qcsat.ez->NOT(ar); + n = sat_mux(qcsat, ar, sat_const(qcsat, ff.val_arst[eb.idx]), n); + } + if (ff.has_sr) { + int clr = qcsat.importSigBit(ff.sig_clr[eb.idx]); + if (!ff.pol_clr) clr = qcsat.ez->NOT(clr); + int set = qcsat.importSigBit(ff.sig_set[eb.idx]); + if (!ff.pol_set) set = qcsat.ez->NOT(set); + n = qcsat.ez->AND(qcsat.ez->NOT(clr), qcsat.ez->OR(set, n)); + } + if (ff.has_srst) { + int srst = qcsat.importSigBit(ff.sig_srst); + if (!ff.pol_srst) srst = qcsat.ez->NOT(srst); + n = sat_mux(qcsat,srst, sat_const(qcsat, ff.val_srst[eb.idx]), n); + } + + n_lit[idx] = n; + } + } + + qcsat.prepare(); + bool any_change = false; + bool changed = true; + + // Bit = class rep, split classes whenever two next states differ + while (changed) { + changed = false; + int joint = qcsat.ez->CONST_TRUE; + + for (auto &cls : classes) { + int rep = cls[0]; + for (int k = 1; k < GetSize(cls); k++) + joint = qcsat.ez->AND(joint, qcsat.ez->IFF(q_lit[rep], q_lit[cls[k]])); + } + + std::vector> new_classes; + new_classes.reserve(classes.size()); + + for (auto &cls : classes) { + std::vector> subs; + for (int b : cls) { + bool placed = false; + + // Identical literal - trivially eq + for (auto &sub : subs) { + if (n_lit[sub[0]] == n_lit[b]) { + sub.push_back(b); + placed = true; + break; + } + } + + if (placed) continue; + + for (auto &sub : subs) { + int rep = sub[0]; + int query = qcsat.ez->NOT(qcsat.ez->IFF(n_lit[rep], n_lit[b])); + if (!qcsat.ez->solve(joint, query)) { + sub.push_back(b); + placed = true; + break; + } + } + + if (!placed) + subs.push_back({b}); + } + + if (GetSize(subs) > 1) + changed = true; + for (auto &sub : subs) + if (GetSize(sub) >= 2) + new_classes.push_back(std::move(sub)); + } + + classes = std::move(new_classes); + if (changed) + any_change = true; + } + + if (classes.empty()) + return any_change; + + dict> remove_bits; + + // Drive every non-rep Q from its class rep, drop merged bits from their FFs + for (auto &cls : classes) { + SigBit rep_q = bits[cls[0]].q; + for (int k = 1; k < GetSize(cls); k++) { + const EqBit &eb = bits[cls[k]]; + initvals.remove_init(eb.q); + module->connect(eb.q, rep_q); + remove_bits[eb.cell].insert(eb.idx); + } + } + + for (auto &kv : remove_bits) { + Cell *cell = kv.first; + const std::set &drop = kv.second; + FfData &ff = ff_for_cell.at(cell); + std::vector keep; + + for (int i = 0; i < ff.width; i++) + if (!drop.count(i)) + keep.push_back(i); + + if (keep.empty()) { + module->remove(cell); + } else { + FfData new_ff = ff.slice(keep); + new_ff.cell = cell; + new_ff.emit(); + } + } + + return true; + } }; struct OptDffPass : public Pass { @@ -946,7 +1226,7 @@ struct OptDffPass : public Pass { log(" -simple-dffe\n"); log(" only enables clock enable recognition transform for obvious cases\n"); log("\n"); - log(" -sat\n"); + log(" -sat AAA\n"); log(" additionally invoke SAT solver to detect and remove flip-flops (with\n"); log(" non-constant inputs) that can also be replaced with a constant driver\n"); log("\n"); @@ -987,6 +1267,8 @@ struct OptDffPass : public Pass { did_something = true; if (worker.run_constbits()) did_something = true; + if (opt.sat && worker.run_eqbits()) + did_something = true; } if (did_something) From d85e3f10de301d1bd594042cf71a3d8f15cf4d8a Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 29 Apr 2026 15:55:45 +0200 Subject: [PATCH 009/101] Add tests. --- passes/opt/opt_dff.cc | 4 +- tests/opt/opt_dff_eqbits.ys | 56 ++++++++ tests/opt/opt_dff_eqbits_large.sv | 231 ++++++++++++++++++++++++++++++ tests/opt/opt_dff_eqbits_small.sv | 30 ++++ 4 files changed, 319 insertions(+), 2 deletions(-) create mode 100644 tests/opt/opt_dff_eqbits.ys create mode 100644 tests/opt/opt_dff_eqbits_large.sv create mode 100644 tests/opt/opt_dff_eqbits_small.sv diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index cc669f902..241ea6888 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -1095,7 +1095,7 @@ struct OptDffWorker if (ff.has_srst) { int srst = qcsat.importSigBit(ff.sig_srst); if (!ff.pol_srst) srst = qcsat.ez->NOT(srst); - n = sat_mux(qcsat,srst, sat_const(qcsat, ff.val_srst[eb.idx]), n); + n = sat_mux(qcsat, srst, sat_const(qcsat, ff.val_srst[eb.idx]), n); } n_lit[idx] = n; @@ -1226,7 +1226,7 @@ struct OptDffPass : public Pass { log(" -simple-dffe\n"); log(" only enables clock enable recognition transform for obvious cases\n"); log("\n"); - log(" -sat AAA\n"); + log(" -sat\n"); log(" additionally invoke SAT solver to detect and remove flip-flops (with\n"); log(" non-constant inputs) that can also be replaced with a constant driver\n"); log("\n"); diff --git a/tests/opt/opt_dff_eqbits.ys b/tests/opt/opt_dff_eqbits.ys new file mode 100644 index 000000000..10e9045e4 --- /dev/null +++ b/tests/opt/opt_dff_eqbits.ys @@ -0,0 +1,56 @@ +# small test case +design -reset +read_verilog -sv opt_dff_eqbits_small.sv +hierarchy -top test_case +techmap +opt_dff -sat +synth +opt_dff -sat +opt_clean -purge + +select -assert-count 2 t:$_SDFF_PN0_ + +# equivalence +design -reset +read_verilog -sv opt_dff_eqbits_small.sv +hierarchy -top test_case +prep +design -save gold + +opt_dff -sat +design -save gate + +design -copy-from gold -as gold test_case +design -copy-from gate -as gate test_case +equiv_make gold gate equiv +equiv_induct equiv +equiv_status -assert + + +# large test case +design -reset +read_verilog -sv opt_dff_eqbits_large.sv +hierarchy -top test_case +techmap +opt_dff -sat +synth +opt_dff -sat +opt_clean -purge + +select -assert-count 6 t:$_SDFFE_PN0P_ + +# equivalence +design -reset +read_verilog -sv opt_dff_eqbits_large.sv +hierarchy -top test_case +prep +design -save gold + +opt_dff -sat +design -save gate + +design -copy-from gold -as gold test_case +design -copy-from gate -as gate test_case +equiv_make gold gate equiv +equiv_induct equiv +equiv_status -assert diff --git a/tests/opt/opt_dff_eqbits_large.sv b/tests/opt/opt_dff_eqbits_large.sv new file mode 100644 index 000000000..4b32c7f8e --- /dev/null +++ b/tests/opt/opt_dff_eqbits_large.sv @@ -0,0 +1,231 @@ +module test_case ( + input wire clk, + input wire rst_n, + input wire [3:0] chan_0_data, + input wire chan_0_vld, + input wire chan_1_rdy, + output wire chan_0_rdy, + output wire [207:0] chan_1_data, + output wire chan_1_vld, + output wire idle +); + wire [12:0] state_init[0:15]; + assign state_init[0] = 13'h0000; + assign state_init[1] = 13'h0000; + assign state_init[2] = 13'h0000; + assign state_init[3] = 13'h0000; + assign state_init[4] = 13'h0000; + assign state_init[5] = 13'h0000; + assign state_init[6] = 13'h0000; + assign state_init[7] = 13'h0000; + assign state_init[8] = 13'h0000; + assign state_init[9] = 13'h0000; + assign state_init[10] = 13'h0000; + assign state_init[11] = 13'h0000; + assign state_init[12] = 13'h0000; + assign state_init[13] = 13'h0000; + assign state_init[14] = 13'h0000; + assign state_init[15] = 13'h0000; + + wire [12:0] ch1_init[0:15]; + assign ch1_init[0] = 13'h0000; + assign ch1_init[1] = 13'h0000; + assign ch1_init[2] = 13'h0000; + assign ch1_init[3] = 13'h0000; + assign ch1_init[4] = 13'h0000; + assign ch1_init[5] = 13'h0000; + assign ch1_init[6] = 13'h0000; + assign ch1_init[7] = 13'h0000; + assign ch1_init[8] = 13'h0000; + assign ch1_init[9] = 13'h0000; + assign ch1_init[10] = 13'h0000; + assign ch1_init[11] = 13'h0000; + assign ch1_init[12] = 13'h0000; + assign ch1_init[13] = 13'h0000; + assign ch1_init[14] = 13'h0000; + assign ch1_init[15] = 13'h0000; + + wire [12:0] mask_1fff[0:15]; + assign mask_1fff[0] = 13'h1fff; + assign mask_1fff[1] = 13'h1fff; + assign mask_1fff[2] = 13'h1fff; + assign mask_1fff[3] = 13'h1fff; + assign mask_1fff[4] = 13'h1fff; + assign mask_1fff[5] = 13'h1fff; + assign mask_1fff[6] = 13'h1fff; + assign mask_1fff[7] = 13'h1fff; + assign mask_1fff[8] = 13'h1fff; + assign mask_1fff[9] = 13'h1fff; + assign mask_1fff[10] = 13'h1fff; + assign mask_1fff[11] = 13'h1fff; + assign mask_1fff[12] = 13'h1fff; + assign mask_1fff[13] = 13'h1fff; + assign mask_1fff[14] = 13'h1fff; + assign mask_1fff[15] = 13'h1fff; + + reg [12:0] state_array[0:15]; + reg [3:0] ch0_in_buf; + reg ch0_in_buf_vld; + reg [12:0] ch1_out_buf[0:15]; + reg ch1_out_buf_vld; + reg stg1_vld; + + wire ch1_not_vld; + wire [3:0] ch0_sel_data; + wire ch0_is_vld; + wire ch1_vld_we; + wire ch1_data_we; + wire stg0_vld_out; + wire ch0_buf_ready; + wire ch0_pipe_stall; + wire [1:0] sel_concat; + wire ch0_buf_data_we; + wire ch0_buf_vld_rst; + wire stg0_idle; + wire stg1_idle; + wire ch0_is_inactive; + wire ch1_is_inactive; + wire [12:0] next_state_val[0:15]; + wire state_we; + wire ch0_buf_vld_we; + wire stg1_vld_we; + wire pipe_idle; + + assign ch1_not_vld = ~ch1_out_buf_vld; + assign ch0_sel_data = ch0_in_buf_vld ? ch0_in_buf : chan_0_data; + assign ch0_is_vld = chan_0_vld | ch0_in_buf_vld; + assign ch1_vld_we = chan_1_rdy | ch1_not_vld; + assign ch1_data_we = ch0_is_vld & ch1_vld_we; + assign stg0_vld_out = ch0_is_vld & ch1_data_we; + assign ch0_buf_ready = ~ch0_in_buf_vld; + assign ch0_pipe_stall = ~stg0_vld_out; + assign sel_concat = {ch0_is_vld & ch0_sel_data[0], ch0_is_vld & ~ch0_sel_data[0]}; + assign ch0_buf_data_we = chan_0_vld & ch0_buf_ready & ch0_pipe_stall; + assign ch0_buf_vld_rst = ch0_in_buf_vld & stg0_vld_out; + assign stg0_idle = ~ch0_is_vld; + assign stg1_idle = ~stg1_vld; + assign ch0_is_inactive = ~(chan_0_vld & ch0_buf_ready); + assign ch1_is_inactive = ~(ch1_out_buf_vld & chan_1_rdy); + + assign next_state_val[0] = state_array[0] & {13{sel_concat[0]}} | mask_1fff[0] & {13{sel_concat[1]}}; + assign next_state_val[1] = state_array[1] & {13{sel_concat[0]}} | mask_1fff[1] & {13{sel_concat[1]}}; + assign next_state_val[2] = state_array[2] & {13{sel_concat[0]}} | mask_1fff[2] & {13{sel_concat[1]}}; + assign next_state_val[3] = state_array[3] & {13{sel_concat[0]}} | mask_1fff[3] & {13{sel_concat[1]}}; + assign next_state_val[4] = state_array[4] & {13{sel_concat[0]}} | mask_1fff[4] & {13{sel_concat[1]}}; + assign next_state_val[5] = state_array[5] & {13{sel_concat[0]}} | mask_1fff[5] & {13{sel_concat[1]}}; + assign next_state_val[6] = state_array[6] & {13{sel_concat[0]}} | mask_1fff[6] & {13{sel_concat[1]}}; + assign next_state_val[7] = state_array[7] & {13{sel_concat[0]}} | mask_1fff[7] & {13{sel_concat[1]}}; + assign next_state_val[8] = state_array[8] & {13{sel_concat[0]}} | mask_1fff[8] & {13{sel_concat[1]}}; + assign next_state_val[9] = state_array[9] & {13{sel_concat[0]}} | mask_1fff[9] & {13{sel_concat[1]}}; + assign next_state_val[10] = state_array[10] & {13{sel_concat[0]}} | mask_1fff[10] & {13{sel_concat[1]}}; + assign next_state_val[11] = state_array[11] & {13{sel_concat[0]}} | mask_1fff[11] & {13{sel_concat[1]}}; + assign next_state_val[12] = state_array[12] & {13{sel_concat[0]}} | mask_1fff[12] & {13{sel_concat[1]}}; + assign next_state_val[13] = state_array[13] & {13{sel_concat[0]}} | mask_1fff[13] & {13{sel_concat[1]}}; + assign next_state_val[14] = state_array[14] & {13{sel_concat[0]}} | mask_1fff[14] & {13{sel_concat[1]}}; + assign next_state_val[15] = state_array[15] & {13{sel_concat[0]}} | mask_1fff[15] & {13{sel_concat[1]}}; + + assign state_we = stg0_vld_out & ch0_sel_data[0] | stg0_vld_out & ~ch0_sel_data[0]; + assign ch0_buf_vld_we = ch0_buf_data_we | ch0_buf_vld_rst; + assign stg1_vld_we = stg0_vld_out | stg1_vld; + assign pipe_idle = stg0_idle & stg1_idle & ch0_is_inactive & ch1_is_inactive; + + always @(posedge clk) begin + if (!rst_n) begin + state_array[0] <= state_init[0]; + state_array[1] <= state_init[1]; + state_array[2] <= state_init[2]; + state_array[3] <= state_init[3]; + state_array[4] <= state_init[4]; + state_array[5] <= state_init[5]; + state_array[6] <= state_init[6]; + state_array[7] <= state_init[7]; + state_array[8] <= state_init[8]; + state_array[9] <= state_init[9]; + state_array[10] <= state_init[10]; + state_array[11] <= state_init[11]; + state_array[12] <= state_init[12]; + state_array[13] <= state_init[13]; + state_array[14] <= state_init[14]; + state_array[15] <= state_init[15]; + ch0_in_buf <= 4'h0; + ch0_in_buf_vld <= 1'h0; + ch1_out_buf[0] <= ch1_init[0]; + ch1_out_buf[1] <= ch1_init[1]; + ch1_out_buf[2] <= ch1_init[2]; + ch1_out_buf[3] <= ch1_init[3]; + ch1_out_buf[4] <= ch1_init[4]; + ch1_out_buf[5] <= ch1_init[5]; + ch1_out_buf[6] <= ch1_init[6]; + ch1_out_buf[7] <= ch1_init[7]; + ch1_out_buf[8] <= ch1_init[8]; + ch1_out_buf[9] <= ch1_init[9]; + ch1_out_buf[10] <= ch1_init[10]; + ch1_out_buf[11] <= ch1_init[11]; + ch1_out_buf[12] <= ch1_init[12]; + ch1_out_buf[13] <= ch1_init[13]; + ch1_out_buf[14] <= ch1_init[14]; + ch1_out_buf[15] <= ch1_init[15]; + ch1_out_buf_vld <= 1'h0; + stg1_vld <= 1'h0; + end else begin + state_array[0] <= state_we ? next_state_val[0] : state_array[0]; + state_array[1] <= state_we ? next_state_val[1] : state_array[1]; + state_array[2] <= state_we ? next_state_val[2] : state_array[2]; + state_array[3] <= state_we ? next_state_val[3] : state_array[3]; + state_array[4] <= state_we ? next_state_val[4] : state_array[4]; + state_array[5] <= state_we ? next_state_val[5] : state_array[5]; + state_array[6] <= state_we ? next_state_val[6] : state_array[6]; + state_array[7] <= state_we ? next_state_val[7] : state_array[7]; + state_array[8] <= state_we ? next_state_val[8] : state_array[8]; + state_array[9] <= state_we ? next_state_val[9] : state_array[9]; + state_array[10] <= state_we ? next_state_val[10] : state_array[10]; + state_array[11] <= state_we ? next_state_val[11] : state_array[11]; + state_array[12] <= state_we ? next_state_val[12] : state_array[12]; + state_array[13] <= state_we ? next_state_val[13] : state_array[13]; + state_array[14] <= state_we ? next_state_val[14] : state_array[14]; + state_array[15] <= state_we ? next_state_val[15] : state_array[15]; + ch0_in_buf <= ch0_buf_data_we ? chan_0_data : ch0_in_buf; + ch0_in_buf_vld <= ch0_buf_vld_we ? ch0_buf_ready : ch0_in_buf_vld; + ch1_out_buf[0] <= ch1_data_we ? state_array[0] : ch1_out_buf[0]; + ch1_out_buf[1] <= ch1_data_we ? state_array[1] : ch1_out_buf[1]; + ch1_out_buf[2] <= ch1_data_we ? state_array[2] : ch1_out_buf[2]; + ch1_out_buf[3] <= ch1_data_we ? state_array[3] : ch1_out_buf[3]; + ch1_out_buf[4] <= ch1_data_we ? state_array[4] : ch1_out_buf[4]; + ch1_out_buf[5] <= ch1_data_we ? state_array[5] : ch1_out_buf[5]; + ch1_out_buf[6] <= ch1_data_we ? state_array[6] : ch1_out_buf[6]; + ch1_out_buf[7] <= ch1_data_we ? state_array[7] : ch1_out_buf[7]; + ch1_out_buf[8] <= ch1_data_we ? state_array[8] : ch1_out_buf[8]; + ch1_out_buf[9] <= ch1_data_we ? state_array[9] : ch1_out_buf[9]; + ch1_out_buf[10] <= ch1_data_we ? state_array[10] : ch1_out_buf[10]; + ch1_out_buf[11] <= ch1_data_we ? state_array[11] : ch1_out_buf[11]; + ch1_out_buf[12] <= ch1_data_we ? state_array[12] : ch1_out_buf[12]; + ch1_out_buf[13] <= ch1_data_we ? state_array[13] : ch1_out_buf[13]; + ch1_out_buf[14] <= ch1_data_we ? state_array[14] : ch1_out_buf[14]; + ch1_out_buf[15] <= ch1_data_we ? state_array[15] : ch1_out_buf[15]; + ch1_out_buf_vld <= ch1_vld_we ? ch0_is_vld : ch1_out_buf_vld; + stg1_vld <= stg1_vld_we ? stg0_vld_out : stg1_vld; + end + end + + assign chan_0_rdy = ch0_buf_ready; + assign chan_1_data = { + ch1_out_buf[15], + ch1_out_buf[14], + ch1_out_buf[13], + ch1_out_buf[12], + ch1_out_buf[11], + ch1_out_buf[10], + ch1_out_buf[9], + ch1_out_buf[8], + ch1_out_buf[7], + ch1_out_buf[6], + ch1_out_buf[5], + ch1_out_buf[4], + ch1_out_buf[3], + ch1_out_buf[2], + ch1_out_buf[1], + ch1_out_buf[0] + }; + assign chan_1_vld = ch1_out_buf_vld; + assign idle = pipe_idle; +endmodule diff --git a/tests/opt/opt_dff_eqbits_small.sv b/tests/opt/opt_dff_eqbits_small.sv new file mode 100644 index 000000000..7c6aeba7f --- /dev/null +++ b/tests/opt/opt_dff_eqbits_small.sv @@ -0,0 +1,30 @@ +module test_case ( + input wire clk, + input wire rst_n, + input wire in_val, + output wire out_a, + output wire out_b, + output wire out_c, + output wire out_d +); + reg a, b, c, d; + + always @(posedge clk) begin + if (!rst_n) begin + a <= 1'b0; + b <= 1'b0; + c <= 1'b0; + d <= 1'b0; + end else begin + a <= c & in_val; + b <= d & in_val; + c <= b | in_val; + d <= a | in_val; + end + end + + assign out_a = a; + assign out_b = b; + assign out_c = c; + assign out_d = d; +endmodule From c6bf13bb94ed8b3f5f7eee14eb67823f497f0e4a Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 13 May 2026 10:49:12 +0200 Subject: [PATCH 010/101] Implement worklist and SAT counterexample splitting. --- passes/opt/opt_dff.cc | 113 ++++++++++++++++++++++++------------------ 1 file changed, 65 insertions(+), 48 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 241ea6888..ef5c56896 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -1104,62 +1104,76 @@ struct OptDffWorker qcsat.prepare(); bool any_change = false; - bool changed = true; + std::vector worklist; + std::vector in_worklist(GetSize(classes), true); - // Bit = class rep, split classes whenever two next states differ - while (changed) { - changed = false; - int joint = qcsat.ez->CONST_TRUE; + for (int i = 0; i < GetSize(classes); i++) { + worklist.push_back(i); + } - for (auto &cls : classes) { - int rep = cls[0]; - for (int k = 1; k < GetSize(cls); k++) - joint = qcsat.ez->AND(joint, qcsat.ez->IFF(q_lit[rep], q_lit[cls[k]])); + while (!worklist.empty()) { + int cls_idx = worklist.back(); + worklist.pop_back(); + in_worklist[cls_idx] = false; + + auto &cls = classes[cls_idx]; + if (GetSize(cls) < 2) continue; + + std::vector assumptions; + for (auto &c : classes) { + if (GetSize(c) < 2) continue; + int rep = c[0]; + for (int k = 1; k < GetSize(c); k++) { + assumptions.push_back(qcsat.ez->IFF(q_lit[rep], q_lit[c[k]])); + } } - std::vector> new_classes; - new_classes.reserve(classes.size()); + // Split at counterexamples + int rep = cls[0]; + for (int i = 1; i < GetSize(cls); i++) { + // Trivially eqivalent + if (n_lit[rep] == n_lit[cls[i]]) + continue; + + int query = qcsat.ez->NOT(qcsat.ez->IFF(n_lit[rep], n_lit[cls[i]])); + std::vector modelExprs; - for (auto &cls : classes) { - std::vector> subs; for (int b : cls) { - bool placed = false; - - // Identical literal - trivially eq - for (auto &sub : subs) { - if (n_lit[sub[0]] == n_lit[b]) { - sub.push_back(b); - placed = true; - break; - } - } - - if (placed) continue; - - for (auto &sub : subs) { - int rep = sub[0]; - int query = qcsat.ez->NOT(qcsat.ez->IFF(n_lit[rep], n_lit[b])); - if (!qcsat.ez->solve(joint, query)) { - sub.push_back(b); - placed = true; - break; - } - } - - if (!placed) - subs.push_back({b}); + modelExprs.push_back(n_lit[b]); } - if (GetSize(subs) > 1) - changed = true; - for (auto &sub : subs) - if (GetSize(sub) >= 2) - new_classes.push_back(std::move(sub)); - } + std::vector modelVals; + assumptions.push_back(query); + + if (qcsat.ez->solve(modelExprs, modelVals, assumptions)) { + // SAT -> partition entire class + std::vector sub0; + std::vector sub1; - classes = std::move(new_classes); - if (changed) - any_change = true; + for (size_t b_idx = 0; b_idx < cls.size(); b_idx++) { + if (modelVals[b_idx]) + sub1.push_back(cls[b_idx]); + else + sub0.push_back(cls[b_idx]); + } + + classes[cls_idx] = std::move(sub0); + classes.push_back(std::move(sub1)); + in_worklist.push_back(false); + + // Partition was split -> the induction hypo weakened + for (int j = 0; j < GetSize(classes); j++) { + if (GetSize(classes[j]) >= 2 && !in_worklist[j]) { + worklist.push_back(j); + in_worklist[j] = true; + } + } + + break; // Process new splits + } + + assumptions.pop_back(); // Remove query for the next pairwise check if UNSAT + } } if (classes.empty()) @@ -1169,7 +1183,10 @@ struct OptDffWorker // Drive every non-rep Q from its class rep, drop merged bits from their FFs for (auto &cls : classes) { + if (GetSize(cls) < 2) + continue; SigBit rep_q = bits[cls[0]].q; + any_change = true; for (int k = 1; k < GetSize(cls); k++) { const EqBit &eb = bits[cls[k]]; initvals.remove_init(eb.q); @@ -1197,7 +1214,7 @@ struct OptDffWorker } } - return true; + return any_change; } }; From bbec8d2902d3bdf65fb90a99881a94c8dfed520b Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 20 May 2026 15:51:04 +0200 Subject: [PATCH 011/101] Gate behind flag. --- passes/opt/opt_dff.cc | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index ef5c56896..e657a8a2d 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -41,6 +41,7 @@ struct OptDffOptions bool simple_dffe; bool sat; bool keepdc; + bool eqbits; }; struct OptDffWorker @@ -977,6 +978,10 @@ struct OptDffWorker bool run_eqbits() { + if(!opt.eqbits) { + return false; + } + std::vector bits; std::vector keys; dict ff_for_cell; @@ -1253,6 +1258,11 @@ struct OptDffPass : public Pass { log(" all result bits to be set to x. this behavior changes when 'a+0' is\n"); log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n"); log("\n"); + log(" -eqbits\n"); + log(" finds groups of flip flop bits provably holding always-equal values\n"); + log(" across cycles and collapses each group to a single bit, potentially\n"); + log(" reducing the number of required flip flops.\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -1265,6 +1275,7 @@ struct OptDffPass : public Pass { opt.simple_dffe = false; opt.keepdc = false; opt.sat = false; + opt.eqbits = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -1273,6 +1284,7 @@ struct OptDffPass : public Pass { if (args[argidx] == "-simple-dffe") { opt.simple_dffe = true; continue; } if (args[argidx] == "-keepdc") { opt.keepdc = true; continue; } if (args[argidx] == "-sat") { opt.sat = true; continue; } + if (args[argidx] == "-eqbits") { opt.eqbits = true; continue; } break; } extra_args(args, argidx, design); @@ -1284,7 +1296,7 @@ struct OptDffPass : public Pass { did_something = true; if (worker.run_constbits()) did_something = true; - if (opt.sat && worker.run_eqbits()) + if (worker.run_eqbits()) did_something = true; } From 04a1611346afbd7ffbed8b4d625c674694a1f972 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 20 May 2026 15:58:27 +0200 Subject: [PATCH 012/101] Tests. --- tests/opt/opt_dff_eqbits.ys | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/opt/opt_dff_eqbits.ys b/tests/opt/opt_dff_eqbits.ys index 10e9045e4..181b5d0a7 100644 --- a/tests/opt/opt_dff_eqbits.ys +++ b/tests/opt/opt_dff_eqbits.ys @@ -3,9 +3,9 @@ design -reset read_verilog -sv opt_dff_eqbits_small.sv hierarchy -top test_case techmap -opt_dff -sat +opt_dff -sat -eqbits synth -opt_dff -sat +opt_dff -sat -eqbits opt_clean -purge select -assert-count 2 t:$_SDFF_PN0_ @@ -17,7 +17,7 @@ hierarchy -top test_case prep design -save gold -opt_dff -sat +opt_dff -sat -eqbits design -save gate design -copy-from gold -as gold test_case @@ -32,9 +32,9 @@ design -reset read_verilog -sv opt_dff_eqbits_large.sv hierarchy -top test_case techmap -opt_dff -sat +opt_dff -sat -eqbits synth -opt_dff -sat +opt_dff -sat -eqbits opt_clean -purge select -assert-count 6 t:$_SDFFE_PN0P_ @@ -46,7 +46,7 @@ hierarchy -top test_case prep design -save gold -opt_dff -sat +opt_dff -sat -eqbits design -save gate design -copy-from gold -as gold test_case From 386e63ae20465e401d749ffe160098e7be97f799 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 25 May 2026 12:49:29 +0200 Subject: [PATCH 013/101] Add prepass for bit simulation. --- kernel/bitsim.h | 79 +++++++++++++++++++++++++++++++++++++++++++ passes/opt/opt_dff.cc | 64 ++++++++++++++++++++++++++++++++++- 2 files changed, 142 insertions(+), 1 deletion(-) create mode 100644 kernel/bitsim.h diff --git a/kernel/bitsim.h b/kernel/bitsim.h new file mode 100644 index 000000000..a0915e28b --- /dev/null +++ b/kernel/bitsim.h @@ -0,0 +1,79 @@ +#ifndef BITSIM_H +#define BITSIM_H + +#include "kernel/modtools.h" + +YOSYS_NAMESPACE_BEGIN + +struct BitSim { + Module *module; + SigMap &sigmap; + ModWalker &modwalker; + dict sim_vals; + uint64_t rng_state; + + BitSim(Module *m, SigMap &sm, ModWalker &mw) + : module(m), sigmap(sm), modwalker(mw), rng_state(1337) {} + + uint64_t xorshift64() { + rng_state ^= rng_state << 13; + rng_state ^= rng_state >> 7; + rng_state ^= rng_state << 17; + return rng_state; + } + + uint64_t eval_bit(SigBit b) { + SigBit mapped = sigmap(b); + if (mapped == State::S0) return 0ULL; + if (mapped == State::S1) return ~0ULL; + if (mapped == State::Sx || mapped == State::Sz) return 0ULL; + + auto it = sim_vals.find(mapped); + if (it != sim_vals.end()) return it->second; + sim_vals[mapped] = 0; + uint64_t res = 0; + + if (!modwalker.has_drivers(mapped)) { + res = xorshift64(); + } else { + auto &drivers = modwalker.signal_drivers[mapped]; + if (drivers.empty()) { + res = xorshift64(); + } else { + auto driver = *drivers.begin(); + Cell *cell = driver.cell; + + if (cell->is_builtin_ff()) { + res = xorshift64(); + } else if (cell->type == ID($_AND_)) { + res = eval_bit(cell->getPort(ID::A)[0]) & eval_bit(cell->getPort(ID::B)[0]); + } else if (cell->type == ID($_OR_)) { + res = eval_bit(cell->getPort(ID::A)[0]) | eval_bit(cell->getPort(ID::B)[0]); + } else if (cell->type == ID($_XOR_)) { + res = eval_bit(cell->getPort(ID::A)[0]) ^ eval_bit(cell->getPort(ID::B)[0]); + } else if (cell->type == ID($_NOT_)) { + res = ~eval_bit(cell->getPort(ID::A)[0]); + } else if (cell->type == ID($_MUX_)) { + uint64_t s = eval_bit(cell->getPort(ID::S)[0]); + uint64_t a = eval_bit(cell->getPort(ID::A)[0]); + uint64_t b = eval_bit(cell->getPort(ID::B)[0]); + res = (a & ~s) | (b & s); + } else if (cell->type == ID($mux)) { + uint64_t s = eval_bit(cell->getPort(ID::S)[0]); + uint64_t a = eval_bit(cell->getPort(ID::A)[driver.offset]); + uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset]); + res = (a & ~s) | (b & s); + } else { + res = xorshift64(); + } + } + } + + sim_vals[mapped] = res; + return res; + } +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index e657a8a2d..dbe0e521a 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -26,6 +26,7 @@ #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" +#include "kernel/bitsim.h" #include "kernel/pattern.h" #include "passes/techmap/simplemap.h" #include @@ -1067,6 +1068,67 @@ struct OptDffWorker return false; ModWalker modwalker(module->design, module); + BitSim sim(module, sigmap, modwalker); + + // Simulation prepass + // Assume same class + for (auto &cls : classes) { + uint64_t class_q_val = sim.xorshift64(); + for (int idx : cls) { + sim.sim_vals[sigmap(bits[idx].q)] = class_q_val; + } + } + + std::vector> refined_classes; + + for (auto &cls : classes) { + dict> sim_buckets; + for (int idx : cls) { + const EqBit &eb = bits[idx]; + const FfData &ff = ff_for_cell.at(eb.cell); + + uint64_t n_val = sim.eval_bit(ff.sig_d[eb.idx]); + + if (ff.has_aload) { + uint64_t al = sim.eval_bit(ff.sig_aload); + if (!ff.pol_aload) al = ~al; + uint64_t ad = sim.eval_bit(ff.sig_ad[eb.idx]); + n_val = (n_val & ~al) | (ad & al); + } + if (ff.has_arst) { + uint64_t ar = sim.eval_bit(ff.sig_arst); + if (!ff.pol_arst) ar = ~ar; + uint64_t ar_val = (ff.val_arst[eb.idx] == State::S1) ? ~0ULL : 0ULL; + n_val = (n_val & ~ar) | (ar_val & ar); + } + if (ff.has_sr) { + uint64_t clr = sim.eval_bit(ff.sig_clr[eb.idx]); + if (!ff.pol_clr) clr = ~clr; + uint64_t set = sim.eval_bit(ff.sig_set[eb.idx]); + if (!ff.pol_set) set = ~set; + n_val = ~clr & (set | n_val); + } + if (ff.has_srst) { + uint64_t srst = sim.eval_bit(ff.sig_srst); + if (!ff.pol_srst) srst = ~srst; + uint64_t srst_val = (ff.val_srst[eb.idx] == State::S1) ? ~0ULL : 0ULL; + n_val = (n_val & ~srst) | (srst_val & srst); + } + + sim_buckets[n_val].push_back(idx); + } + + for (auto &kv : sim_buckets) { + if (GetSize(kv.second) >= 2) { + refined_classes.push_back(std::move(kv.second)); + } + } + } + + classes = std::move(refined_classes); + if (classes.empty()) + return false; + QuickConeSat qcsat(modwalker); std::vector q_lit(bits.size(), -1); std::vector n_lit(bits.size(), -1); @@ -1136,7 +1198,7 @@ struct OptDffWorker // Split at counterexamples int rep = cls[0]; for (int i = 1; i < GetSize(cls); i++) { - // Trivially eqivalent + // Trivially equivalent if (n_lit[rep] == n_lit[cls[i]]) continue; From 68df0be7d2ef7b3a0dd54abe469b81b9494a48e1 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 25 May 2026 14:16:55 +0200 Subject: [PATCH 014/101] Remove eqbits flag. --- passes/opt/opt_dff.cc | 106 ++++++++++++++++++++---------------- tests/opt/opt_dff_eqbits.ys | 12 ++-- 2 files changed, 64 insertions(+), 54 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index dbe0e521a..500df142e 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -42,7 +42,6 @@ struct OptDffOptions bool simple_dffe; bool sat; bool keepdc; - bool eqbits; }; struct OptDffWorker @@ -977,15 +976,9 @@ struct OptDffWorker return v == State::S1 ? qcsat.ez->CONST_TRUE : qcsat.ez->CONST_FALSE; } - bool run_eqbits() + std::vector> gather_initial_eq_classes(std::vector &bits, dict &ff_for_cell) { - if(!opt.eqbits) { - return false; - } - - std::vector bits; std::vector keys; - dict ff_for_cell; // Collect FF bits eligible for merging for (auto cell : module->selected_cells()) { @@ -1050,27 +1043,26 @@ struct OptDffWorker } } - if (GetSize(bits) < 2) - return false; - - // Group bits by control signature dict> buckets; for (int i = 0; i < GetSize(bits); i++) buckets[keys[i]].push_back(i); std::vector> classes; - classes.reserve(GetSize(buckets)); for (auto &kv : buckets) if (GetSize(kv.second) >= 2) classes.push_back(std::move(kv.second)); - if (classes.empty()) - return false; + return classes; + } - ModWalker modwalker(module->design, module); + std::vector> filter_classes_sim( + const std::vector> &classes, + const std::vector &bits, + const dict &ff_for_cell, + ModWalker &modwalker + ) { BitSim sim(module, sigmap, modwalker); - - // Simulation prepass + // Assume same class for (auto &cls : classes) { uint64_t class_q_val = sim.xorshift64(); @@ -1080,15 +1072,13 @@ struct OptDffWorker } std::vector> refined_classes; - for (auto &cls : classes) { dict> sim_buckets; for (int idx : cls) { const EqBit &eb = bits[idx]; const FfData &ff = ff_for_cell.at(eb.cell); - uint64_t n_val = sim.eval_bit(ff.sig_d[eb.idx]); - + if (ff.has_aload) { uint64_t al = sim.eval_bit(ff.sig_aload); if (!ff.pol_aload) al = ~al; @@ -1118,17 +1108,20 @@ struct OptDffWorker sim_buckets[n_val].push_back(idx); } - for (auto &kv : sim_buckets) { - if (GetSize(kv.second) >= 2) { + for (auto &kv : sim_buckets) + if (GetSize(kv.second) >= 2) refined_classes.push_back(std::move(kv.second)); - } - } } - classes = std::move(refined_classes); - if (classes.empty()) - return false; + return refined_classes; + } + std::vector> filter_classes_sat( + std::vector> classes, + const std::vector &bits, + const dict &ff_for_cell, + ModWalker &modwalker + ) { QuickConeSat qcsat(modwalker); std::vector q_lit(bits.size(), -1); std::vector n_lit(bits.size(), -1); @@ -1144,8 +1137,7 @@ struct OptDffWorker if (ff.has_aload) { int al = qcsat.importSigBit(ff.sig_aload); if (!ff.pol_aload) al = qcsat.ez->NOT(al); - int ad = qcsat.importSigBit(ff.sig_ad[eb.idx]); - n = sat_mux(qcsat, al, ad, n); + n = sat_mux(qcsat, al, qcsat.importSigBit(ff.sig_ad[eb.idx]), n); } if (ff.has_arst) { int ar = qcsat.importSigBit(ff.sig_arst); @@ -1170,13 +1162,11 @@ struct OptDffWorker } qcsat.prepare(); - bool any_change = false; std::vector worklist; std::vector in_worklist(GetSize(classes), true); - for (int i = 0; i < GetSize(classes); i++) { + for (int i = 0; i < GetSize(classes); i++) worklist.push_back(i); - } while (!worklist.empty()) { int cls_idx = worklist.back(); @@ -1190,9 +1180,8 @@ struct OptDffWorker for (auto &c : classes) { if (GetSize(c) < 2) continue; int rep = c[0]; - for (int k = 1; k < GetSize(c); k++) { + for (int k = 1; k < GetSize(c); k++) assumptions.push_back(qcsat.ez->IFF(q_lit[rep], q_lit[c[k]])); - } } // Split at counterexamples @@ -1204,14 +1193,12 @@ struct OptDffWorker int query = qcsat.ez->NOT(qcsat.ez->IFF(n_lit[rep], n_lit[cls[i]])); std::vector modelExprs; - - for (int b : cls) { + for (int b : cls) modelExprs.push_back(n_lit[b]); - } std::vector modelVals; assumptions.push_back(query); - + if (qcsat.ez->solve(modelExprs, modelVals, assumptions)) { // SAT -> partition entire class std::vector sub0; @@ -1243,9 +1230,12 @@ struct OptDffWorker } } - if (classes.empty()) - return any_change; + return classes; + } + bool apply_eq_merges(const std::vector> &classes, const std::vector &bits, dict &ff_for_cell) + { + bool any_change = false; dict> remove_bits; // Drive every non-rep Q from its class rep, drop merged bits from their FFs @@ -1283,6 +1273,33 @@ struct OptDffWorker return any_change; } + + bool run_eqbits() + { + if (!opt.sat) + return false; + + std::vector bits; + dict ff_for_cell; + + std::vector> classes = gather_initial_eq_classes(bits, ff_for_cell); + if (classes.empty()) + return false; + + ModWalker modwalker(module->design, module); + + // Simulation prepass + classes = filter_classes_sim(classes, bits, ff_for_cell, modwalker); + if (classes.empty()) + return false; + + // SAT prove + classes = filter_classes_sat(std::move(classes), bits, ff_for_cell, modwalker); + if (classes.empty()) + return false; + + return apply_eq_merges(classes, bits, ff_for_cell); + } }; struct OptDffPass : public Pass { @@ -1320,11 +1337,6 @@ struct OptDffPass : public Pass { log(" all result bits to be set to x. this behavior changes when 'a+0' is\n"); log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n"); log("\n"); - log(" -eqbits\n"); - log(" finds groups of flip flop bits provably holding always-equal values\n"); - log(" across cycles and collapses each group to a single bit, potentially\n"); - log(" reducing the number of required flip flops.\n"); - log("\n"); } void execute(std::vector args, RTLIL::Design *design) override @@ -1337,7 +1349,6 @@ struct OptDffPass : public Pass { opt.simple_dffe = false; opt.keepdc = false; opt.sat = false; - opt.eqbits = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -1346,7 +1357,6 @@ struct OptDffPass : public Pass { if (args[argidx] == "-simple-dffe") { opt.simple_dffe = true; continue; } if (args[argidx] == "-keepdc") { opt.keepdc = true; continue; } if (args[argidx] == "-sat") { opt.sat = true; continue; } - if (args[argidx] == "-eqbits") { opt.eqbits = true; continue; } break; } extra_args(args, argidx, design); diff --git a/tests/opt/opt_dff_eqbits.ys b/tests/opt/opt_dff_eqbits.ys index 181b5d0a7..10e9045e4 100644 --- a/tests/opt/opt_dff_eqbits.ys +++ b/tests/opt/opt_dff_eqbits.ys @@ -3,9 +3,9 @@ design -reset read_verilog -sv opt_dff_eqbits_small.sv hierarchy -top test_case techmap -opt_dff -sat -eqbits +opt_dff -sat synth -opt_dff -sat -eqbits +opt_dff -sat opt_clean -purge select -assert-count 2 t:$_SDFF_PN0_ @@ -17,7 +17,7 @@ hierarchy -top test_case prep design -save gold -opt_dff -sat -eqbits +opt_dff -sat design -save gate design -copy-from gold -as gold test_case @@ -32,9 +32,9 @@ design -reset read_verilog -sv opt_dff_eqbits_large.sv hierarchy -top test_case techmap -opt_dff -sat -eqbits +opt_dff -sat synth -opt_dff -sat -eqbits +opt_dff -sat opt_clean -purge select -assert-count 6 t:$_SDFFE_PN0P_ @@ -46,7 +46,7 @@ hierarchy -top test_case prep design -save gold -opt_dff -sat -eqbits +opt_dff -sat design -save gate design -copy-from gold -as gold test_case From d52670e58b3e886e07f2863da99195832edffca3 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 10 Jun 2026 11:29:55 +0200 Subject: [PATCH 015/101] Replace suitable (2^k-1)-x with ~x. --- passes/opt/opt_expr.cc | 50 ++++++++++++++++++++++++ tests/arch/xilinx/dynamic_upto_select.ys | 19 +++++++++ 2 files changed, 69 insertions(+) create mode 100644 tests/arch/xilinx/dynamic_upto_select.ys diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 48a9aa1da..cb9d1ce36 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1970,6 +1970,56 @@ skip_identity: } skip_alu_split: + // replace (2^k-1)-x with ~x when x is known to be smaller than 2^k + if (do_fine && cell->type == ID($sub)) + { + int y_width = GetSize(cell->getPort(ID::Y)); + bool a_signed = cell->getParam(ID::A_SIGNED).as_bool(); + + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + sig_a.extend_u0(y_width, a_signed); + + if (y_width > 0 && sig_a.is_fully_const()) + { + RTLIL::Const a_val = sig_a.as_const(); + + int k = 0; + while (k < y_width && a_val[k] == State::S1) + k++; + + bool a_is_mask = k > 0; + for (int i = k; a_is_mask && i < y_width; i++) + if (a_val[i] != State::S0) + a_is_mask = false; + + if (a_is_mask) + { + bool b_signed = cell->getParam(ID::B_SIGNED).as_bool(); + RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); + sig_b.extend_u0(y_width, b_signed); + + bool b_fits = true; + for (int i = k; b_fits && i < y_width; i++) + if (sig_b[i] != State::S0) + b_fits = false; + + if (b_fits) + { + RTLIL::SigSpec sig_y = module->Not(NEW_ID, sig_b.extract(0, k)); + if (y_width > k) + sig_y.append(RTLIL::SigSpec(State::S0, y_width - k)); + + log_debug("Replacing `(2^%d-1) - B` $sub cell `%s' in module `%s' with $not.\n", + k, cell->name.c_str(), module->name.c_str()); + module->connect(cell->getPort(ID::Y), sig_y); + module->remove(cell); + did_something = true; + goto next_cell; + } + } + } + } + // remove redundant pairs of bits in ==, ===, !=, and !== // replace cell with const driver if inputs can't be equal if (do_fine && cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) diff --git a/tests/arch/xilinx/dynamic_upto_select.ys b/tests/arch/xilinx/dynamic_upto_select.ys new file mode 100644 index 000000000..ba2b23f60 --- /dev/null +++ b/tests/arch/xilinx/dynamic_upto_select.ys @@ -0,0 +1,19 @@ +# https://github.com/YosysHQ/yosys/issues/892 + +read_verilog < Date: Wed, 10 Jun 2026 11:30:03 +0200 Subject: [PATCH 016/101] Add tests. --- tests/opt/opt_expr_sub_not.ys | 100 ++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 tests/opt/opt_expr_sub_not.ys diff --git a/tests/opt/opt_expr_sub_not.ys b/tests/opt/opt_expr_sub_not.ys new file mode 100644 index 000000000..459ec0f94 --- /dev/null +++ b/tests/opt/opt_expr_sub_not.ys @@ -0,0 +1,100 @@ +# Rewrite (2^k-1)-x into ~x when x is known to be smaller than 2^k + +read_verilog -icells < Date: Wed, 10 Jun 2026 14:46:04 +0200 Subject: [PATCH 017/101] Add muxcover regression test. --- tests/various/muxcover_index.ys | 87 +++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 tests/various/muxcover_index.ys diff --git a/tests/various/muxcover_index.ys b/tests/various/muxcover_index.ys new file mode 100644 index 000000000..041d497a5 --- /dev/null +++ b/tests/various/muxcover_index.ys @@ -0,0 +1,87 @@ +# https://github.com/YosysHQ/yosys/issues/964 + +read_verilog -formal < Date: Mon, 15 Jun 2026 13:41:47 +0200 Subject: [PATCH 018/101] force Ninja to display Makefile output for tests --- CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 9874fa88b..c972891ae 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -536,6 +536,7 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY) COMMAND make vanilla-test ${makefile_vars} WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests DEPENDS ${makefile_depends} + USES_TERMINAL JOB_SERVER_AWARE TRUE ) From 2bab5d3fa53e20430ec52c8b4fd3951480e256a0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 15 Jun 2026 14:48:11 +0200 Subject: [PATCH 019/101] Add VERBOSE (and V) option to Makefiles --- tests/common.mk | 8 +++++++- tests/gen_tests_makefile.py | 8 ++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/tests/common.mk b/tests/common.mk index 3f1efbf2a..eb9dcf260 100644 --- a/tests/common.mk +++ b/tests/common.mk @@ -28,6 +28,12 @@ export YOSYS_MAX_THREADS export LLVM_PROFILE_FILE export LLVM_PROFILE_FILE_BUFFER_SIZE=0 +ifeq ($(or $(V),$(VERBOSE)),1) + QUIET := +else + QUIET := >/dev/null 2>&1 +endif + all: ifndef OVERRIDE_MAIN @@ -38,7 +44,7 @@ endif define run_test @set -e; \ rc=0; \ - ( set -e; $(2) ) >/dev/null 2>&1 || rc=$$?; \ + ( set -e; $(2) ) $(QUIET) || rc=$$?; \ if [ $$rc -eq 0 ]; then \ echo "PASS $1"; \ echo PASS > $1.result; \ diff --git a/tests/gen_tests_makefile.py b/tests/gen_tests_makefile.py index efaa9a652..13bb806c9 100644 --- a/tests/gen_tests_makefile.py +++ b/tests/gen_tests_makefile.py @@ -26,27 +26,27 @@ def generate_target(name, command, deps = None): print(f"\t@$(call run_test,{target}, $({target}_cmd))") def generate_ys_test(ys_file, yosys_args="", commands=""): - cmd = f'$(YOSYS) -ql {ys_file}.err {yosys_args} {ys_file} && mv {ys_file}.err {ys_file}.log' + cmd = f'$(YOSYS) -l {ys_file}.err {yosys_args} {ys_file} && mv {ys_file}.err {ys_file}.log' if commands: cmd += f"; \\\n{commands}" generate_target(ys_file, cmd) def generate_tcl_test(tcl_file, yosys_args="", commands=""): - cmd = f'$(YOSYS) -ql {tcl_file}.err {yosys_args} {tcl_file} && mv {tcl_file}.err {tcl_file}.log' + cmd = f'$(YOSYS) -l {tcl_file}.err {yosys_args} {tcl_file} && mv {tcl_file}.err {tcl_file}.log' if commands: cmd += f"; \\\n{commands}" generate_target(tcl_file, cmd) def generate_sv_check(sv_file, yosys_args="", yosys_cmds=""): yosys_cmd = f'read -sv {sv_file}; {yosys_cmds}' - cmd = f'$(YOSYS) -ql {sv_file}.err -p "{yosys_cmd}" {yosys_args} && mv {sv_file}.err {sv_file}.log' + cmd = f'$(YOSYS) -l {sv_file}.err -p "{yosys_cmd}" {yosys_args} && mv {sv_file}.err {sv_file}.log' generate_target(sv_file, cmd) def generate_sv_test(sv_file, yosys_args="", commands=""): base = os.path.splitext(sv_file)[0] if not os.path.exists(base + ".ys"): yosys_cmd = '-p "prep -top top; async2sync; sat -enable_undef -verify -prove-asserts"' - cmd = f'$(YOSYS) -ql {sv_file}.err {yosys_cmd} {yosys_args} {sv_file} && mv {sv_file}.err {sv_file}.log' + cmd = f'$(YOSYS) -l {sv_file}.err {yosys_cmd} {yosys_args} {sv_file} && mv {sv_file}.err {sv_file}.log' if commands: cmd += f"; \\\n{commands}" generate_target(sv_file, cmd) From 6032b064e25cf50629e5af269f00ed4df51e0d91 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 15 Jun 2026 15:04:59 +0200 Subject: [PATCH 020/101] opt_muxtree: optimize for single driver, error on multiple drivers --- passes/opt/opt_muxtree.cc | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index c62252896..4887355b2 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -68,7 +68,7 @@ struct OptMuxtreeWorker // Is bit directly used by non-mux cells or ports? bool seen_non_mux; pool mux_users; - pool mux_drivers; + std::optional mux_driver; }; idict bit2num; @@ -107,7 +107,7 @@ struct OptMuxtreeWorker // Populate bit2info[]: // .seen_non_mux // .mux_users - // .mux_drivers + // .mux_driver // Populate mux2info[].ports[]: // .ctrl_sig // .input_sigs @@ -137,8 +137,11 @@ struct OptMuxtreeWorker // Analyze port A muxinfo.ports.push_back(used_port_bit(sig_a, this_mux_idx)); - for (int idx : sig2bits(sig_y)) - bit2info[idx].mux_drivers.insert(this_mux_idx); + for (int idx : sig2bits(sig_y)) { + if (bit2info[idx].mux_driver) + log_cmd_error("Cell %s Y port signal %s already driven by %s\n", cell->name, log_signal(sig_y), mux2info[*bit2info[idx].mux_driver].cell->name); + bit2info[idx].mux_driver = this_mux_idx; + } for (int idx : sig2bits(sig_s)) bit2info[idx].seen_non_mux = true; @@ -170,8 +173,8 @@ struct OptMuxtreeWorker for (int j : bit2info[i].mux_users) for (auto &p : mux2info[j].ports) { if (p.input_sigs.count(i)) - for (int k : bit2info[i].mux_drivers) - p.input_muxes.insert(k); + if (bit2info[i].mux_driver) + p.input_muxes.insert(*bit2info[i].mux_driver); } } @@ -184,14 +187,14 @@ struct OptMuxtreeWorker root_muxes.resize(GetSize(mux2info)); for (auto &bi : bit2info) { - for (int i : bi.mux_drivers) + if (bi.mux_driver) for (int j : bi.mux_users) - mux_to_users[i].insert(j); + mux_to_users[*bi.mux_driver].insert(j); if (!bi.seen_non_mux) continue; - for (int mux_idx : bi.mux_drivers) { - root_muxes.at(mux_idx) = true; - root_enable_muxes.at(mux_idx) = true; + if (bi.mux_driver) { + root_muxes.at(*bi.mux_driver) = true; + root_enable_muxes.at(*bi.mux_driver) = true; } } From 48c1e1a724ed028cfa6346c9fcff89c5b335268f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 15 Jun 2026 15:06:02 +0200 Subject: [PATCH 021/101] tests: remove hana test with multiple drivers --- tests/hana/test_parse2synthtrans.v | 28 +--------------------------- 1 file changed, 1 insertion(+), 27 deletions(-) diff --git a/tests/hana/test_parse2synthtrans.v b/tests/hana/test_parse2synthtrans.v index a1c0bfdb8..19943ffb5 100644 --- a/tests/hana/test_parse2synthtrans.v +++ b/tests/hana/test_parse2synthtrans.v @@ -23,33 +23,7 @@ always @(clk or reset) begin end endmodule -// test_parse2synthtrans_case_1_test.v -module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0); -output out0, out1, out2, out3; -reg out0, out1, out2, out3; -input in; -input s1, s0; -reg [3:0] encoding; -reg [1:0] state; - always @(encoding) begin - case (encoding) - 4'bxx11: state = 1; - 4'bx0xx: state = 3; - 4'b11xx: state = 4; - 4'bx1xx: state = 2; - 4'bxx1x: state = 1; - 4'bxxx1: state = 0; - default: state = 0; - endcase - end - - always @(encoding) begin - case (encoding) - 4'b0000: state = 1; - default: state = 0; - endcase - end -endmodule +// test_parse2synthtrans_case_1_test.v module f2_demultiplexer1_to_4 - REMOVED, multiple drivers // test_parse2synthtrans_contassign_1_test.v module f3_test(in, out); From 247bcfed65de665b8ceb8d2524233e57699de671 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 15 Jun 2026 15:25:58 +0200 Subject: [PATCH 022/101] Remove old Makefile and fix documentation --- .../extending_yosys/test_suites.rst | 10 ++- tests/unit/Makefile | 62 ------------------- 2 files changed, 4 insertions(+), 68 deletions(-) delete mode 100644 tests/unit/Makefile diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 2342c505d..e8b6634bc 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -164,6 +164,9 @@ compiler versions. For up to date information, including OS versions, refer to test for ``kernel/celledges.cc``, you will need to create a file like this: ``tests/unit/kernel/celledgesTest.cc``; * Implement your unit test + * Add unit test to file list in `CMakeLists.txt` + In case unit tests are added to new directory, note that you need also to + create new `CmakeList.txt` file and add ``yosys_gtest(dir-name unit-test.cc)``` Run unit tests ~~~~~~~~~~~~~~ @@ -172,10 +175,5 @@ compiler versions. For up to date information, including OS versions, refer to .. code-block:: console - make unit-test + cmake --build build --target test-unit - If you want to remove all unit test files, type: - - .. code-block:: console - - make clean-unit-test diff --git a/tests/unit/Makefile b/tests/unit/Makefile deleted file mode 100644 index 88f449bf8..000000000 --- a/tests/unit/Makefile +++ /dev/null @@ -1,62 +0,0 @@ -UNAME_S := $(shell uname -s) - -# GoogleTest flags -GTEST_PREFIX := $(shell brew --prefix googletest 2>/dev/null) -ifeq ($(GTEST_PREFIX),) - GTEST_CXXFLAGS := - GTEST_LDFLAGS := -lgtest -lgmock -lgtest_main -else - GTEST_CXXFLAGS := -I$(GTEST_PREFIX)/include - GTEST_LDFLAGS := -L$(GTEST_PREFIX)/lib -lgtest -lgmock -lgtest_main -endif - -ifeq ($(UNAME_S),Darwin) - RPATH = -Wl,-rpath,$(ROOTPATH) -else - RPATH = -Wl,-rpath=$(ROOTPATH) -endif - -EXTRAFLAGS := -lyosys -pthread - -MAKEFILE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) -OBJTEST := $(MAKEFILE_DIR)objtest -BINTEST := $(MAKEFILE_DIR)bintest - -ALLTESTFILE := $(shell cd $(MAKEFILE_DIR) && find . -name '*Test.cc' | sed 's|^\./||' | tr '\n' ' ') -TESTDIRS := $(sort $(dir $(ALLTESTFILE))) -TESTS := $(addprefix $(BINTEST)/, $(basename $(ALLTESTFILE:%Test.cc=%Test.o))) - -# Prevent make from removing our .o files -.SECONDARY: - -all: prepare $(TESTS) run-tests - -$(BINTEST)/%: $(OBJTEST)/%.o | prepare - $(CXX) -L$(ROOTPATH) $(RPATH) $(LINKFLAGS) -o $@ $^ $(LIBS) \ - $(GTEST_LDFLAGS) $(EXTRAFLAGS) - -$(OBJTEST)/%.o: $(MAKEFILE_DIR)/%.cc | prepare - $(CXX) -o $@ -c -I$(ROOTPATH) $(CPPFLAGS) $(CXXFLAGS) $(GTEST_CXXFLAGS) $^ - -.PHONY: prepare run-tests clean - -run-tests: $(TESTS) -ifeq ($(UNAME_S),Darwin) - @for t in $^; do \ - echo "Running $$t"; \ - DYLD_LIBRARY_PATH=$(ROOTPATH) $$t || exit 1; \ - done -else - @for t in $^; do \ - echo "Running $$t"; \ - $$t || exit 1; \ - done -endif - -prepare: - mkdir -p $(addprefix $(BINTEST)/,$(TESTDIRS)) - mkdir -p $(addprefix $(OBJTEST)/,$(TESTDIRS)) - -clean: - rm -rf $(OBJTEST) - rm -rf $(BINTEST) From a5bdb29d7ff155aee81d7e83052b758498aa642b Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 15 Jun 2026 15:44:50 +0200 Subject: [PATCH 023/101] Recognise asynchronous set/reset. --- passes/proc/proc_dlatch.cc | 126 ++++++++++++++++++++++++++++++---- passes/techmap/dfflegalize.cc | 69 +++++++++++++++++-- 2 files changed, 177 insertions(+), 18 deletions(-) diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 50e64f482..4a4045242 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -201,6 +201,77 @@ struct proc_dlatch_db_t sig[index] = State::Sx; cell->setPort(ID::A, sig); } + bool sibling_undef = true; + for (int i = 0; i < (is_bwmux ? 1 : GetSize(sig_s)); i++) + if (sig_b[i*width + index] != State::Sx) + sibling_undef = false; + if (!sibling_undef) { + if (!is_bwmux) { + for (int i = 0; i < GetSize(sig_s); i++) + n = make_inner(sig_s[i], State::S0, n); + } else { + n = make_inner(sig_s[index], State::S0, n); + } + } + children.insert(n); + } + + for (int i = 0; i < (is_bwmux ? 1 : GetSize(sig_s)); i++) { + n = find_mux_feedback(sig_b[i*width + index], needle, set_undef); + if (n != false_node) { + if (set_undef && sig_b[i*width + index] == needle) { + SigSpec sig = cell->getPort(ID::B); + sig[i*width + index] = State::Sx; + cell->setPort(ID::B, sig); + } + bool sibling_undef = (sig_a[index] == State::Sx); + if (!is_bwmux) + for (int j = 0; j < GetSize(sig_s); j++) + if (j != i && sig_b[j*width + index] != State::Sx) + sibling_undef = false; + if (!sibling_undef) + n = make_inner(sig_s[is_bwmux ? index : i], State::S1, n); + children.insert(n); + } + } + + if (children.empty()) + return false_node; + + return make_inner(children); + } + + int find_mux_constant(SigBit haystack, State needle, bool set_undef) + { + if (sigusers[haystack] > 1) + set_undef = false; + + if (haystack == SigBit(needle)) + return true_node; + + auto it = mux_drivers.find(haystack); + if (it == mux_drivers.end()) + return false_node; + + Cell *cell = it->second.first; + int index = it->second.second; + + log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux))); + bool is_bwmux = (cell->type == ID($bwmux)); + SigSpec sig_a = sigmap(cell->getPort(ID::A)); + SigSpec sig_b = sigmap(cell->getPort(ID::B)); + SigSpec sig_s = sigmap(cell->getPort(ID::S)); + int width = GetSize(sig_a); + + pool children; + + int n = find_mux_constant(sig_a[index], needle, set_undef); + if (n != false_node) { + if (set_undef && sig_a[index] == SigBit(needle)) { + SigSpec sig = cell->getPort(ID::A); + sig[index] = State::Sx; + cell->setPort(ID::A, sig); + } if (!is_bwmux) { for (int i = 0; i < GetSize(sig_s); i++) n = make_inner(sig_s[i], State::S0, n); @@ -211,9 +282,9 @@ struct proc_dlatch_db_t } for (int i = 0; i < (is_bwmux ? 1 : GetSize(sig_s)); i++) { - n = find_mux_feedback(sig_b[i*width + index], needle, set_undef); + n = find_mux_constant(sig_b[i*width + index], needle, set_undef); if (n != false_node) { - if (set_undef && sig_b[i*width + index] == needle) { + if (set_undef && sig_b[i*width + index] == SigBit(needle)) { SigSpec sig = cell->getPort(ID::B); sig[i*width + index] = State::Sx; cell->setPort(ID::B, sig); @@ -349,7 +420,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) { RTLIL::SigSig latches_bits, nolatches_bits; dict latches_out_in; - dict latches_hold; + dict latches_hold, latches_rst, latches_set; std::string src = proc->get_src_attribute(); for (auto sr : proc->syncs) @@ -381,15 +452,31 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) latches_out_in.sort(); for (auto &it : latches_out_in) { - int n = db.find_mux_feedback(it.second, it.first, true); - if (n == db.false_node) { + if (db.find_mux_feedback(it.second, it.first, false) == db.false_node) { nolatches_bits.first.append(it.first); nolatches_bits.second.append(it.second); - } else { - latches_bits.first.append(it.first); - latches_bits.second.append(it.second); - latches_hold[it.first] = n; + continue; } + + latches_bits.first.append(it.first); + latches_bits.second.append(it.second); + int nrst = db.find_mux_constant(it.second, State::S0, false); + int nset = db.find_mux_constant(it.second, State::S1, false); + bool has_rst = (nrst != db.false_node); + bool has_set = (nset != db.false_node); + + if (has_rst && !has_set) + nrst = db.find_mux_constant(it.second, State::S0, true); + else if (has_set && !has_rst) + nset = db.find_mux_constant(it.second, State::S1, true); + else + nrst = nset = db.false_node; + + int n = db.find_mux_feedback(it.second, it.first, true); + log_assert(n != db.false_node); + latches_hold[it.first] = n; + latches_rst[it.first] = nrst; + latches_set[it.first] = nset; } int offset = 0; @@ -423,20 +510,35 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) while (offset < GetSize(latches_bits.first)) { int width = 1; - int n = latches_hold[latches_bits.first[offset]]; - Wire *w = latches_bits.first[offset].wire; + SigBit obit = latches_bits.first[offset]; + int n = latches_hold[obit]; + int nrst = latches_rst[obit]; + int nset = latches_set[obit]; + Wire *w = obit.wire; if (w != nullptr) { while (offset+width < GetSize(latches_bits.first) && n == latches_hold[latches_bits.first[offset+width]] && + nrst == latches_rst[latches_bits.first[offset+width]] && + nset == latches_set[latches_bits.first[offset+width]] && w == latches_bits.first[offset+width].wire) width++; SigSpec lhs = latches_bits.first.extract(offset, width); SigSpec rhs = latches_bits.second.extract(offset, width); - Cell *cell = db.module->addDlatch(NEW_ID, db.module->Not(NEW_ID, db.make_hold(n, src)), rhs, lhs); + SigBit en = db.module->Not(NEW_ID, db.make_hold(n, src)); + bool has_rst = (nrst != db.false_node); + bool has_set = (nset != db.false_node); + + Cell *cell; + if (has_rst) + cell = db.module->addAdlatch(NEW_ID, en, db.make_hold(nrst, src), rhs, lhs, RTLIL::Const(State::S0, width)); + else if (has_set) + cell = db.module->addAdlatch(NEW_ID, en, db.make_hold(nset, src), rhs, lhs, RTLIL::Const(State::S1, width)); + else + cell = db.module->addDlatch(NEW_ID, en, rhs, lhs); cell->set_src_attribute(src); db.generated_dlatches.insert(cell); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 3cba527b2..d2755b53e 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -370,10 +370,16 @@ struct DffLegalizePass : public Pass { else fail_ff(ff, "initialized dffs with async set and reset are not supported"); } else { - if (!supported_cells[FF_DLATCHSR]) - fail_ff(ff, "dlatch with async set and reset are not supported"); - else - fail_ff(ff, "initialized dlatch with async set and reset are not supported"); + if (!supported_dlatch) { + if (!supported_cells[FF_DLATCHSR]) + fail_ff(ff, "dlatch with async set and reset are not supported"); + else + fail_ff(ff, "initialized dlatch with async set and reset are not supported"); + } + if (ff.cell) + log_warning("Emulating async set + reset latch with a plain D latch and logic for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape()); + emulate_dlatch(ff); + return; } } @@ -449,6 +455,51 @@ struct DffLegalizePass : public Pass { legalize_ff(ff_sel); } + void emulate_dlatch(FfData &ff) { + // emulate adlatch or dlatchsr + log_assert(!ff.has_clk); + log_assert(ff.has_aload); + log_assert(ff.width == 1); + + auto active_high = [&](SigBit sig, bool pol) -> SigBit { + if (pol) + return sig; + return ff.is_fine ? ff.module->NotGate(NEW_ID, sig) : ff.module->Not(NEW_ID, sig)[0]; + }; + + auto do_mux = [&](SigBit a, SigBit b, SigBit s) -> SigBit { + return ff.is_fine ? ff.module->MuxGate(NEW_ID, a, b, s) : ff.module->Mux(NEW_ID, a, b, s)[0]; + }; + + auto do_or = [&](SigBit a, SigBit b) -> SigBit { + return ff.is_fine ? ff.module->OrGate(NEW_ID, a, b) : ff.module->Or(NEW_ID, a, b)[0]; + }; + + SigBit en = active_high(ff.sig_aload, ff.pol_aload); + SigBit d = ff.sig_ad; + + if (ff.has_sr) { + SigBit set = active_high(ff.sig_set[0], ff.pol_set); + SigBit clr = active_high(ff.sig_clr[0], ff.pol_clr); + // clr > set > load > hold + d = do_mux(d, State::S1, set); + d = do_mux(d, State::S0, clr); + en = do_or(en, do_or(set, clr)); + ff.has_sr = false; + } + if (ff.has_arst) { + SigBit arst = active_high(ff.sig_arst[0], ff.pol_arst); + d = do_mux(d, ff.val_arst[0], arst); + en = do_or(en, arst); + ff.has_arst = false; + } + + ff.sig_ad = d; + ff.sig_aload = en; + ff.pol_aload = true; + legalize_dlatch(ff); + } + void legalize_dff(FfData &ff) { if (!try_flip(ff, supported_dff)) { if (!supported_dff) @@ -742,8 +793,14 @@ struct DffLegalizePass : public Pass { void legalize_adlatch(FfData &ff) { if (!try_flip(ff, supported_adlatch)) { - if (!supported_adlatch) - fail_ff(ff, "D latches with async set or reset are not supported"); + if (!supported_adlatch) { + if (!supported_dlatch) + fail_ff(ff, "D latches with async set or reset are not supported"); + if (ff.cell) + log_warning("Emulating async reset latch with a plain D latch and logic for %s.%s\n", ff.module->name.unescape(), ff.cell->name.unescape()); + emulate_dlatch(ff); + return; + } if (!(supported_dlatch & (INIT_0 | INIT_1))) fail_ff(ff, "initialized D latches are not supported"); From eb4703808a3c777e6b974a48508c63ad3247462b Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 15 Jun 2026 15:46:13 +0200 Subject: [PATCH 024/101] Add tests. --- tests/proc/proc_dlatch.ys | 89 +++++++++++++++++++++++++ tests/proc/yosys_latch.sv | 11 +++ tests/proc/yosys_latch.ys | 20 ++++++ tests/techmap/dfflegalize_dlatch_emu.ys | 25 +++++++ 4 files changed, 145 insertions(+) create mode 100644 tests/proc/proc_dlatch.ys create mode 100644 tests/proc/yosys_latch.sv create mode 100644 tests/proc/yosys_latch.ys create mode 100644 tests/techmap/dfflegalize_dlatch_emu.ys diff --git a/tests/proc/proc_dlatch.ys b/tests/proc/proc_dlatch.ys new file mode 100644 index 000000000..3dba3076e --- /dev/null +++ b/tests/proc/proc_dlatch.ys @@ -0,0 +1,89 @@ +read_verilog -formal < Date: Mon, 15 Jun 2026 16:04:37 +0200 Subject: [PATCH 025/101] Added functional tests option --- CMakeLists.txt | 11 +++++++++++ .../extending_yosys/test_suites.rst | 18 +++++++++++------- 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c972891ae..a37b52ebe 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -39,6 +39,7 @@ set(CMAKE_CXX_SCAN_FOR_MODULES NO) set(YOSYS_COMPILER_LAUNCHER "" CACHE STRING "Compiler launcher (ccache, sccache)") option(YOSYS_ENABLE_COVERAGE "Enable code coverage" OFF) option(YOSYS_ENABLE_PROFILING "Enable instruction profiling" OFF) +option(YOSYS_ENABLE_FUNCTIONAL_TESTS "Enable running functional tests" OFF) set(YOSYS_PROGRAM_PREFIX "" CACHE STRING "Name prefix for programs, libraries, and data") set(YOSYS_COMPONENTS "everything" CACHE STRING "List of components to build (use pass names)") @@ -534,6 +535,16 @@ if (NOT YOSYS_BUILD_PYTHON_ONLY) add_custom_target(test-vanilla COMMAND make vanilla-test ${makefile_vars} + ENABLE_FUNCTIONAL_TESTS=$,1,0> + WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests + DEPENDS ${makefile_depends} + USES_TERMINAL + JOB_SERVER_AWARE TRUE + ) + + add_custom_target(test-functional + COMMAND make functional ${makefile_vars} + ENABLE_FUNCTIONAL_TESTS=$,1,0> WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests DEPENDS ${makefile_depends} USES_TERMINAL diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index e8b6634bc..3e30d36b8 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -76,15 +76,19 @@ If you don't have one of the :ref:`getting_started/installation:CAD suite(s)` installed, you should also install Z3 `following their instructions `_. -.. TODO:: CMAKE_TODO +Functional tests are disabled by default, to enable them use next code snippet +and run tests as usual: - How does this work under CMake? Is it only via ``make -C tests - ENABLE_FUNCTIONAL_TESTS=1`` and then manually setting ``BUILD_DIR`` and - ``PROGRAM_PREFIX``? And possibly also setting ``YOSYS`` et al if there is a - ``.exe``. Previous instructions: +.. code:: console - Then, set the :makevar:`ENABLE_FUNCTIONAL_TESTS` make variable when calling - ``make test`` and the functional tests will be run as well. + cmake -B build . -DYOSYS_ENABLE_FUNCTIONAL_TESTS=ON + cmake --build build --target test --parallel $(nproc) + +Or run just functional tests with: + +.. code:: console + + cmake --build build --target test-functional Docs tests ~~~~~~~~~~ From c0709b1b4ed011b72c9fd2f65732e9b470d6566e Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 15 Jun 2026 16:23:44 +0200 Subject: [PATCH 026/101] Fixup issue test. --- tests/proc/proc_dlatch.ys | 44 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/tests/proc/proc_dlatch.ys b/tests/proc/proc_dlatch.ys index 3dba3076e..b45e9831b 100644 --- a/tests/proc/proc_dlatch.ys +++ b/tests/proc/proc_dlatch.ys @@ -87,3 +87,47 @@ EOT proc select -assert-count 1 t:$dlatch select -assert-count 0 t:$adlatch + +design -reset + +read_verilog -formal < Date: Mon, 15 Jun 2026 19:42:17 +0200 Subject: [PATCH 027/101] Update ABC as per 2026-06-15 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index 1e85fff18..30c47da5c 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 1e85fff18db313b29584dc1ff7c2074d2275a381 +Subproject commit 30c47da5c9343713ef0b3e12914686ffd28ef367 From 0584587f9a5eaff3c915969fb00b891982581092 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 16 Jun 2026 10:07:45 +0200 Subject: [PATCH 028/101] Make compilation like by abc scripts --- cmake/YosysAbc.cmake | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cmake/YosysAbc.cmake b/cmake/YosysAbc.cmake index 1c59308d3..6e3736712 100644 --- a/cmake/YosysAbc.cmake +++ b/cmake/YosysAbc.cmake @@ -42,7 +42,9 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) list(TRANSFORM all_sources PREPEND abc/) # Required to get `-DABC_NAMESPACE` below to work consistently. - set_source_files_properties(${all_sources} PROPERTIES LANGUAGE CXX) + if(NOT MSVC) + set_source_files_properties(${all_sources} PROPERTIES LANGUAGE CXX) + endif() set(main_source abc/src/base/main/main.c) list(REMOVE_ITEM all_sources ${main_source}) @@ -55,7 +57,7 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) target_include_directories(${arg_LIBNAME} PRIVATE abc/src) target_compile_definitions(${arg_LIBNAME} PUBLIC WIN32_NO_DLL - ABC_NAMESPACE=abc + $<$>:ABC_NAMESPACE=abc> ABC_USE_STDINT_H=1 ABC_USE_CUDD=1 ABC_NO_DYNAMIC_LINKING From 3af45e7d04320930cc27e5b7791cd7d1a8a346f3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 16 Jun 2026 10:31:37 +0200 Subject: [PATCH 029/101] Some more explanations --- .../extending_yosys/test_suites.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 3e30d36b8..58274c864 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -16,6 +16,20 @@ tests. cmake -B build . cmake --build build --target test --parallel $(nproc) +.. warning:: + + There are limitations when using `Ninja` as generator, so we suggest using + `Unix Makefiles` to make running tests in parallel possible. However, it is + possible to use it directly by running: + +.. code:: console + + cd tests + make -j9 + +Please note that in this case default build directory is `build` but can be +overwritten by providing `BUILD_DIR` variable. + Vanilla tests ~~~~~~~~~~~~~ From 88d4af94cfd24ed49fdc8f088ddfe1509765c4a1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 17 Jun 2026 10:40:13 +0200 Subject: [PATCH 030/101] Fix share lookup for mingw builds --- kernel/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt index 9dd1fd5cd..4cd76b4ff 100644 --- a/kernel/CMakeLists.txt +++ b/kernel/CMakeLists.txt @@ -156,7 +156,7 @@ yosys_core(kernel set(yosys_cc_definitions "$<$:ABCEXTERNAL=\"${YOSYS_ABC_EXECUTABLE}\">" - $<$:YOSYS_WIN32_UNIX_DIR> + $<$:YOSYS_WIN32_UNIX_DIR> ) set_source_files_properties(yosys.cc PROPERTIES COMPILE_DEFINITIONS "${yosys_cc_definitions}" From 7fbeb344a48db5d08ac8852793f221437d00de53 Mon Sep 17 00:00:00 2001 From: Matt Liberty Date: Thu, 18 Jun 2026 05:15:04 +0000 Subject: [PATCH 031/101] Update lz4 to 1.10.0 for CVE-2014-4715, CVE-2021-3520, CVE-2019-17543 Signed-off-by: Matt Liberty --- libs/fst/lz4.cc | 215 ++++++++++++++++++++++++++++++------------------ libs/fst/lz4.h | 104 +++++++++++++---------- 2 files changed, 198 insertions(+), 121 deletions(-) diff --git a/libs/fst/lz4.cc b/libs/fst/lz4.cc index 0a727596b..493a27e45 100644 --- a/libs/fst/lz4.cc +++ b/libs/fst/lz4.cc @@ -1,6 +1,6 @@ /* LZ4 - Fast LZ compression algorithm - Copyright (C) 2011-2023, Yann Collet. + Copyright (c) Yann Collet. All rights reserved. BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) @@ -77,7 +77,8 @@ #ifndef LZ4_FORCE_MEMORY_ACCESS /* can be defined externally */ # if defined(__GNUC__) && \ ( defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) \ - || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) ) + || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ + || (defined(__riscv) && defined(__riscv_zicclsm)) ) # define LZ4_FORCE_MEMORY_ACCESS 2 # elif (defined(__INTEL_COMPILER) && !defined(_WIN32)) || defined(__GNUC__) || defined(_MSC_VER) # define LZ4_FORCE_MEMORY_ACCESS 1 @@ -124,14 +125,17 @@ # include /* only present in VS2005+ */ # pragma warning(disable : 4127) /* disable: C4127: conditional expression is constant */ # pragma warning(disable : 6237) /* disable: C6237: conditional expression is always 0 */ +# pragma warning(disable : 6239) /* disable: C6239: ( && ) always evaluates to the result of */ +# pragma warning(disable : 6240) /* disable: C6240: ( && ) always evaluates to the result of */ +# pragma warning(disable : 6326) /* disable: C6326: Potential comparison of a constant with another constant */ #endif /* _MSC_VER */ #ifndef LZ4_FORCE_INLINE -# ifdef _MSC_VER /* Visual Studio */ +# if defined (_MSC_VER) && !defined (__clang__) /* MSVC */ # define LZ4_FORCE_INLINE static __forceinline # else # if defined (__cplusplus) || defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L /* C99 */ -# ifdef __GNUC__ +# if defined (__GNUC__) || defined (__clang__) # define LZ4_FORCE_INLINE static inline __attribute__((always_inline)) # else # define LZ4_FORCE_INLINE static inline @@ -298,12 +302,12 @@ static int LZ4_isAligned(const void* ptr, size_t alignment) #include #if defined(__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */) # include - typedef uint8_t BYTE; - typedef uint16_t U16; - typedef uint32_t U32; - typedef int32_t S32; - typedef uint64_t U64; - typedef uintptr_t uptrval; + typedef unsigned char BYTE; /*uint8_t not necessarily blessed to alias arbitrary type*/ + typedef uint16_t U16; + typedef uint32_t U32; + typedef int32_t S32; + typedef uint64_t U64; + typedef uintptr_t uptrval; #else # if UINT_MAX != 4294967295UL # error "LZ4 code (when not C++ or C99) assumes that sizeof(int) == 4" @@ -430,7 +434,7 @@ static U16 LZ4_readLE16(const void* memPtr) return LZ4_read16(memPtr); } else { const BYTE* p = (const BYTE*)memPtr; - return (U16)((U16)p[0] + (p[1]<<8)); + return (U16)((U16)p[0] | (p[1]<<8)); } } @@ -441,7 +445,7 @@ static U32 LZ4_readLE32(const void* memPtr) return LZ4_read32(memPtr); } else { const BYTE* p = (const BYTE*)memPtr; - return (U32)p[0] + (p[1]<<8) + (p[2]<<16) + (p[3]<<24); + return (U32)p[0] | (p[1]<<8) | (p[2]<<16) | (p[3]<<24); } } #endif @@ -475,12 +479,7 @@ static const int dec64table[8] = {0, 0, 0, -1, -4, 1, 2, 3}; #ifndef LZ4_FAST_DEC_LOOP # if defined __i386__ || defined _M_IX86 || defined __x86_64__ || defined _M_X64 # define LZ4_FAST_DEC_LOOP 1 -# elif defined(__aarch64__) && defined(__APPLE__) -# define LZ4_FAST_DEC_LOOP 1 -# elif defined(__aarch64__) && !defined(__clang__) - /* On non-Apple aarch64, we disable this optimization for clang because - * on certain mobile chipsets, performance is reduced with clang. For - * more information refer to https://github.com/lz4/lz4/pull/707 */ +# elif defined(__aarch64__) # define LZ4_FAST_DEC_LOOP 1 # else # define LZ4_FAST_DEC_LOOP 0 @@ -495,10 +494,9 @@ LZ4_memcpy_using_offset_base(BYTE* dstPtr, const BYTE* srcPtr, BYTE* dstEnd, con assert(srcPtr + offset == dstPtr); if (offset < 8) { LZ4_write32(dstPtr, 0); /* silence an msan warning when offset==0 */ - dstPtr[0] = srcPtr[0]; - dstPtr[1] = srcPtr[1]; - dstPtr[2] = srcPtr[2]; - dstPtr[3] = srcPtr[3]; + assert(offset != 1); /* offset==0 happens on testing */ + LZ4_memcpy(dstPtr, srcPtr, 2); + LZ4_memcpy(dstPtr + 2, srcPtr + 2, 2); srcPtr += inc32table[offset]; LZ4_memcpy(dstPtr+4, srcPtr, 4); srcPtr -= dec64table[offset]; @@ -512,6 +510,20 @@ LZ4_memcpy_using_offset_base(BYTE* dstPtr, const BYTE* srcPtr, BYTE* dstEnd, con LZ4_wildCopy8(dstPtr, srcPtr, dstEnd); } + +#ifdef __aarch64__ +/* customized variant of memcpy, which can overwrite up to 64 bytes beyond dstEnd */ +LZ4_FORCE_INLINE void +LZ4_wildCopy64(void* dstPtr, const void* srcPtr, void* dstEnd) +{ + BYTE* d = (BYTE*)dstPtr; + const BYTE* s = (const BYTE*)srcPtr; + BYTE* const e = (BYTE*)dstEnd; + + do { LZ4_memcpy(d,s,64); d+=64; s+=64; } while (d= 16. */ @@ -527,7 +539,7 @@ LZ4_wildCopy32(void* dstPtr, const void* srcPtr, void* dstEnd) /* LZ4_memcpy_using_offset() presumes : * - dstEnd >= dstPtr + MINMATCH - * - there is at least 8 bytes available to write after dstEnd */ + * - there is at least 12 bytes available to write after dstEnd */ LZ4_FORCE_INLINE void LZ4_memcpy_using_offset(BYTE* dstPtr, const BYTE* srcPtr, BYTE* dstEnd, const size_t offset) { @@ -893,7 +905,7 @@ LZ4_prepareTable(LZ4_stream_t_internal* const cctx, || tableType == byPtr || inputSize >= 4 KB) { - DEBUGLOG(4, "LZ4_prepareTable: Resetting table in %p", cctx); + DEBUGLOG(4, "LZ4_prepareTable: Resetting table in %p", (void*)cctx); MEM_INIT(cctx->hashTable, 0, LZ4_HASHTABLESIZE); cctx->currentOffset = 0; cctx->tableType = (U32)clearedTable; @@ -1118,7 +1130,7 @@ LZ4_FORCE_INLINE int LZ4_compress_generic_validated( goto _last_literals; } if (litLength >= RUN_MASK) { - int len = (int)(litLength - RUN_MASK); + unsigned len = litLength - RUN_MASK; *token = (RUN_MASK<= 255 ; len-=255) *op++ = 255; *op++ = (BYTE)len; @@ -1529,7 +1541,7 @@ LZ4_stream_t* LZ4_createStream(void) { LZ4_stream_t* const lz4s = (LZ4_stream_t*)ALLOC(sizeof(LZ4_stream_t)); LZ4_STATIC_ASSERT(sizeof(LZ4_stream_t) >= sizeof(LZ4_stream_t_internal)); - DEBUGLOG(4, "LZ4_createStream %p", lz4s); + DEBUGLOG(4, "LZ4_createStream %p", (void*)lz4s); if (lz4s == NULL) return NULL; LZ4_initStream(lz4s, sizeof(*lz4s)); return lz4s; @@ -1560,7 +1572,7 @@ LZ4_stream_t* LZ4_initStream (void* buffer, size_t size) * prefer initStream() which is more general */ void LZ4_resetStream (LZ4_stream_t* LZ4_stream) { - DEBUGLOG(5, "LZ4_resetStream (ctx:%p)", LZ4_stream); + DEBUGLOG(5, "LZ4_resetStream (ctx:%p)", (void*)LZ4_stream); MEM_INIT(LZ4_stream, 0, sizeof(LZ4_stream_t_internal)); } @@ -1572,15 +1584,18 @@ void LZ4_resetStream_fast(LZ4_stream_t* ctx) { int LZ4_freeStream (LZ4_stream_t* LZ4_stream) { if (!LZ4_stream) return 0; /* support free on NULL */ - DEBUGLOG(5, "LZ4_freeStream %p", LZ4_stream); + DEBUGLOG(5, "LZ4_freeStream %p", (void*)LZ4_stream); FREEMEM(LZ4_stream); return (0); } #endif +typedef enum { _ld_fast, _ld_slow } LoadDict_mode_e; #define HASH_UNIT sizeof(reg_t) -int LZ4_loadDict (LZ4_stream_t* LZ4_dict, const char* dictionary, int dictSize) +static int LZ4_loadDict_internal(LZ4_stream_t* LZ4_dict, + const char* dictionary, int dictSize, + LoadDict_mode_e _ld) { LZ4_stream_t_internal* const dict = &LZ4_dict->internal_donotuse; const tableType_t tableType = byU32; @@ -1588,7 +1603,7 @@ int LZ4_loadDict (LZ4_stream_t* LZ4_dict, const char* dictionary, int dictSize) const BYTE* const dictEnd = p + dictSize; U32 idx32; - DEBUGLOG(4, "LZ4_loadDict (%i bytes from %p into %p)", dictSize, dictionary, LZ4_dict); + DEBUGLOG(4, "LZ4_loadDict (%i bytes from %p into %p)", dictSize, (void*)dictionary, (void*)LZ4_dict); /* It's necessary to reset the context, * and not just continue it with prepareTable() @@ -1616,20 +1631,46 @@ int LZ4_loadDict (LZ4_stream_t* LZ4_dict, const char* dictionary, int dictSize) while (p <= dictEnd-HASH_UNIT) { U32 const h = LZ4_hashPosition(p, tableType); + /* Note: overwriting => favors positions end of dictionary */ LZ4_putIndexOnHash(idx32, h, dict->hashTable, tableType); p+=3; idx32+=3; } + if (_ld == _ld_slow) { + /* Fill hash table with additional references, to improve compression capability */ + p = dict->dictionary; + idx32 = dict->currentOffset - dict->dictSize; + while (p <= dictEnd-HASH_UNIT) { + U32 const h = LZ4_hashPosition(p, tableType); + U32 const limit = dict->currentOffset - 64 KB; + if (LZ4_getIndexOnHash(h, dict->hashTable, tableType) <= limit) { + /* Note: not overwriting => favors positions beginning of dictionary */ + LZ4_putIndexOnHash(idx32, h, dict->hashTable, tableType); + } + p++; idx32++; + } + } + return (int)dict->dictSize; } +int LZ4_loadDict(LZ4_stream_t* LZ4_dict, const char* dictionary, int dictSize) +{ + return LZ4_loadDict_internal(LZ4_dict, dictionary, dictSize, _ld_fast); +} + +int LZ4_loadDictSlow(LZ4_stream_t* LZ4_dict, const char* dictionary, int dictSize) +{ + return LZ4_loadDict_internal(LZ4_dict, dictionary, dictSize, _ld_slow); +} + void LZ4_attach_dictionary(LZ4_stream_t* workingStream, const LZ4_stream_t* dictionaryStream) { const LZ4_stream_t_internal* dictCtx = (dictionaryStream == NULL) ? NULL : &(dictionaryStream->internal_donotuse); DEBUGLOG(4, "LZ4_attach_dictionary (%p, %p, size %u)", - workingStream, dictionaryStream, + (void*)workingStream, (void*)dictionaryStream, dictCtx != NULL ? dictCtx->dictSize : 0); if (dictCtx != NULL) { @@ -1693,7 +1734,7 @@ int LZ4_compress_fast_continue (LZ4_stream_t* LZ4_stream, && (inputSize > 0) /* tolerance : don't lose history, in case next invocation would use prefix mode */ && (streamPtr->dictCtx == NULL) /* usingDictCtx */ ) { - DEBUGLOG(5, "LZ4_compress_fast_continue: dictSize(%u) at addr:%p is too small", streamPtr->dictSize, streamPtr->dictionary); + DEBUGLOG(5, "LZ4_compress_fast_continue: dictSize(%u) at addr:%p is too small", streamPtr->dictSize, (void*)streamPtr->dictionary); /* remove dictionary existence from history, to employ faster prefix mode */ streamPtr->dictSize = 0; streamPtr->dictionary = (const BYTE*)source; @@ -1783,7 +1824,7 @@ int LZ4_saveDict (LZ4_stream_t* LZ4_dict, char* safeBuffer, int dictSize) { LZ4_stream_t_internal* const dict = &LZ4_dict->internal_donotuse; - DEBUGLOG(5, "LZ4_saveDict : dictSize=%i, safeBuffer=%p", dictSize, safeBuffer); + DEBUGLOG(5, "LZ4_saveDict : dictSize=%i, safeBuffer=%p", dictSize, (void*)safeBuffer); if ((U32)dictSize > 64 KB) { dictSize = 64 KB; } /* useless to define a dictionary > 64 KB */ if ((U32)dictSize > dict->dictSize) { dictSize = (int)dict->dictSize; } @@ -1936,42 +1977,32 @@ LZ4_decompress_unsafe_generic( /* Read the variable-length literal or match length. * - * @ip : input pointer - * @ilimit : position after which if length is not decoded, the input is necessarily corrupted. - * @initial_check - check ip >= ipmax before start of loop. Returns initial_error if so. - * @error (output) - error code. Must be set to 0 before call. + * @ipPtr : pointer to input pointer, will be advanced + * @ilimit : read is forbidden beyond this position (must be within input buffer) **/ typedef size_t Rvl_t; static const Rvl_t rvl_error = (Rvl_t)(-1); LZ4_FORCE_INLINE Rvl_t -read_variable_length(const BYTE** ip, const BYTE* ilimit, - int initial_check) +read_variable_length(const BYTE** ipPtr, const BYTE* ilimit) { Rvl_t s, length = 0; - assert(ip != NULL); - assert(*ip != NULL); + assert(ipPtr != NULL); + assert(*ipPtr != NULL); assert(ilimit != NULL); - if (initial_check && unlikely((*ip) >= ilimit)) { /* read limit reached */ + if (unlikely((*ipPtr) >= ilimit)) { /* read limit reached */ return rvl_error; } - s = **ip; - (*ip)++; + s = **ipPtr; + (*ipPtr)++; length += s; - if (unlikely((*ip) > ilimit)) { /* read limit reached */ - return rvl_error; - } - /* accumulator overflow detection (32-bit mode only) */ - if ((sizeof(length) < 8) && unlikely(length > ((Rvl_t)(-1)/2)) ) { - return rvl_error; - } if (likely(s != 255)) return length; do { - s = **ip; - (*ip)++; - length += s; - if (unlikely((*ip) > ilimit)) { /* read limit reached */ + if (unlikely((*ipPtr) >= ilimit)) { /* read limit reached */ return rvl_error; } + s = **ipPtr; + (*ipPtr)++; + length += s; /* accumulator overflow detection (32-bit mode only) */ if ((sizeof(length) < 8) && unlikely(length > ((Rvl_t)(-1)/2)) ) { return rvl_error; @@ -2042,7 +2073,7 @@ LZ4_decompress_generic( * note : fast loop may show a regression for some client arm chips. */ #if LZ4_FAST_DEC_LOOP if ((oend - op) < FASTLOOP_SAFE_DISTANCE) { - DEBUGLOG(6, "skip fast decode loop"); + DEBUGLOG(6, "move to safe decode loop"); goto safe_decode; } @@ -2054,50 +2085,61 @@ LZ4_decompress_generic( assert(ip < iend); token = *ip++; length = token >> ML_BITS; /* literal length */ + DEBUGLOG(7, "blockPos%6u: litLength token = %u", (unsigned)(op-(BYTE*)dst), (unsigned)length); + + if (ip > iend-(16 + 1/*max lit + offset + nextToken*/)) { goto safe_literal_copy_early; } /* decode literal length */ if (length == RUN_MASK) { - size_t const addl = read_variable_length(&ip, iend-RUN_MASK, 1); + /* literal length >= RUN_MASK means >= RUN_MASK literal bytes follow the extension bytes, + * so extension bytes cannot reach the last RUN_MASK bytes of input */ + size_t const addl = read_variable_length(&ip, iend - RUN_MASK); if (addl == rvl_error) { DEBUGLOG(6, "error reading long literal length"); goto _output_error; } length += addl; - if (unlikely((uptrval)(op)+length<(uptrval)(op))) { goto _output_error; } /* overflow detection */ + cpy = op+length; + if (unlikely((uptrval)(cpy)<(uptrval)(op))) { goto _output_error; } /* overflow detection */ if (unlikely((uptrval)(ip)+length<(uptrval)(ip))) { goto _output_error; } /* overflow detection */ /* copy literals */ LZ4_STATIC_ASSERT(MFLIMIT >= WILDCOPYLENGTH); - if ((op+length>oend-32) || (ip+length>iend-32)) { goto safe_literal_copy; } - LZ4_wildCopy32(op, ip, op+length); - ip += length; op += length; - } else if (ip <= iend-(16 + 1/*max lit + offset + nextToken*/)) { - /* We don't need to check oend, since we check it once for each loop below */ + #ifdef __aarch64__ + if ((cpy>oend-64) || (ip+length>iend-64)) { goto safe_literal_copy; } + LZ4_wildCopy64(op, ip, cpy); + #else + if ((cpy>oend-32) || (ip+length>iend-32)) { goto safe_literal_copy; } + LZ4_wildCopy32(op, ip, cpy); + #endif + ip += length; op = cpy; + } else { DEBUGLOG(7, "copy %u bytes in a 16-bytes stripe", (unsigned)length); /* Literals can only be <= 14, but hope compilers optimize better when copy by a register size */ LZ4_memcpy(op, ip, 16); ip += length; op += length; - } else { - goto safe_literal_copy; } /* get offset */ offset = LZ4_readLE16(ip); ip+=2; - DEBUGLOG(6, " offset = %zu", offset); + DEBUGLOG(6, "blockPos%6u: offset = %u", (unsigned)(op-(BYTE*)dst), (unsigned)offset); match = op - offset; assert(match <= op); /* overflow check */ /* get matchlength */ length = token & ML_MASK; + DEBUGLOG(7, " match length token = %u (len==%u)", (unsigned)length, (unsigned)length+MINMATCH); if (length == ML_MASK) { - size_t const addl = read_variable_length(&ip, iend - LASTLITERALS + 1, 0); + /* after match length extension bytes, at least 1 token + LASTLITERALS literals must remain */ + size_t const addl = read_variable_length(&ip, iend - (1 + LASTLITERALS)); if (addl == rvl_error) { - DEBUGLOG(6, "error reading long match length"); + DEBUGLOG(5, "error reading long match length"); goto _output_error; } length += addl; length += MINMATCH; + DEBUGLOG(7, " long match length == %u", (unsigned)length); if (unlikely((uptrval)(op)+length<(uptrval)op)) { goto _output_error; } /* overflow detection */ if (op + length >= oend - FASTLOOP_SAFE_DISTANCE) { goto safe_match_copy; @@ -2105,6 +2147,7 @@ LZ4_decompress_generic( } else { length += MINMATCH; if (op + length >= oend - FASTLOOP_SAFE_DISTANCE) { + DEBUGLOG(7, "moving to safe_match_copy (ml==%u)", (unsigned)length); goto safe_match_copy; } @@ -2123,7 +2166,7 @@ LZ4_decompress_generic( } } } if ( checkOffset && (unlikely(match + dictSize < lowPrefix)) ) { - DEBUGLOG(6, "Error : pos=%zi, offset=%zi => outside buffers", op-lowPrefix, op-match); + DEBUGLOG(5, "Error : pos=%zi, offset=%zi => outside buffers", op-lowPrefix, op-match); goto _output_error; } /* match starting within external dictionary */ @@ -2162,9 +2205,13 @@ LZ4_decompress_generic( /* copy match within block */ cpy = op + length; - assert((op <= oend) && (oend-op >= 32)); + assert((op <= oend) && (oend-op >= 64)); if (unlikely(offset<16)) { LZ4_memcpy_using_offset(op, match, cpy, offset); + #ifdef __aarch64__ + } else if (offset >= 64) { + LZ4_wildCopy64(op, match, cpy); + #endif } else { LZ4_wildCopy32(op, match, cpy); } @@ -2180,6 +2227,7 @@ LZ4_decompress_generic( assert(ip < iend); token = *ip++; length = token >> ML_BITS; /* literal length */ + DEBUGLOG(7, "blockPos%6u: litLength token = %u", (unsigned)(op-(BYTE*)dst), (unsigned)length); /* A two-stage shortcut for the most common case: * 1) If the literal length is 0..14, and there is enough space, @@ -2200,6 +2248,7 @@ LZ4_decompress_generic( /* The second stage: prepare for match copying, decode full info. * If it doesn't work out, the info won't be wasted. */ length = token & ML_MASK; /* match length */ + DEBUGLOG(7, "blockPos%6u: matchLength token = %u (len=%u)", (unsigned)(op-(BYTE*)dst), (unsigned)length, (unsigned)length + 4); offset = LZ4_readLE16(ip); ip += 2; match = op - offset; assert(match <= op); /* check overflow */ @@ -2222,20 +2271,27 @@ LZ4_decompress_generic( goto _copy_match; } +#if LZ4_FAST_DEC_LOOP + safe_literal_copy_early: +#endif + /* decode literal length */ if (length == RUN_MASK) { - size_t const addl = read_variable_length(&ip, iend-RUN_MASK, 1); + /* literal length >= RUN_MASK means >= RUN_MASK literal bytes follow the extension bytes, + * so extension bytes cannot reach the last RUN_MASK bytes of input */ + size_t const addl = read_variable_length(&ip, iend-RUN_MASK); if (addl == rvl_error) { goto _output_error; } length += addl; if (unlikely((uptrval)(op)+length<(uptrval)(op))) { goto _output_error; } /* overflow detection */ if (unlikely((uptrval)(ip)+length<(uptrval)(ip))) { goto _output_error; } /* overflow detection */ } + /* copy literals */ + cpy = op+length; + #if LZ4_FAST_DEC_LOOP safe_literal_copy: #endif - /* copy literals */ - cpy = op+length; LZ4_STATIC_ASSERT(MFLIMIT >= WILDCOPYLENGTH); if ((cpy>oend-MFLIMIT) || (ip+length>iend-(2+1+LASTLITERALS))) { @@ -2272,9 +2328,10 @@ LZ4_decompress_generic( * so check that we exactly consume the input and don't overrun the output buffer. */ if ((ip+length != iend) || (cpy > oend)) { - DEBUGLOG(6, "should have been last run of literals") - DEBUGLOG(6, "ip(%p) + length(%i) = %p != iend (%p)", ip, (int)length, ip+length, iend); - DEBUGLOG(6, "or cpy(%p) > oend(%p)", cpy, oend); + DEBUGLOG(5, "should have been last run of literals") + DEBUGLOG(5, "ip(%p) + length(%i) = %p != iend (%p)", (void*)ip, (int)length, (void*)(ip+length), (void*)iend); + DEBUGLOG(5, "or cpy(%p) > (oend-MFLIMIT)(%p)", (void*)cpy, (void*)(oend-MFLIMIT)); + DEBUGLOG(5, "after writing %u bytes / %i bytes available", (unsigned)(op-(BYTE*)dst), outputSize); goto _output_error; } } @@ -2300,10 +2357,12 @@ LZ4_decompress_generic( /* get matchlength */ length = token & ML_MASK; + DEBUGLOG(7, "blockPos%6u: matchLength token = %u", (unsigned)(op-(BYTE*)dst), (unsigned)length); _copy_match: if (length == ML_MASK) { - size_t const addl = read_variable_length(&ip, iend - LASTLITERALS + 1, 0); + /* after match length extension bytes, at least 1 token + LASTLITERALS literals must remain */ + size_t const addl = read_variable_length(&ip, iend - (1 + LASTLITERALS)); if (addl == rvl_error) { goto _output_error; } length += addl; if (unlikely((uptrval)(op)+length<(uptrval)op)) goto _output_error; /* overflow detection */ @@ -2389,7 +2448,7 @@ LZ4_decompress_generic( while (op < cpy) { *op++ = *match++; } } else { LZ4_memcpy(op, match, 8); - if (length > 16) { LZ4_wildCopy8(op+8, match+8, cpy); } + if (length > 16) { LZ4_wildCopy8(op+8, match+8, cpy); } } op = cpy; /* wildcopy correction */ } diff --git a/libs/fst/lz4.h b/libs/fst/lz4.h index 7a2dbfd4b..5b147b29d 100644 --- a/libs/fst/lz4.h +++ b/libs/fst/lz4.h @@ -1,7 +1,7 @@ /* * LZ4 - Fast LZ compression algorithm * Header File - * Copyright (C) 2011-2023, Yann Collet. + * Copyright (c) Yann Collet. All rights reserved. BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) @@ -129,8 +129,8 @@ extern "C" { /*------ Version ------*/ #define LZ4_VERSION_MAJOR 1 /* for breaking interface changes */ -#define LZ4_VERSION_MINOR 9 /* for new (non-breaking) interface capabilities */ -#define LZ4_VERSION_RELEASE 5 /* for tweaks, bug-fixes, or development */ +#define LZ4_VERSION_MINOR 10 /* for new (non-breaking) interface capabilities */ +#define LZ4_VERSION_RELEASE 0 /* for tweaks, bug-fixes, or development */ #define LZ4_VERSION_NUMBER (LZ4_VERSION_MAJOR *100*100 + LZ4_VERSION_MINOR *100 + LZ4_VERSION_RELEASE) @@ -148,6 +148,7 @@ LZ4LIB_API const char* LZ4_versionString (void); /**< library version string; **************************************/ /*! * LZ4_MEMORY_USAGE : + * Can be selected at compile time, by setting LZ4_MEMORY_USAGE. * Memory usage formula : N->2^N Bytes (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB) * Increasing memory usage improves compression ratio, generally at the cost of speed. * Reduced memory usage may improve speed at the cost of ratio, thanks to better cache locality. @@ -157,6 +158,7 @@ LZ4LIB_API const char* LZ4_versionString (void); /**< library version string; # define LZ4_MEMORY_USAGE LZ4_MEMORY_USAGE_DEFAULT #endif +/* These are absolute limits, they should not be changed by users */ #define LZ4_MEMORY_USAGE_MIN 10 #define LZ4_MEMORY_USAGE_DEFAULT 14 #define LZ4_MEMORY_USAGE_MAX 20 @@ -256,10 +258,12 @@ LZ4LIB_API int LZ4_compress_fast_extState (void* state, const char* src, char* d * @return : Nb bytes written into 'dst' (necessarily <= dstCapacity) * or 0 if compression fails. * - * Note : from v1.8.2 to v1.9.1, this function had a bug (fixed in v1.9.2+): - * the produced compressed content could, in specific circumstances, - * require to be decompressed into a destination buffer larger - * by at least 1 byte than the content to decompress. + * Note : 'targetDstSize' must be >= 1, because it's the smallest valid lz4 payload. + * + * Note 2:from v1.8.2 to v1.9.1, this function had a bug (fixed in v1.9.2+): + * the produced compressed content could, in rare circumstances, + * require to be decompressed into a destination buffer + * larger by at least 1 byte than decompressesSize. * If an application uses `LZ4_compress_destSize()`, * it's highly recommended to update liblz4 to v1.9.2 or better. * If this can't be done or ensured, @@ -368,6 +372,51 @@ LZ4LIB_API void LZ4_resetStream_fast (LZ4_stream_t* streamPtr); */ LZ4LIB_API int LZ4_loadDict (LZ4_stream_t* streamPtr, const char* dictionary, int dictSize); +/*! LZ4_loadDictSlow() : v1.10.0+ + * Same as LZ4_loadDict(), + * but uses a bit more cpu to reference the dictionary content more thoroughly. + * This is expected to slightly improve compression ratio. + * The extra-cpu cost is likely worth it if the dictionary is re-used across multiple sessions. + * @return : loaded dictionary size, in bytes (note: only the last 64 KB are loaded) + */ +LZ4LIB_API int LZ4_loadDictSlow(LZ4_stream_t* streamPtr, const char* dictionary, int dictSize); + +/*! LZ4_attach_dictionary() : stable since v1.10.0 + * + * This allows efficient re-use of a static dictionary multiple times. + * + * Rather than re-loading the dictionary buffer into a working context before + * each compression, or copying a pre-loaded dictionary's LZ4_stream_t into a + * working LZ4_stream_t, this function introduces a no-copy setup mechanism, + * in which the working stream references @dictionaryStream in-place. + * + * Several assumptions are made about the state of @dictionaryStream. + * Currently, only states which have been prepared by LZ4_loadDict() or + * LZ4_loadDictSlow() should be expected to work. + * + * Alternatively, the provided @dictionaryStream may be NULL, + * in which case any existing dictionary stream is unset. + * + * If a dictionary is provided, it replaces any pre-existing stream history. + * The dictionary contents are the only history that can be referenced and + * logically immediately precede the data compressed in the first subsequent + * compression call. + * + * The dictionary will only remain attached to the working stream through the + * first compression call, at the end of which it is cleared. + * @dictionaryStream stream (and source buffer) must remain in-place / accessible / unchanged + * through the completion of the compression session. + * + * Note: there is no equivalent LZ4_attach_*() method on the decompression side + * because there is no initialization cost, hence no need to share the cost across multiple sessions. + * To decompress LZ4 blocks using dictionary, attached or not, + * just employ the regular LZ4_setStreamDecode() for streaming, + * or the stateless LZ4_decompress_safe_usingDict() for one-shot decompression. + */ +LZ4LIB_API void +LZ4_attach_dictionary(LZ4_stream_t* workingStream, + const LZ4_stream_t* dictionaryStream); + /*! LZ4_compress_fast_continue() : * Compress 'src' content using data from previously compressed blocks, for better compression ratio. * 'dst' buffer must be already allocated. @@ -563,43 +612,12 @@ LZ4_decompress_safe_partial_usingDict(const char* src, char* dst, */ LZ4LIB_STATIC_API int LZ4_compress_fast_extState_fastReset (void* state, const char* src, char* dst, int srcSize, int dstCapacity, int acceleration); -/*! LZ4_compress_destSize_extState() : +/*! LZ4_compress_destSize_extState() : introduced in v1.10.0 * Same as LZ4_compress_destSize(), but using an externally allocated state. * Also: exposes @acceleration */ int LZ4_compress_destSize_extState(void* state, const char* src, char* dst, int* srcSizePtr, int targetDstSize, int acceleration); -/*! LZ4_attach_dictionary() : - * This is an experimental API that allows - * efficient use of a static dictionary many times. - * - * Rather than re-loading the dictionary buffer into a working context before - * each compression, or copying a pre-loaded dictionary's LZ4_stream_t into a - * working LZ4_stream_t, this function introduces a no-copy setup mechanism, - * in which the working stream references the dictionary stream in-place. - * - * Several assumptions are made about the state of the dictionary stream. - * Currently, only streams which have been prepared by LZ4_loadDict() should - * be expected to work. - * - * Alternatively, the provided dictionaryStream may be NULL, - * in which case any existing dictionary stream is unset. - * - * If a dictionary is provided, it replaces any pre-existing stream history. - * The dictionary contents are the only history that can be referenced and - * logically immediately precede the data compressed in the first subsequent - * compression call. - * - * The dictionary will only remain attached to the working stream through the - * first compression call, at the end of which it is cleared. The dictionary - * stream (and source buffer) must remain in-place / accessible / unchanged - * through the completion of the first compression call on the stream. - */ -LZ4LIB_STATIC_API void -LZ4_attach_dictionary(LZ4_stream_t* workingStream, - const LZ4_stream_t* dictionaryStream); - - /*! In-place compression and decompression * * It's possible to have input and output sharing the same buffer, @@ -682,10 +700,10 @@ LZ4_attach_dictionary(LZ4_stream_t* workingStream, #if defined(__cplusplus) || (defined (__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) /* C99 */) # include - typedef int8_t LZ4_i8; - typedef uint8_t LZ4_byte; - typedef uint16_t LZ4_u16; - typedef uint32_t LZ4_u32; + typedef int8_t LZ4_i8; + typedef unsigned char LZ4_byte; + typedef uint16_t LZ4_u16; + typedef uint32_t LZ4_u32; #else typedef signed char LZ4_i8; typedef unsigned char LZ4_byte; From 25810193ab72e80041a7a6728e3e3685e7c5610b Mon Sep 17 00:00:00 2001 From: nella Date: Thu, 18 Jun 2026 10:57:20 +0200 Subject: [PATCH 032/101] Reuse sat/hashlib. --- kernel/bitsim.h | 16 ++++++++-------- passes/opt/opt_dff.cc | 19 ++++++------------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/kernel/bitsim.h b/kernel/bitsim.h index a0915e28b..c659a5e34 100644 --- a/kernel/bitsim.h +++ b/kernel/bitsim.h @@ -15,10 +15,10 @@ struct BitSim { BitSim(Module *m, SigMap &sm, ModWalker &mw) : module(m), sigmap(sm), modwalker(mw), rng_state(1337) {} - uint64_t xorshift64() { - rng_state ^= rng_state << 13; - rng_state ^= rng_state >> 7; - rng_state ^= rng_state << 17; + uint64_t next_rand() { + uint32_t lo = mkhash_xorshift((uint32_t)rng_state); + uint32_t hi = mkhash_xorshift((uint32_t)(rng_state >> 32) ^ lo); + rng_state = ((uint64_t)hi << 32) | lo; return rng_state; } @@ -34,17 +34,17 @@ struct BitSim { uint64_t res = 0; if (!modwalker.has_drivers(mapped)) { - res = xorshift64(); + res = next_rand(); } else { auto &drivers = modwalker.signal_drivers[mapped]; if (drivers.empty()) { - res = xorshift64(); + res = next_rand(); } else { auto driver = *drivers.begin(); Cell *cell = driver.cell; if (cell->is_builtin_ff()) { - res = xorshift64(); + res = next_rand(); } else if (cell->type == ID($_AND_)) { res = eval_bit(cell->getPort(ID::A)[0]) & eval_bit(cell->getPort(ID::B)[0]); } else if (cell->type == ID($_OR_)) { @@ -64,7 +64,7 @@ struct BitSim { uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset]); res = (a & ~s) | (b & s); } else { - res = xorshift64(); + res = next_rand(); } } } diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 500df142e..6984f3f4b 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -968,14 +968,6 @@ struct OptDffWorker return s == State::S0 || s == State::S1; } - int sat_mux(QuickConeSat &qcsat, int s, int a, int b) { - return qcsat.ez->OR(qcsat.ez->AND(s, a), qcsat.ez->AND(qcsat.ez->NOT(s), b)); - } - - int sat_const(QuickConeSat &qcsat, State v) { - return v == State::S1 ? qcsat.ez->CONST_TRUE : qcsat.ez->CONST_FALSE; - } - std::vector> gather_initial_eq_classes(std::vector &bits, dict &ff_for_cell) { std::vector keys; @@ -1065,7 +1057,7 @@ struct OptDffWorker // Assume same class for (auto &cls : classes) { - uint64_t class_q_val = sim.xorshift64(); + uint64_t class_q_val = sim.next_rand(); for (int idx : cls) { sim.sim_vals[sigmap(bits[idx].q)] = class_q_val; } @@ -1137,12 +1129,12 @@ struct OptDffWorker if (ff.has_aload) { int al = qcsat.importSigBit(ff.sig_aload); if (!ff.pol_aload) al = qcsat.ez->NOT(al); - n = sat_mux(qcsat, al, qcsat.importSigBit(ff.sig_ad[eb.idx]), n); + n = qcsat.ez->ITE(al, qcsat.importSigBit(ff.sig_ad[eb.idx]), n); } if (ff.has_arst) { int ar = qcsat.importSigBit(ff.sig_arst); if (!ff.pol_arst) ar = qcsat.ez->NOT(ar); - n = sat_mux(qcsat, ar, sat_const(qcsat, ff.val_arst[eb.idx]), n); + n = qcsat.ez->ITE(ar, qcsat.ez->value(ff.val_arst[eb.idx] == State::S1), n); } if (ff.has_sr) { int clr = qcsat.importSigBit(ff.sig_clr[eb.idx]); @@ -1154,7 +1146,7 @@ struct OptDffWorker if (ff.has_srst) { int srst = qcsat.importSigBit(ff.sig_srst); if (!ff.pol_srst) srst = qcsat.ez->NOT(srst); - n = sat_mux(qcsat, srst, sat_const(qcsat, ff.val_srst[eb.idx]), n); + n = qcsat.ez->ITE(srst, qcsat.ez->value(ff.val_srst[eb.idx] == State::S1), n); } n_lit[idx] = n; @@ -1191,7 +1183,8 @@ struct OptDffWorker if (n_lit[rep] == n_lit[cls[i]]) continue; - int query = qcsat.ez->NOT(qcsat.ez->IFF(n_lit[rep], n_lit[cls[i]])); + // next-state bits differ + int query = qcsat.ez->XOR(n_lit[rep], n_lit[cls[i]]); std::vector modelExprs; for (int b : cls) modelExprs.push_back(n_lit[b]); From 75a30a22d655c591758daed5b4f392791162387f Mon Sep 17 00:00:00 2001 From: nella Date: Thu, 18 Jun 2026 11:43:13 +0200 Subject: [PATCH 033/101] Cleanup bitsim, document hypo. --- kernel/bitsim.h | 79 --------------------------------- passes/opt/opt_dff.cc | 101 +++++++++++++++++++++++++++++++++++++++--- 2 files changed, 94 insertions(+), 86 deletions(-) delete mode 100644 kernel/bitsim.h diff --git a/kernel/bitsim.h b/kernel/bitsim.h deleted file mode 100644 index c659a5e34..000000000 --- a/kernel/bitsim.h +++ /dev/null @@ -1,79 +0,0 @@ -#ifndef BITSIM_H -#define BITSIM_H - -#include "kernel/modtools.h" - -YOSYS_NAMESPACE_BEGIN - -struct BitSim { - Module *module; - SigMap &sigmap; - ModWalker &modwalker; - dict sim_vals; - uint64_t rng_state; - - BitSim(Module *m, SigMap &sm, ModWalker &mw) - : module(m), sigmap(sm), modwalker(mw), rng_state(1337) {} - - uint64_t next_rand() { - uint32_t lo = mkhash_xorshift((uint32_t)rng_state); - uint32_t hi = mkhash_xorshift((uint32_t)(rng_state >> 32) ^ lo); - rng_state = ((uint64_t)hi << 32) | lo; - return rng_state; - } - - uint64_t eval_bit(SigBit b) { - SigBit mapped = sigmap(b); - if (mapped == State::S0) return 0ULL; - if (mapped == State::S1) return ~0ULL; - if (mapped == State::Sx || mapped == State::Sz) return 0ULL; - - auto it = sim_vals.find(mapped); - if (it != sim_vals.end()) return it->second; - sim_vals[mapped] = 0; - uint64_t res = 0; - - if (!modwalker.has_drivers(mapped)) { - res = next_rand(); - } else { - auto &drivers = modwalker.signal_drivers[mapped]; - if (drivers.empty()) { - res = next_rand(); - } else { - auto driver = *drivers.begin(); - Cell *cell = driver.cell; - - if (cell->is_builtin_ff()) { - res = next_rand(); - } else if (cell->type == ID($_AND_)) { - res = eval_bit(cell->getPort(ID::A)[0]) & eval_bit(cell->getPort(ID::B)[0]); - } else if (cell->type == ID($_OR_)) { - res = eval_bit(cell->getPort(ID::A)[0]) | eval_bit(cell->getPort(ID::B)[0]); - } else if (cell->type == ID($_XOR_)) { - res = eval_bit(cell->getPort(ID::A)[0]) ^ eval_bit(cell->getPort(ID::B)[0]); - } else if (cell->type == ID($_NOT_)) { - res = ~eval_bit(cell->getPort(ID::A)[0]); - } else if (cell->type == ID($_MUX_)) { - uint64_t s = eval_bit(cell->getPort(ID::S)[0]); - uint64_t a = eval_bit(cell->getPort(ID::A)[0]); - uint64_t b = eval_bit(cell->getPort(ID::B)[0]); - res = (a & ~s) | (b & s); - } else if (cell->type == ID($mux)) { - uint64_t s = eval_bit(cell->getPort(ID::S)[0]); - uint64_t a = eval_bit(cell->getPort(ID::A)[driver.offset]); - uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset]); - res = (a & ~s) | (b & s); - } else { - res = next_rand(); - } - } - } - - sim_vals[mapped] = res; - return res; - } -}; - -YOSYS_NAMESPACE_END - -#endif diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 6984f3f4b..e87fcb716 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -26,7 +26,6 @@ #include "kernel/sigtools.h" #include "kernel/ffinit.h" #include "kernel/ff.h" -#include "kernel/bitsim.h" #include "kernel/pattern.h" #include "passes/techmap/simplemap.h" #include @@ -44,6 +43,76 @@ struct OptDffOptions bool keepdc; }; +// Bit-parallel random simulation used as a cheap pre-filter for equivalence +struct BitSim { + Module *module; + SigMap &sigmap; + ModWalker &modwalker; + dict sim_vals; + uint64_t rng_state; + + BitSim(Module *m, SigMap &sm, ModWalker &mw) + : module(m), sigmap(sm), modwalker(mw), rng_state(1337) {} + + uint64_t next_rand() { + uint32_t lo = mkhash_xorshift((uint32_t)rng_state); + uint32_t hi = mkhash_xorshift((uint32_t)(rng_state >> 32) ^ lo); + rng_state = ((uint64_t)hi << 32) | lo; + return rng_state; + } + + uint64_t eval_bit(SigBit b) { + SigBit mapped = sigmap(b); + if (mapped == State::S0) return 0ULL; + if (mapped == State::S1) return ~0ULL; + if (mapped == State::Sx || mapped == State::Sz) return 0ULL; + + auto it = sim_vals.find(mapped); + if (it != sim_vals.end()) return it->second; + sim_vals[mapped] = 0; + uint64_t res = 0; + + if (!modwalker.has_drivers(mapped)) { + res = next_rand(); + } else { + auto &drivers = modwalker.signal_drivers[mapped]; + if (drivers.empty()) { + res = next_rand(); + } else { + auto driver = *drivers.begin(); + Cell *cell = driver.cell; + + if (cell->is_builtin_ff()) { + res = next_rand(); + } else if (cell->type == ID($_AND_)) { + res = eval_bit(cell->getPort(ID::A)[0]) & eval_bit(cell->getPort(ID::B)[0]); + } else if (cell->type == ID($_OR_)) { + res = eval_bit(cell->getPort(ID::A)[0]) | eval_bit(cell->getPort(ID::B)[0]); + } else if (cell->type == ID($_XOR_)) { + res = eval_bit(cell->getPort(ID::A)[0]) ^ eval_bit(cell->getPort(ID::B)[0]); + } else if (cell->type == ID($_NOT_)) { + res = ~eval_bit(cell->getPort(ID::A)[0]); + } else if (cell->type == ID($_MUX_)) { + uint64_t s = eval_bit(cell->getPort(ID::S)[0]); + uint64_t a = eval_bit(cell->getPort(ID::A)[0]); + uint64_t b = eval_bit(cell->getPort(ID::B)[0]); + res = (a & ~s) | (b & s); + } else if (cell->type == ID($mux)) { + uint64_t s = eval_bit(cell->getPort(ID::S)[0]); + uint64_t a = eval_bit(cell->getPort(ID::A)[driver.offset]); + uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset]); + res = (a & ~s) | (b & s); + } else { + res = next_rand(); + } + } + } + + sim_vals[mapped] = res; + return res; + } +}; + struct OptDffWorker { const OptDffOptions &opt; @@ -927,6 +996,8 @@ struct OptDffWorker SigBit q; }; + // NOTE: This intentionally duplicates a subset of FfData, as flattening just the + // fields that matter for merging into a single comparable/hashable key is cheaper struct SigKey { enum Flag : uint16_t { InitOne = 1u << 0, @@ -965,6 +1036,7 @@ struct OptDffWorker }; bool is_def(State s) { + // Concrete constant bit (0 or 1), as opposed to x/z return s == State::S0 || s == State::S1; } @@ -984,11 +1056,12 @@ struct OptDffWorker ff_for_cell.emplace(cell, ff); for (int i = 0; i < ff.width; i++) { - // X value + // Skip bits whose reset drives an undefined (x) value if (ff.has_srst && !is_def(ff.val_srst[i])) continue; if (ff.has_arst && !is_def(ff.val_arst[i])) continue; - // Missing anchor + // Class members are assumed equal in the current cycle and proven equal in the next, which needs + // a base case anchoring them to a common known value bool def_init = is_def(ff.val_init[i]); if (!def_init && !ff.has_srst && !ff.has_arst) continue; @@ -1118,7 +1191,11 @@ struct OptDffWorker std::vector q_lit(bits.size(), -1); std::vector n_lit(bits.size(), -1); - // Per candidate SAT for its next state, model difference + // Build the next-state function n_lit[idx] of every candidate bit by + // folding the FF's control logic on top of the D input (-> next value) + + // Two bits are equivalent if their next states always agree whenever their + // current states (and those of every other candidate pair) agree for (auto &cls : classes) { for (int idx : cls) { const EqBit &eb = bits[idx]; @@ -1154,6 +1231,12 @@ struct OptDffWorker } qcsat.prepare(); + + // Assume the induction hypo (that every current class is internally equal in the present cycle), and try + // to prove that the members of each class therefore also agree in the next cycle + + // A class survives only if no counterexample exists under that hypo, so combined with the common init/reset + // value that every class shares, this makes the equality an inductive invariant -> bits are eq and safe to merge std::vector worklist; std::vector in_worklist(GetSize(classes), true); @@ -1168,6 +1251,7 @@ struct OptDffWorker auto &cls = classes[cls_idx]; if (GetSize(cls) < 2) continue; + // Induction hypo: assume every candidate class is equal std::vector assumptions; for (auto &c : classes) { if (GetSize(c) < 2) continue; @@ -1176,15 +1260,18 @@ struct OptDffWorker assumptions.push_back(qcsat.ez->IFF(q_lit[rep], q_lit[c[k]])); } - // Split at counterexamples + // Scan the class members against the representative and issue a query per pair, + // stopping early at the first counterexample, which is reused to split the entire + // class at once int rep = cls[0]; for (int i = 1; i < GetSize(cls); i++) { - // Trivially equivalent if (n_lit[rep] == n_lit[cls[i]]) continue; - // next-state bits differ + // Can the next state of the rep and this member ever differ? int query = qcsat.ez->XOR(n_lit[rep], n_lit[cls[i]]); + // Capture every member's next-state value in that model so one counterexample + // partitions the whole class std::vector modelExprs; for (int b : cls) modelExprs.push_back(n_lit[b]); From 46cbeab720af3421da88f932aeb38aaa5c34381e Mon Sep 17 00:00:00 2001 From: nella Date: Thu, 18 Jun 2026 11:58:01 +0200 Subject: [PATCH 034/101] Add effort limit. --- passes/opt/opt_dff.cc | 39 +++++++++++++++++++++++++++------------ 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index e87fcb716..1b1c3bf0e 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -50,9 +50,15 @@ struct BitSim { ModWalker &modwalker; dict sim_vals; uint64_t rng_state; + int max_depth; + int evals_left; BitSim(Module *m, SigMap &sm, ModWalker &mw) - : module(m), sigmap(sm), modwalker(mw), rng_state(1337) {} + : module(m), sigmap(sm), modwalker(mw), rng_state(1337) + { + max_depth = module->design->scratchpad_get_int("opt_dff.sim_depth", 10000); + evals_left = module->design->scratchpad_get_int("opt_dff.sim_evals", 1000000); + } uint64_t next_rand() { uint32_t lo = mkhash_xorshift((uint32_t)rng_state); @@ -61,7 +67,7 @@ struct BitSim { return rng_state; } - uint64_t eval_bit(SigBit b) { + uint64_t eval_bit(SigBit b, int depth = 0) { SigBit mapped = sigmap(b); if (mapped == State::S0) return 0ULL; if (mapped == State::S1) return ~0ULL; @@ -69,6 +75,15 @@ struct BitSim { auto it = sim_vals.find(mapped); if (it != sim_vals.end()) return it->second; + + // Failsafe for huge designs + if (depth >= max_depth || evals_left <= 0) { + uint64_t r = next_rand(); + sim_vals[mapped] = r; + return r; + } + evals_left--; + sim_vals[mapped] = 0; uint64_t res = 0; @@ -85,22 +100,22 @@ struct BitSim { if (cell->is_builtin_ff()) { res = next_rand(); } else if (cell->type == ID($_AND_)) { - res = eval_bit(cell->getPort(ID::A)[0]) & eval_bit(cell->getPort(ID::B)[0]); + res = eval_bit(cell->getPort(ID::A)[0], depth+1) & eval_bit(cell->getPort(ID::B)[0], depth+1); } else if (cell->type == ID($_OR_)) { - res = eval_bit(cell->getPort(ID::A)[0]) | eval_bit(cell->getPort(ID::B)[0]); + res = eval_bit(cell->getPort(ID::A)[0], depth+1) | eval_bit(cell->getPort(ID::B)[0], depth+1); } else if (cell->type == ID($_XOR_)) { - res = eval_bit(cell->getPort(ID::A)[0]) ^ eval_bit(cell->getPort(ID::B)[0]); + res = eval_bit(cell->getPort(ID::A)[0], depth+1) ^ eval_bit(cell->getPort(ID::B)[0], depth+1); } else if (cell->type == ID($_NOT_)) { - res = ~eval_bit(cell->getPort(ID::A)[0]); + res = ~eval_bit(cell->getPort(ID::A)[0], depth+1); } else if (cell->type == ID($_MUX_)) { - uint64_t s = eval_bit(cell->getPort(ID::S)[0]); - uint64_t a = eval_bit(cell->getPort(ID::A)[0]); - uint64_t b = eval_bit(cell->getPort(ID::B)[0]); + uint64_t s = eval_bit(cell->getPort(ID::S)[0], depth+1); + uint64_t a = eval_bit(cell->getPort(ID::A)[0], depth+1); + uint64_t b = eval_bit(cell->getPort(ID::B)[0], depth+1); res = (a & ~s) | (b & s); } else if (cell->type == ID($mux)) { - uint64_t s = eval_bit(cell->getPort(ID::S)[0]); - uint64_t a = eval_bit(cell->getPort(ID::A)[driver.offset]); - uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset]); + uint64_t s = eval_bit(cell->getPort(ID::S)[0], depth+1); + uint64_t a = eval_bit(cell->getPort(ID::A)[driver.offset], depth+1); + uint64_t b = eval_bit(cell->getPort(ID::B)[driver.offset], depth+1); res = (a & ~s) | (b & s); } else { res = next_rand(); From 338d4adef2529938cbd77f5b8f2b78786ca5ff53 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 19 Jun 2026 10:18:27 +1200 Subject: [PATCH 035/101] write_verilog: Fix upto indexing for single bit --- backends/verilog/verilog_backend.cc | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index fd9986144..68e2ee20e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -197,14 +197,22 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) reg_name = id(chunk.wire->name); if (sig.size() != chunk.wire->width) { - if (sig.size() == 1) - reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset); - else if (chunk.wire->upto) - reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset, - (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); + int idx; + if (chunk.wire->upto) + idx = (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset; else - reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1, - chunk.wire->start_offset + chunk.offset); + idx = chunk.wire->start_offset + chunk.offset; + + if (sig.size() == 1) + reg_name += stringf("[%d]", idx); + else { + int left_idx; + if (chunk.wire->upto) + left_idx = (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset; + else + left_idx = chunk.wire->start_offset + chunk.offset + chunk.width - 1; + reg_name += stringf("[%d:%d]", left_idx, idx); + } } return true; From b77bb851edf69e7f8e85b8b2bbe56d245a0c6869 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 19 Jun 2026 11:15:08 +1200 Subject: [PATCH 036/101] tests: Add mixed_upto write_verilog test --- tests/Makefile | 1 + tests/write_verilog/generate_mk.py | 37 ++++++++++++++++++++++++++++++ tests/write_verilog/mixed_upto.sv | 13 +++++++++++ 3 files changed, 51 insertions(+) create mode 100644 tests/write_verilog/generate_mk.py create mode 100644 tests/write_verilog/mixed_upto.sv diff --git a/tests/Makefile b/tests/Makefile index 1721dba71..fb442ffff 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -75,6 +75,7 @@ MK_TEST_DIRS += ./memories MK_TEST_DIRS += ./aiger MK_TEST_DIRS += ./alumacc MK_TEST_DIRS += ./check_mem +MK_TEST_DIRS += ./write_verilog all: vanilla-test diff --git a/tests/write_verilog/generate_mk.py b/tests/write_verilog/generate_mk.py new file mode 100644 index 000000000..bdcf93a65 --- /dev/null +++ b/tests/write_verilog/generate_mk.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 + +import glob + +import sys +sys.path.append("..") + +import gen_tests_makefile + +def generate_write_test(sv_file: str): + # if the first line of the file starts with // (ie a comment), the rest of + # the line is treated as the commands to run after reading the input + header_cmds = "" + with open(sv_file, "r") as f: + line = f.readline().rstrip() + if line.startswith("//"): + header_cmds = line[3:] + + # process input & write output + read_cmd = f"read -sv {sv_file}; {header_cmds}" + out_file = f"{sv_file}.out" + out_yosys_cmd = f"{read_cmd}; rename gold gate; write_verilog {out_file}" + out_cmd = f'$(YOSYS) -l {out_file}.err -p "{out_yosys_cmd}" && mv {out_file}.err {out_file}.log' + gen_tests_makefile.generate_target(out_file, out_cmd) + + # test input & output equivalence + equiv = "equiv_make gold gate equiv; equiv_induct equiv; equiv_status -assert equiv" + yosys_cmd = f"{read_cmd}; design -stash gold; read -sv {out_file}; {header_cmds}; design -import gold; {equiv}" + cmd = f'$(YOSYS) -l {sv_file}.err -p "{yosys_cmd}" && mv {sv_file}.err {sv_file}.log' + gen_tests_makefile.generate_target(sv_file, cmd, [out_file]) + +def generate_write_tests(): + # currently configured to use `read -sv` on each + for f in sorted(glob.glob("*.sv")): + generate_write_test(f) + +gen_tests_makefile.generate_custom(generate_write_tests) diff --git a/tests/write_verilog/mixed_upto.sv b/tests/write_verilog/mixed_upto.sv new file mode 100644 index 000000000..3ef608c99 --- /dev/null +++ b/tests/write_verilog/mixed_upto.sv @@ -0,0 +1,13 @@ +// hierarchy; proc;; simplemap +module gold( + input clk, + input [1:0] in, + output reg [1:0] out +); + reg [0:1] r; + + always @(posedge clk) begin + out <= r; + r <= in; + end +endmodule From 54d43d85e302ca15d8dc0c05f935a9ed03821f31 Mon Sep 17 00:00:00 2001 From: Amelia Dobis <22934557+dobios@users.noreply.github.com> Date: Fri, 19 Jun 2026 17:30:28 -0400 Subject: [PATCH 037/101] [docs] nit: usign the right acronym to refer to the right thing Tiny nit, but the description of `RTLIL::Wire` was using MSB and LSB to refer to the least and most significant *bits* of a wire and not Bytes, which should be referred to using LSb and MSb instead --- docs/source/yosys_internals/formats/rtlil_rep.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst index dbd69c7e4..580285e8a 100644 --- a/docs/source/yosys_internals/formats/rtlil_rep.rst +++ b/docs/source/yosys_internals/formats/rtlil_rep.rst @@ -158,8 +158,8 @@ An ``RTLIL::Wire`` object has the following properties: - The wire name - A list of attributes - A width (buses are just wires with a width more than 1) -- Bus direction (MSB to LSB or vice versa) -- Lowest valid bit index (LSB or MSB depending on bus direction) +- Bus direction (MSb to LSb or vice versa) +- Lowest valid bit index (LSb or MSb depending on bus direction) - If the wire is a port: port number and direction (input/output/inout) As with modules, the attributes can be Verilog attributes imported by the From 41566a6b70871e9278cffe3df2704f2d06e12d6a Mon Sep 17 00:00:00 2001 From: Amelia Dobis <22934557+dobios@users.noreply.github.com> Date: Fri, 19 Jun 2026 17:47:39 -0400 Subject: [PATCH 038/101] more typo found --- docs/source/yosys_internals/formats/rtlil_rep.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst index 580285e8a..0fa09a3bc 100644 --- a/docs/source/yosys_internals/formats/rtlil_rep.rst +++ b/docs/source/yosys_internals/formats/rtlil_rep.rst @@ -171,8 +171,8 @@ signals. This makes some aspects of RTLIL more complex but enables Yosys to be used for coarse grain synthesis where the cells of the target architecture operate on entire signal vectors instead of single bit wires. -In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either -the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB; +In Verilog and VHDL, busses may have arbitrary bounds, and LSb can have either +the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSb; however, information from the HDL frontend is preserved so that the bus will be correctly indexed in error messages, backend output, constraint files, etc. From ebcbc06951ae111f38c638919e069110a9ef226b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 22 Jun 2026 08:40:16 +0200 Subject: [PATCH 039/101] smtbmc: support latest bitwuzla --- backends/smt2/smtio.py | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index 2bc7daddc..b7897fa99 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -226,7 +226,7 @@ class SmtIo: print('timeout option is not supported for mathsat.') sys.exit(1) - if self.solver in ["boolector", "bitwuzla"]: + if self.solver == "boolector": if self.noincr: self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts else: @@ -236,6 +236,29 @@ class SmtIo: print('timeout option is not supported for %s.' % self.solver) sys.exit(1) + if self.solver == "bitwuzla": + try: + help_text = subprocess.check_output([self.solver, "--help"], text=True) + except FileNotFoundError: + print("%s SMT Solver '%s' not found in path." % (self.timestamp(), self.solver), flush=True) + sys.exit(1) + if "--lang" in help_text: + self.popen_vargs = [self.solver, '--lang', 'smt2'] + self.solver_opts + self.unroll = True + if self.timeout != 0: + self.popen_vargs.append('--time-limit') + self.popen_vargs.append('%d000' % self.timeout) + else: + # Versions before 0.3 + if self.noincr: + self.popen_vargs = [self.solver, '--smt2'] + self.solver_opts + else: + self.popen_vargs = [self.solver, '--smt2', '-i'] + self.solver_opts + self.unroll = True + if self.timeout != 0: + print('timeout option is not supported for %s.' % self.solver) + sys.exit(1) + if self.solver == "abc": if len(self.solver_opts) > 0: self.popen_vargs = ['yosys-abc', '-S', '; '.join(self.solver_opts)] From 94e43f7675cf9c528cf68015714067d6a8f3b002 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 22 Jun 2026 09:50:39 +0200 Subject: [PATCH 040/101] Remove define since snprintf is supported in MSVC now --- kernel/yosys_common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/yosys_common.h b/kernel/yosys_common.h index 645c36345..9e19814bd 100644 --- a/kernel/yosys_common.h +++ b/kernel/yosys_common.h @@ -77,7 +77,6 @@ # define strtok_r strtok_s # define strdup _strdup -# define snprintf _snprintf # define getcwd _getcwd # define mkdir _mkdir # define popen _popen From 8f5d2d5894bc09555d01fb22b59036786e170b99 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 22 Jun 2026 11:12:00 +0200 Subject: [PATCH 041/101] Use -assert-none. --- tests/various/muxcover_index.ys | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/various/muxcover_index.ys b/tests/various/muxcover_index.ys index 041d497a5..b8a9a2cb0 100644 --- a/tests/various/muxcover_index.ys +++ b/tests/various/muxcover_index.ys @@ -18,8 +18,8 @@ clean opt_expr -mux_bool select -assert-count 2 t:$_MUX8_ -select -assert-count 0 t:$_MUX_ t:$_MUX4_ t:$_MUX16_ -select -assert-count 0 t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_ +select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_ +select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_ techmap -map +/simcells.v t:$_MUX8_ design -stash gate @@ -47,8 +47,8 @@ clean opt_expr -mux_bool select -assert-count 3 t:$_MUX8_ -select -assert-count 0 t:$_MUX_ t:$_MUX4_ t:$_MUX16_ -select -assert-count 0 t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_ +select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_ +select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_ techmap -map +/simcells.v t:$_MUX8_ design -stash gate @@ -76,8 +76,8 @@ clean opt_expr -mux_bool select -assert-count 4 t:$_MUX8_ -select -assert-count 0 t:$_MUX_ t:$_MUX4_ t:$_MUX16_ -select -assert-count 0 t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_ +select -assert-none t:$_MUX_ t:$_MUX4_ t:$_MUX16_ +select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NAND_ t:$_NOR_ t:$_XNOR_ techmap -map +/simcells.v t:$_MUX8_ design -stash gate From ed654de3d9d444a276e0ecfcdfee25c30df1163c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 22 Jun 2026 16:22:13 +0200 Subject: [PATCH 042/101] Add mingw64 build to CI --- .github/workflows/extra-builds.yml | 46 ++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 260f676d5..603d91e5d 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -66,6 +66,51 @@ jobs: --config Release --parallel + mingw-build: + name: MINGW64 build + runs-on: windows-latest + needs: [pre_job] + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + steps: + - uses: actions/checkout@v5 + with: + submodules: true + persist-credentials: false + + - name: Setup MSYS2 (MINGW64) + uses: msys2/setup-msys2@v2 + with: + msystem: MINGW64 + update: true + + install: >- + base-devel + mingw-w64-x86_64-toolchain + mingw-w64-x86_64-cmake + mingw-w64-x86_64-gtest + mingw-w64-x86_64-pkgconf + mingw-w64-x86_64-python + mingw-w64-x86_64-tcl + mingw-w64-x86_64-libffi + mingw-w64-x86_64-git + + msys2-install: >- + bison + flex + gawk + diffutils + make + + - name: Build Yosys + shell: msys2 {0} + run: | + set -e + procs=$(nproc) + rm -rf build + cmake -S . -B build -DCMAKE_BUILD_TYPE=Release + cmake --build build -j${procs} + ctest --test-dir build/tests/unit --output-on-failure + wasi-build: name: WASI build needs: pre_job @@ -121,6 +166,7 @@ jobs: runs-on: ubuntu-latest needs: - vs-build + - mingw-build - wasi-build - nix-build if: always() From 09eef69e312cc8a92a5d29ca6a5bf0fecfc3c870 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 22 Jun 2026 17:51:26 +0200 Subject: [PATCH 043/101] synth_intel: fix broken dsp mapping --- techlibs/intel/CMakeLists.txt | 1 + techlibs/intel/synth_intel.cc | 3 +++ 2 files changed, 4 insertions(+) diff --git a/techlibs/intel/CMakeLists.txt b/techlibs/intel/CMakeLists.txt index a0b321edb..1f1d30b7a 100644 --- a/techlibs/intel/CMakeLists.txt +++ b/techlibs/intel/CMakeLists.txt @@ -40,6 +40,7 @@ yosys_pass(synth_intel max10/cells_sim.v max10/cells_map.v + max10/dsp_map.v cyclone10lp/cells_sim.v cyclone10lp/cells_map.v diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 0b0eb6ae9..982e0db10 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -176,6 +176,9 @@ struct SynthIntelPass : public ScriptPass { family_opt != "cyclone10lp") log_cmd_error("Invalid or no family specified: '%s'\n", family_opt); + if (family_opt != "max10") + nodsp = true; + log_header(design, "Executing SYNTH_INTEL pass.\n"); log_push(); From de6aa77dc835525cd56f64d0ebf9a2200eecb419 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 23 Jun 2026 10:54:00 +1200 Subject: [PATCH 044/101] equiv_opt: Add ignore-unknown-cells --- passes/equiv/equiv_opt.cc | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index f5eb75730..db793ac6a 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -69,7 +69,7 @@ struct EquivOptPass:public ScriptPass } std::string command, techmap_opts, make_opts; - bool assert, undef, multiclock, async2sync, nocheck; + bool assert, undef, ignore_unknown_cells, multiclock, async2sync, nocheck; void clear_flags() override { @@ -78,6 +78,7 @@ struct EquivOptPass:public ScriptPass make_opts = ""; assert = false; undef = false; + ignore_unknown_cells = false; multiclock = false; async2sync = false; nocheck = false; @@ -114,6 +115,10 @@ struct EquivOptPass:public ScriptPass undef = true; continue; } + if (args[argidx] == "-ignore-unknown-cells") { + ignore_unknown_cells = true; + continue; + } if (args[argidx] == "-nocheck") { nocheck = true; continue; @@ -197,12 +202,16 @@ struct EquivOptPass:public ScriptPass else opts = make_opts; run("equiv_make" + opts + " gold gate equiv"); + string induct_opts; if (help_mode) - run("equiv_induct [-undef] equiv"); - else if (undef) - run("equiv_induct -undef equiv"); - else - run("equiv_induct equiv"); + induct_opts = " [-undef] [-ignore-unknown-cells]"; + else { + if (undef) + induct_opts += " -undef"; + if (ignore_unknown_cells) + induct_opts += " -ignore-unknown-cells"; + } + run("equiv_induct" + induct_opts + " equiv"); if (help_mode) run("equiv_status [-assert] equiv"); else if (assert) From f362e1db0e9a71ecb3998d092d96d1db9e83ee98 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:12:43 +0200 Subject: [PATCH 045/101] Remove executable flag from .v files --- examples/smtbmc/glift/C7552.v | 0 examples/smtbmc/glift/C880.v | 0 examples/smtbmc/glift/alu2.v | 0 examples/smtbmc/glift/alu4.v | 0 examples/smtbmc/glift/t481.v | 0 examples/smtbmc/glift/too_large.v | 0 examples/smtbmc/glift/ttt2.v | 0 examples/smtbmc/glift/x1.v | 0 tests/sim/tb/tb_adff.v | 0 tests/sim/tb/tb_adffe.v | 0 tests/sim/tb/tb_adlatch.v | 0 tests/sim/tb/tb_aldff.v | 0 tests/sim/tb/tb_aldffe.v | 0 tests/sim/tb/tb_dff.v | 0 tests/sim/tb/tb_dffe.v | 0 tests/sim/tb/tb_dffsr.v | 0 tests/sim/tb/tb_dlatch.v | 0 tests/sim/tb/tb_dlatchsr.v | 0 tests/sim/tb/tb_sdff.v | 0 tests/sim/tb/tb_sdffce.v | 0 tests/sim/tb/tb_sdffe.v | 0 21 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 examples/smtbmc/glift/C7552.v mode change 100755 => 100644 examples/smtbmc/glift/C880.v mode change 100755 => 100644 examples/smtbmc/glift/alu2.v mode change 100755 => 100644 examples/smtbmc/glift/alu4.v mode change 100755 => 100644 examples/smtbmc/glift/t481.v mode change 100755 => 100644 examples/smtbmc/glift/too_large.v mode change 100755 => 100644 examples/smtbmc/glift/ttt2.v mode change 100755 => 100644 examples/smtbmc/glift/x1.v mode change 100755 => 100644 tests/sim/tb/tb_adff.v mode change 100755 => 100644 tests/sim/tb/tb_adffe.v mode change 100755 => 100644 tests/sim/tb/tb_adlatch.v mode change 100755 => 100644 tests/sim/tb/tb_aldff.v mode change 100755 => 100644 tests/sim/tb/tb_aldffe.v mode change 100755 => 100644 tests/sim/tb/tb_dff.v mode change 100755 => 100644 tests/sim/tb/tb_dffe.v mode change 100755 => 100644 tests/sim/tb/tb_dffsr.v mode change 100755 => 100644 tests/sim/tb/tb_dlatch.v mode change 100755 => 100644 tests/sim/tb/tb_dlatchsr.v mode change 100755 => 100644 tests/sim/tb/tb_sdff.v mode change 100755 => 100644 tests/sim/tb/tb_sdffce.v mode change 100755 => 100644 tests/sim/tb/tb_sdffe.v diff --git a/examples/smtbmc/glift/C7552.v b/examples/smtbmc/glift/C7552.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/C880.v b/examples/smtbmc/glift/C880.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/alu2.v b/examples/smtbmc/glift/alu2.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/alu4.v b/examples/smtbmc/glift/alu4.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/t481.v b/examples/smtbmc/glift/t481.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/too_large.v b/examples/smtbmc/glift/too_large.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/ttt2.v b/examples/smtbmc/glift/ttt2.v old mode 100755 new mode 100644 diff --git a/examples/smtbmc/glift/x1.v b/examples/smtbmc/glift/x1.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_adff.v b/tests/sim/tb/tb_adff.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_adffe.v b/tests/sim/tb/tb_adffe.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_adlatch.v b/tests/sim/tb/tb_adlatch.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_aldff.v b/tests/sim/tb/tb_aldff.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_aldffe.v b/tests/sim/tb/tb_aldffe.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_dff.v b/tests/sim/tb/tb_dff.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_dffe.v b/tests/sim/tb/tb_dffe.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_dffsr.v b/tests/sim/tb/tb_dffsr.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_dlatch.v b/tests/sim/tb/tb_dlatch.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_sdff.v b/tests/sim/tb/tb_sdff.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_sdffce.v b/tests/sim/tb/tb_sdffce.v old mode 100755 new mode 100644 diff --git a/tests/sim/tb/tb_sdffe.v b/tests/sim/tb/tb_sdffe.v old mode 100755 new mode 100644 From 1f0ac8fffcdca9df2b0171cc7372b4f6c50e1f78 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:14:20 +0200 Subject: [PATCH 046/101] Remove utf-8 marker --- tests/pyosys/test_design_run_pass.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py index f0013577d..7638cc064 100644 --- a/tests/pyosys/test_design_run_pass.py +++ b/tests/pyosys/test_design_run_pass.py @@ -1,4 +1,4 @@ -from pathlib import Path +from pathlib import Path from pyosys import libyosys as ys __file_dir__ = Path(__file__).absolute().parent From 3ac58b3ac1f4059d122e1d4e8c22d5eb61c29b11 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:17:22 +0200 Subject: [PATCH 047/101] Fixed line endings --- examples/smtbmc/glift/C880.v | 902 +++---- techlibs/gatemate/arith_map.v | 138 +- techlibs/gatemate/brams_map.v | 1764 ++++++------- techlibs/gatemate/cells_bb.v | 680 ++--- techlibs/gatemate/cells_sim.v | 3684 +++++++++++++-------------- techlibs/gatemate/lut_map.v | 90 +- techlibs/gatemate/mux_map.v | 112 +- techlibs/gatemate/reg_map.v | 102 +- techlibs/gatemate/synth_gatemate.cc | 780 +++--- tests/arch/ecp5/bug1836.mem | 64 +- 10 files changed, 4158 insertions(+), 4158 deletions(-) diff --git a/examples/smtbmc/glift/C880.v b/examples/smtbmc/glift/C880.v index 18dc24cc5..20e665f4a 100644 --- a/examples/smtbmc/glift/C880.v +++ b/examples/smtbmc/glift/C880.v @@ -1,451 +1,451 @@ -module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, - pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59, - po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, - po20, po21, po22, po23, po24, po25); - -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, - pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59; - -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, - po20, po21, po22, po23, po24, po25; - -wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357, - n358, n359, n360, n361, n362, n363, n365, n366, n367, n368, - n369, n370, n371, n372, n373, n374, n375, n376, n378, n379, - n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, - n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n416, n417, n418, n419, n420, - n421, n422, n423, n424, n425, n426, n428, n429, n430, n431, - n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, - n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, - n452, n453, n455, n456, n457, n458, n459, n460, n461, n462, - n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, - n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, - n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, - n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, - n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, - n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, - n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, - n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, - n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, - n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, - n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, - n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, - n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, - n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, - n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, - n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, - n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, - n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, - n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, - n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, - n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, - n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, - n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, - n693, n694, n695, n696; - - -assign po22 = n137; -assign po19 = n346; -assign po16 = n364; -assign po17 = n415; -assign po18 = n295; -assign po00 = n427; -assign po09 = n351; -assign po04 = n377; -assign po06 = n454; - AN2 U371 ( .A(pi11), .B(pi08), .Z(n357)); - AN2 U372 ( .A(pi28), .B(n357), .Z(n346)); - AN2 U373 ( .A(pi41), .B(pi25), .Z(n369)); - AN2 U374 ( .A(pi52), .B(n369), .Z(n361)); - AN2 U375 ( .A(pi51), .B(pi54), .Z(n359)); - AN2 U376 ( .A(pi28), .B(pi31), .Z(n604)); - AN2 U377 ( .A(n604), .B(pi55), .Z(n358)); - AN2 U378 ( .A(n359), .B(n358), .Z(n602)); - AN2 U379 ( .A(pi53), .B(n602), .Z(n360)); - AN2 U380 ( .A(n361), .B(n360), .Z(n577)); - IV2 U381 ( .A(pi20), .Z(n607)); - OR2 U382 ( .A(n607), .B(pi25), .Z(n362)); - IV2 U383 ( .A(n362), .Z(n365)); - AN2 U384 ( .A(pi25), .B(n607), .Z(n363)); - OR2 U385 ( .A(n365), .B(n363), .Z(n367)); - AN2 U386 ( .A(pi41), .B(pi24), .Z(n378)); - AN2 U387 ( .A(n346), .B(n378), .Z(n366)); - AN2 U388 ( .A(n367), .B(n366), .Z(n373)); - AN2 U389 ( .A(pi28), .B(pi54), .Z(n368)); - AN2 U390 ( .A(pi20), .B(n368), .Z(n603)); - AN2 U391 ( .A(pi08), .B(n603), .Z(n371)); - IV2 U392 ( .A(pi56), .Z(n694)); - IV2 U393 ( .A(n369), .Z(n692)); - OR2 U394 ( .A(n694), .B(n692), .Z(n370)); - AN2 U395 ( .A(n371), .B(n370), .Z(n372)); - OR2 U396 ( .A(n373), .B(n372), .Z(n424)); - AN2 U397 ( .A(pi14), .B(n424), .Z(n384)); - AN2 U398 ( .A(pi56), .B(pi48), .Z(n608)); - AN2 U399 ( .A(n608), .B(n346), .Z(n374)); - AN2 U400 ( .A(pi07), .B(n374), .Z(n376)); - IV2 U401 ( .A(pi43), .Z(n375)); - AN2 U402 ( .A(n376), .B(n375), .Z(n406)); - AN2 U403 ( .A(pi20), .B(n406), .Z(n403)); - IV2 U404 ( .A(n378), .Z(n379)); - AN2 U405 ( .A(n346), .B(n379), .Z(n407)); - AN2 U406 ( .A(pi55), .B(n407), .Z(n399)); - AN2 U407 ( .A(pi44), .B(n399), .Z(n381)); - AN2 U408 ( .A(pi37), .B(pi54), .Z(n380)); - OR2 U409 ( .A(n381), .B(n380), .Z(n382)); - OR2 U410 ( .A(n403), .B(n382), .Z(n383)); - OR2 U411 ( .A(n384), .B(n383), .Z(n436)); - AN2 U412 ( .A(pi26), .B(n436), .Z(n385)); - OR2 U413 ( .A(n577), .B(n385), .Z(n386)); - AN2 U414 ( .A(pi34), .B(n386), .Z(n448)); - AN2 U415 ( .A(pi43), .B(pi05), .Z(n388)); - AN2 U416 ( .A(pi32), .B(n436), .Z(n387)); - OR2 U417 ( .A(n388), .B(n387), .Z(n446)); - AN2 U418 ( .A(pi08), .B(pi37), .Z(n393)); - AN2 U419 ( .A(pi50), .B(n399), .Z(n390)); - AN2 U420 ( .A(pi18), .B(n424), .Z(n389)); - OR2 U421 ( .A(n390), .B(n389), .Z(n391)); - OR2 U422 ( .A(n403), .B(n391), .Z(n392)); - OR2 U423 ( .A(n393), .B(n392), .Z(n494)); - AN2 U424 ( .A(pi27), .B(n494), .Z(n497)); - OR2 U425 ( .A(pi27), .B(n494), .Z(n499)); - AN2 U426 ( .A(pi20), .B(pi37), .Z(n398)); - AN2 U427 ( .A(pi45), .B(n399), .Z(n395)); - AN2 U428 ( .A(pi22), .B(n424), .Z(n394)); - OR2 U429 ( .A(n395), .B(n394), .Z(n396)); - OR2 U430 ( .A(n403), .B(n396), .Z(n397)); - OR2 U431 ( .A(n398), .B(n397), .Z(n536)); - AN2 U432 ( .A(pi17), .B(n536), .Z(n539)); - OR2 U433 ( .A(pi17), .B(n536), .Z(n541)); - AN2 U434 ( .A(pi23), .B(n424), .Z(n405)); - AN2 U435 ( .A(pi30), .B(pi37), .Z(n401)); - AN2 U436 ( .A(pi29), .B(n399), .Z(n400)); - OR2 U437 ( .A(n401), .B(n400), .Z(n402)); - OR2 U438 ( .A(n403), .B(n402), .Z(n404)); - OR2 U439 ( .A(n405), .B(n404), .Z(n579)); - AN2 U440 ( .A(pi21), .B(n579), .Z(n582)); - OR2 U441 ( .A(pi21), .B(n579), .Z(n584)); - AN2 U442 ( .A(n406), .B(pi55), .Z(n429)); - IV2 U443 ( .A(pi28), .Z(n409)); - AN2 U444 ( .A(n407), .B(pi20), .Z(n408)); - OR2 U445 ( .A(n409), .B(n408), .Z(n423)); - AN2 U446 ( .A(pi50), .B(n423), .Z(n411)); - AN2 U447 ( .A(pi42), .B(n424), .Z(n410)); - OR2 U448 ( .A(n411), .B(n410), .Z(n412)); - OR2 U449 ( .A(n429), .B(n412), .Z(n514)); - AN2 U450 ( .A(pi15), .B(n514), .Z(n517)); - OR2 U451 ( .A(pi15), .B(n514), .Z(n519)); - AN2 U452 ( .A(pi45), .B(n423), .Z(n414)); - AN2 U453 ( .A(pi40), .B(n424), .Z(n413)); - OR2 U454 ( .A(n414), .B(n413), .Z(n416)); - OR2 U455 ( .A(n429), .B(n416), .Z(n556)); - AN2 U456 ( .A(pi03), .B(n556), .Z(n559)); - OR2 U457 ( .A(pi03), .B(n556), .Z(n561)); - AN2 U458 ( .A(pi29), .B(n423), .Z(n418)); - AN2 U459 ( .A(pi04), .B(n424), .Z(n417)); - OR2 U460 ( .A(n418), .B(n417), .Z(n419)); - OR2 U461 ( .A(n429), .B(n419), .Z(n471)); - AN2 U462 ( .A(pi10), .B(n471), .Z(n480)); - OR2 U463 ( .A(pi10), .B(n471), .Z(n482)); - AN2 U464 ( .A(pi46), .B(n482), .Z(n420)); - OR2 U465 ( .A(n480), .B(n420), .Z(n562)); - AN2 U466 ( .A(n561), .B(n562), .Z(n421)); - OR2 U467 ( .A(n559), .B(n421), .Z(n520)); - AN2 U468 ( .A(n519), .B(n520), .Z(n422)); - OR2 U469 ( .A(n517), .B(n422), .Z(n449)); - AN2 U470 ( .A(pi44), .B(n423), .Z(n426)); - AN2 U471 ( .A(pi49), .B(n424), .Z(n425)); - OR2 U472 ( .A(n426), .B(n425), .Z(n428)); - OR2 U473 ( .A(n429), .B(n428), .Z(n464)); - AN2 U474 ( .A(n449), .B(n464), .Z(n432)); - OR2 U475 ( .A(n449), .B(n464), .Z(n430)); - AN2 U476 ( .A(pi09), .B(n430), .Z(n431)); - OR2 U477 ( .A(n432), .B(n431), .Z(n585)); - AN2 U478 ( .A(n584), .B(n585), .Z(n433)); - OR2 U479 ( .A(n582), .B(n433), .Z(n542)); - AN2 U480 ( .A(n541), .B(n542), .Z(n434)); - OR2 U481 ( .A(n539), .B(n434), .Z(n500)); - AN2 U482 ( .A(n499), .B(n500), .Z(n435)); - OR2 U483 ( .A(n497), .B(n435), .Z(n597)); - OR2 U484 ( .A(pi34), .B(n436), .Z(n598)); - AN2 U485 ( .A(n436), .B(pi34), .Z(n600)); - IV2 U486 ( .A(n600), .Z(n437)); - AN2 U487 ( .A(n598), .B(n437), .Z(n442)); - OR2 U488 ( .A(n597), .B(n442), .Z(n440)); - AN2 U489 ( .A(n597), .B(n442), .Z(n438)); - IV2 U490 ( .A(n438), .Z(n439)); - AN2 U491 ( .A(n440), .B(n439), .Z(n441)); - AN2 U492 ( .A(pi12), .B(n441), .Z(n444)); - AN2 U493 ( .A(n442), .B(pi19), .Z(n443)); - OR2 U494 ( .A(n444), .B(n443), .Z(n445)); - OR2 U495 ( .A(n446), .B(n445), .Z(n447)); - OR2 U496 ( .A(n448), .B(n447), .Z(n137)); - IV2 U497 ( .A(n464), .Z(n459)); - AN2 U498 ( .A(pi12), .B(n449), .Z(n456)); - AN2 U499 ( .A(n459), .B(n456), .Z(n453)); - IV2 U500 ( .A(n449), .Z(n450)); - AN2 U501 ( .A(n450), .B(pi12), .Z(n451)); - OR2 U502 ( .A(pi19), .B(n451), .Z(n458)); - AN2 U503 ( .A(n464), .B(n458), .Z(n452)); - OR2 U504 ( .A(n453), .B(n452), .Z(n455)); - IV2 U505 ( .A(pi09), .Z(n612)); - AN2 U506 ( .A(n455), .B(n612), .Z(n470)); - OR2 U507 ( .A(pi26), .B(n456), .Z(n457)); - AN2 U508 ( .A(n464), .B(n457), .Z(n462)); - AN2 U509 ( .A(n459), .B(n458), .Z(n460)); - OR2 U510 ( .A(n577), .B(n460), .Z(n461)); - OR2 U511 ( .A(n462), .B(n461), .Z(n463)); - AN2 U512 ( .A(pi09), .B(n463), .Z(n468)); - AN2 U513 ( .A(pi23), .B(pi05), .Z(n466)); - AN2 U514 ( .A(pi32), .B(n464), .Z(n465)); - OR2 U515 ( .A(n466), .B(n465), .Z(n467)); - OR2 U516 ( .A(n468), .B(n467), .Z(n469)); - OR2 U517 ( .A(n470), .B(n469), .Z(n295)); - AN2 U518 ( .A(pi26), .B(n480), .Z(n479)); - AN2 U519 ( .A(pi40), .B(pi05), .Z(n473)); - AN2 U520 ( .A(pi32), .B(n471), .Z(n472)); - OR2 U521 ( .A(n473), .B(n472), .Z(n477)); - AN2 U522 ( .A(pi38), .B(pi36), .Z(n475)); - AN2 U523 ( .A(pi10), .B(n577), .Z(n474)); - OR2 U524 ( .A(n475), .B(n474), .Z(n476)); - OR2 U525 ( .A(n477), .B(n476), .Z(n478)); - OR2 U526 ( .A(n479), .B(n478), .Z(n491)); - IV2 U527 ( .A(n480), .Z(n481)); - AN2 U528 ( .A(n482), .B(n481), .Z(n487)); - OR2 U529 ( .A(pi46), .B(n487), .Z(n485)); - AN2 U530 ( .A(pi46), .B(n487), .Z(n483)); - IV2 U531 ( .A(n483), .Z(n484)); - AN2 U532 ( .A(n485), .B(n484), .Z(n486)); - AN2 U533 ( .A(pi12), .B(n486), .Z(n489)); - AN2 U534 ( .A(n487), .B(pi19), .Z(n488)); - OR2 U535 ( .A(n489), .B(n488), .Z(n490)); - OR2 U536 ( .A(n491), .B(n490), .Z(n351)); - AN2 U537 ( .A(pi26), .B(n494), .Z(n492)); - OR2 U538 ( .A(n577), .B(n492), .Z(n493)); - AN2 U539 ( .A(pi27), .B(n493), .Z(n511)); - AN2 U540 ( .A(pi14), .B(pi05), .Z(n496)); - AN2 U541 ( .A(pi32), .B(n494), .Z(n495)); - OR2 U542 ( .A(n496), .B(n495), .Z(n509)); - IV2 U543 ( .A(n497), .Z(n498)); - AN2 U544 ( .A(n499), .B(n498), .Z(n505)); - OR2 U545 ( .A(n500), .B(n505), .Z(n503)); - AN2 U546 ( .A(n500), .B(n505), .Z(n501)); - IV2 U547 ( .A(n501), .Z(n502)); - AN2 U548 ( .A(n503), .B(n502), .Z(n504)); - AN2 U549 ( .A(pi12), .B(n504), .Z(n507)); - AN2 U550 ( .A(n505), .B(pi19), .Z(n506)); - OR2 U551 ( .A(n507), .B(n506), .Z(n508)); - OR2 U552 ( .A(n509), .B(n508), .Z(n510)); - OR2 U553 ( .A(n511), .B(n510), .Z(n364)); - AN2 U554 ( .A(pi26), .B(n514), .Z(n512)); - OR2 U555 ( .A(n577), .B(n512), .Z(n513)); - AN2 U556 ( .A(pi15), .B(n513), .Z(n533)); - AN2 U557 ( .A(pi49), .B(pi05), .Z(n531)); - AN2 U558 ( .A(pi33), .B(pi36), .Z(n516)); - AN2 U559 ( .A(pi32), .B(n514), .Z(n515)); - OR2 U560 ( .A(n516), .B(n515), .Z(n529)); - IV2 U561 ( .A(n517), .Z(n518)); - AN2 U562 ( .A(n519), .B(n518), .Z(n525)); - OR2 U563 ( .A(n520), .B(n525), .Z(n523)); - AN2 U564 ( .A(n520), .B(n525), .Z(n521)); - IV2 U565 ( .A(n521), .Z(n522)); - AN2 U566 ( .A(n523), .B(n522), .Z(n524)); - AN2 U567 ( .A(pi12), .B(n524), .Z(n527)); - AN2 U568 ( .A(n525), .B(pi19), .Z(n526)); - OR2 U569 ( .A(n527), .B(n526), .Z(n528)); - OR2 U570 ( .A(n529), .B(n528), .Z(n530)); - OR2 U571 ( .A(n531), .B(n530), .Z(n532)); - OR2 U572 ( .A(n533), .B(n532), .Z(n377)); - AN2 U573 ( .A(pi26), .B(n536), .Z(n534)); - OR2 U574 ( .A(n577), .B(n534), .Z(n535)); - AN2 U575 ( .A(pi17), .B(n535), .Z(n553)); - AN2 U576 ( .A(pi18), .B(pi05), .Z(n538)); - AN2 U577 ( .A(pi32), .B(n536), .Z(n537)); - OR2 U578 ( .A(n538), .B(n537), .Z(n551)); - IV2 U579 ( .A(n539), .Z(n540)); - AN2 U580 ( .A(n541), .B(n540), .Z(n547)); - OR2 U581 ( .A(n542), .B(n547), .Z(n545)); - AN2 U582 ( .A(n542), .B(n547), .Z(n543)); - IV2 U583 ( .A(n543), .Z(n544)); - AN2 U584 ( .A(n545), .B(n544), .Z(n546)); - AN2 U585 ( .A(pi12), .B(n546), .Z(n549)); - AN2 U586 ( .A(n547), .B(pi19), .Z(n548)); - OR2 U587 ( .A(n549), .B(n548), .Z(n550)); - OR2 U588 ( .A(n551), .B(n550), .Z(n552)); - OR2 U589 ( .A(n553), .B(n552), .Z(n415)); - AN2 U590 ( .A(pi26), .B(n556), .Z(n554)); - OR2 U591 ( .A(n577), .B(n554), .Z(n555)); - AN2 U592 ( .A(pi03), .B(n555), .Z(n575)); - AN2 U593 ( .A(pi42), .B(pi05), .Z(n573)); - AN2 U594 ( .A(pi47), .B(pi36), .Z(n558)); - AN2 U595 ( .A(pi32), .B(n556), .Z(n557)); - OR2 U596 ( .A(n558), .B(n557), .Z(n571)); - IV2 U597 ( .A(n559), .Z(n560)); - AN2 U598 ( .A(n561), .B(n560), .Z(n567)); - OR2 U599 ( .A(n562), .B(n567), .Z(n565)); - AN2 U600 ( .A(n562), .B(n567), .Z(n563)); - IV2 U601 ( .A(n563), .Z(n564)); - AN2 U602 ( .A(n565), .B(n564), .Z(n566)); - AN2 U603 ( .A(pi12), .B(n566), .Z(n569)); - AN2 U604 ( .A(n567), .B(pi19), .Z(n568)); - OR2 U605 ( .A(n569), .B(n568), .Z(n570)); - OR2 U606 ( .A(n571), .B(n570), .Z(n572)); - OR2 U607 ( .A(n573), .B(n572), .Z(n574)); - OR2 U608 ( .A(n575), .B(n574), .Z(n427)); - AN2 U609 ( .A(pi26), .B(n579), .Z(n576)); - OR2 U610 ( .A(n577), .B(n576), .Z(n578)); - AN2 U611 ( .A(pi21), .B(n578), .Z(n596)); - AN2 U612 ( .A(pi22), .B(pi05), .Z(n581)); - AN2 U613 ( .A(pi32), .B(n579), .Z(n580)); - OR2 U614 ( .A(n581), .B(n580), .Z(n594)); - IV2 U615 ( .A(n582), .Z(n583)); - AN2 U616 ( .A(n584), .B(n583), .Z(n590)); - OR2 U617 ( .A(n585), .B(n590), .Z(n588)); - AN2 U618 ( .A(n585), .B(n590), .Z(n586)); - IV2 U619 ( .A(n586), .Z(n587)); - AN2 U620 ( .A(n588), .B(n587), .Z(n589)); - AN2 U621 ( .A(pi12), .B(n589), .Z(n592)); - AN2 U622 ( .A(n590), .B(pi19), .Z(n591)); - OR2 U623 ( .A(n592), .B(n591), .Z(n593)); - OR2 U624 ( .A(n594), .B(n593), .Z(n595)); - OR2 U625 ( .A(n596), .B(n595), .Z(n454)); - AN2 U626 ( .A(n598), .B(n597), .Z(n599)); - OR2 U627 ( .A(n600), .B(n599), .Z(po07)); - OR2 U628 ( .A(pi58), .B(pi00), .Z(n609)); - AN2 U629 ( .A(pi59), .B(n609), .Z(po24)); - AN2 U630 ( .A(n602), .B(pi57), .Z(n601)); - AN2 U631 ( .A(pi41), .B(n601), .Z(po13)); - AN2 U632 ( .A(pi48), .B(n602), .Z(po08)); - AN2 U633 ( .A(n603), .B(pi31), .Z(po03)); - AN2 U634 ( .A(pi48), .B(pi16), .Z(n610)); - AN2 U635 ( .A(pi25), .B(n610), .Z(po25)); - AN2 U636 ( .A(pi11), .B(n604), .Z(n605)); - IV2 U637 ( .A(n605), .Z(n606)); - OR2 U638 ( .A(n607), .B(n606), .Z(n691)); - OR2 U639 ( .A(po25), .B(n691), .Z(po02)); - AN2 U640 ( .A(n608), .B(pi25), .Z(po10)); - AN2 U641 ( .A(pi13), .B(n609), .Z(po12)); - AN2 U642 ( .A(pi07), .B(n610), .Z(po14)); - IV2 U643 ( .A(pi15), .Z(n611)); - AN2 U644 ( .A(pi09), .B(n611), .Z(n614)); - AN2 U645 ( .A(pi15), .B(n612), .Z(n613)); - OR2 U646 ( .A(n614), .B(n613), .Z(n618)); - IV2 U647 ( .A(pi35), .Z(n654)); - OR2 U648 ( .A(n654), .B(pi06), .Z(n617)); - IV2 U649 ( .A(pi06), .Z(n615)); - OR2 U650 ( .A(n615), .B(pi35), .Z(n616)); - AN2 U651 ( .A(n617), .B(n616), .Z(n619)); - OR2 U652 ( .A(n618), .B(n619), .Z(n622)); - AN2 U653 ( .A(n619), .B(n618), .Z(n620)); - IV2 U654 ( .A(n620), .Z(n621)); - AN2 U655 ( .A(n622), .B(n621), .Z(n628)); - IV2 U656 ( .A(pi10), .Z(n624)); - OR2 U657 ( .A(n624), .B(pi03), .Z(n623)); - IV2 U658 ( .A(n623), .Z(n626)); - AN2 U659 ( .A(pi03), .B(n624), .Z(n625)); - OR2 U660 ( .A(n626), .B(n625), .Z(n627)); - OR2 U661 ( .A(n628), .B(n627), .Z(n631)); - AN2 U662 ( .A(n628), .B(n627), .Z(n629)); - IV2 U663 ( .A(n629), .Z(n630)); - AN2 U664 ( .A(n631), .B(n630), .Z(n637)); - IV2 U665 ( .A(pi34), .Z(n632)); - AN2 U666 ( .A(pi27), .B(n632), .Z(n635)); - OR2 U667 ( .A(n632), .B(pi27), .Z(n633)); - IV2 U668 ( .A(n633), .Z(n634)); - OR2 U669 ( .A(n635), .B(n634), .Z(n636)); - OR2 U670 ( .A(n637), .B(n636), .Z(n640)); - AN2 U671 ( .A(n637), .B(n636), .Z(n638)); - IV2 U672 ( .A(n638), .Z(n639)); - AN2 U673 ( .A(n640), .B(n639), .Z(n647)); - IV2 U674 ( .A(pi21), .Z(n642)); - OR2 U675 ( .A(n642), .B(pi17), .Z(n641)); - IV2 U676 ( .A(n641), .Z(n644)); - AN2 U677 ( .A(pi17), .B(n642), .Z(n643)); - OR2 U678 ( .A(n644), .B(n643), .Z(n646)); - OR2 U679 ( .A(n647), .B(n646), .Z(n645)); - IV2 U680 ( .A(n645), .Z(n649)); - AN2 U681 ( .A(n647), .B(n646), .Z(n648)); - OR2 U682 ( .A(n649), .B(n648), .Z(po15)); - IV2 U683 ( .A(pi42), .Z(n650)); - AN2 U684 ( .A(pi49), .B(n650), .Z(n653)); - IV2 U685 ( .A(pi49), .Z(n651)); - AN2 U686 ( .A(pi42), .B(n651), .Z(n652)); - OR2 U687 ( .A(n653), .B(n652), .Z(n658)); - OR2 U688 ( .A(n654), .B(pi39), .Z(n657)); - IV2 U689 ( .A(pi39), .Z(n655)); - OR2 U690 ( .A(n655), .B(pi35), .Z(n656)); - AN2 U691 ( .A(n657), .B(n656), .Z(n659)); - OR2 U692 ( .A(n658), .B(n659), .Z(n662)); - AN2 U693 ( .A(n659), .B(n658), .Z(n660)); - IV2 U694 ( .A(n660), .Z(n661)); - AN2 U695 ( .A(n662), .B(n661), .Z(n668)); - IV2 U696 ( .A(pi04), .Z(n664)); - OR2 U697 ( .A(n664), .B(pi18), .Z(n663)); - IV2 U698 ( .A(n663), .Z(n666)); - AN2 U699 ( .A(pi18), .B(n664), .Z(n665)); - OR2 U700 ( .A(n666), .B(n665), .Z(n667)); - OR2 U701 ( .A(n668), .B(n667), .Z(n671)); - AN2 U702 ( .A(n668), .B(n667), .Z(n669)); - IV2 U703 ( .A(n669), .Z(n670)); - AN2 U704 ( .A(n671), .B(n670), .Z(n677)); - IV2 U705 ( .A(pi22), .Z(n673)); - OR2 U706 ( .A(n673), .B(pi14), .Z(n672)); - IV2 U707 ( .A(n672), .Z(n675)); - AN2 U708 ( .A(pi14), .B(n673), .Z(n674)); - OR2 U709 ( .A(n675), .B(n674), .Z(n676)); - OR2 U710 ( .A(n677), .B(n676), .Z(n680)); - AN2 U711 ( .A(n677), .B(n676), .Z(n678)); - IV2 U712 ( .A(n678), .Z(n679)); - AN2 U713 ( .A(n680), .B(n679), .Z(n687)); - IV2 U714 ( .A(pi40), .Z(n682)); - OR2 U715 ( .A(n682), .B(pi23), .Z(n681)); - IV2 U716 ( .A(n681), .Z(n684)); - AN2 U717 ( .A(pi23), .B(n682), .Z(n683)); - OR2 U718 ( .A(n684), .B(n683), .Z(n686)); - OR2 U719 ( .A(n687), .B(n686), .Z(n685)); - IV2 U720 ( .A(n685), .Z(n689)); - AN2 U721 ( .A(n687), .B(n686), .Z(n688)); - OR2 U722 ( .A(n689), .B(n688), .Z(po20)); - AN2 U723 ( .A(pi01), .B(pi02), .Z(po21)); - IV2 U724 ( .A(po25), .Z(n690)); - OR2 U725 ( .A(n691), .B(n690), .Z(po23)); - IV2 U726 ( .A(pi16), .Z(n696)); - OR2 U727 ( .A(n692), .B(n696), .Z(po11)); - AN2 U728 ( .A(pi07), .B(pi41), .Z(n693)); - IV2 U729 ( .A(n693), .Z(n695)); - OR2 U730 ( .A(n694), .B(n695), .Z(po01)); - OR2 U731 ( .A(n696), .B(n695), .Z(po05)); - -endmodule - -module IV2(A, Z); - input A; - output Z; - - assign Z = ~A; -endmodule - -module AN2(A, B, Z); - input A, B; - output Z; - - assign Z = A & B; -endmodule - -module OR2(A, B, Z); - input A, B; - output Z; - - assign Z = A | B; -endmodule +module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, + pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59, + po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, + po20, po21, po22, po23, po24, po25); + +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, + pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59; + +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, + po20, po21, po22, po23, po24, po25; + +wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357, + n358, n359, n360, n361, n362, n363, n365, n366, n367, n368, + n369, n370, n371, n372, n373, n374, n375, n376, n378, n379, + n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, + n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n416, n417, n418, n419, n420, + n421, n422, n423, n424, n425, n426, n428, n429, n430, n431, + n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, + n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, + n452, n453, n455, n456, n457, n458, n459, n460, n461, n462, + n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, + n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, + n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, + n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, + n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, + n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, + n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, + n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, + n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, + n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, + n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, + n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, + n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, + n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, + n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, + n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, + n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, + n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, + n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, + n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, + n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, + n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, + n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, + n693, n694, n695, n696; + + +assign po22 = n137; +assign po19 = n346; +assign po16 = n364; +assign po17 = n415; +assign po18 = n295; +assign po00 = n427; +assign po09 = n351; +assign po04 = n377; +assign po06 = n454; + AN2 U371 ( .A(pi11), .B(pi08), .Z(n357)); + AN2 U372 ( .A(pi28), .B(n357), .Z(n346)); + AN2 U373 ( .A(pi41), .B(pi25), .Z(n369)); + AN2 U374 ( .A(pi52), .B(n369), .Z(n361)); + AN2 U375 ( .A(pi51), .B(pi54), .Z(n359)); + AN2 U376 ( .A(pi28), .B(pi31), .Z(n604)); + AN2 U377 ( .A(n604), .B(pi55), .Z(n358)); + AN2 U378 ( .A(n359), .B(n358), .Z(n602)); + AN2 U379 ( .A(pi53), .B(n602), .Z(n360)); + AN2 U380 ( .A(n361), .B(n360), .Z(n577)); + IV2 U381 ( .A(pi20), .Z(n607)); + OR2 U382 ( .A(n607), .B(pi25), .Z(n362)); + IV2 U383 ( .A(n362), .Z(n365)); + AN2 U384 ( .A(pi25), .B(n607), .Z(n363)); + OR2 U385 ( .A(n365), .B(n363), .Z(n367)); + AN2 U386 ( .A(pi41), .B(pi24), .Z(n378)); + AN2 U387 ( .A(n346), .B(n378), .Z(n366)); + AN2 U388 ( .A(n367), .B(n366), .Z(n373)); + AN2 U389 ( .A(pi28), .B(pi54), .Z(n368)); + AN2 U390 ( .A(pi20), .B(n368), .Z(n603)); + AN2 U391 ( .A(pi08), .B(n603), .Z(n371)); + IV2 U392 ( .A(pi56), .Z(n694)); + IV2 U393 ( .A(n369), .Z(n692)); + OR2 U394 ( .A(n694), .B(n692), .Z(n370)); + AN2 U395 ( .A(n371), .B(n370), .Z(n372)); + OR2 U396 ( .A(n373), .B(n372), .Z(n424)); + AN2 U397 ( .A(pi14), .B(n424), .Z(n384)); + AN2 U398 ( .A(pi56), .B(pi48), .Z(n608)); + AN2 U399 ( .A(n608), .B(n346), .Z(n374)); + AN2 U400 ( .A(pi07), .B(n374), .Z(n376)); + IV2 U401 ( .A(pi43), .Z(n375)); + AN2 U402 ( .A(n376), .B(n375), .Z(n406)); + AN2 U403 ( .A(pi20), .B(n406), .Z(n403)); + IV2 U404 ( .A(n378), .Z(n379)); + AN2 U405 ( .A(n346), .B(n379), .Z(n407)); + AN2 U406 ( .A(pi55), .B(n407), .Z(n399)); + AN2 U407 ( .A(pi44), .B(n399), .Z(n381)); + AN2 U408 ( .A(pi37), .B(pi54), .Z(n380)); + OR2 U409 ( .A(n381), .B(n380), .Z(n382)); + OR2 U410 ( .A(n403), .B(n382), .Z(n383)); + OR2 U411 ( .A(n384), .B(n383), .Z(n436)); + AN2 U412 ( .A(pi26), .B(n436), .Z(n385)); + OR2 U413 ( .A(n577), .B(n385), .Z(n386)); + AN2 U414 ( .A(pi34), .B(n386), .Z(n448)); + AN2 U415 ( .A(pi43), .B(pi05), .Z(n388)); + AN2 U416 ( .A(pi32), .B(n436), .Z(n387)); + OR2 U417 ( .A(n388), .B(n387), .Z(n446)); + AN2 U418 ( .A(pi08), .B(pi37), .Z(n393)); + AN2 U419 ( .A(pi50), .B(n399), .Z(n390)); + AN2 U420 ( .A(pi18), .B(n424), .Z(n389)); + OR2 U421 ( .A(n390), .B(n389), .Z(n391)); + OR2 U422 ( .A(n403), .B(n391), .Z(n392)); + OR2 U423 ( .A(n393), .B(n392), .Z(n494)); + AN2 U424 ( .A(pi27), .B(n494), .Z(n497)); + OR2 U425 ( .A(pi27), .B(n494), .Z(n499)); + AN2 U426 ( .A(pi20), .B(pi37), .Z(n398)); + AN2 U427 ( .A(pi45), .B(n399), .Z(n395)); + AN2 U428 ( .A(pi22), .B(n424), .Z(n394)); + OR2 U429 ( .A(n395), .B(n394), .Z(n396)); + OR2 U430 ( .A(n403), .B(n396), .Z(n397)); + OR2 U431 ( .A(n398), .B(n397), .Z(n536)); + AN2 U432 ( .A(pi17), .B(n536), .Z(n539)); + OR2 U433 ( .A(pi17), .B(n536), .Z(n541)); + AN2 U434 ( .A(pi23), .B(n424), .Z(n405)); + AN2 U435 ( .A(pi30), .B(pi37), .Z(n401)); + AN2 U436 ( .A(pi29), .B(n399), .Z(n400)); + OR2 U437 ( .A(n401), .B(n400), .Z(n402)); + OR2 U438 ( .A(n403), .B(n402), .Z(n404)); + OR2 U439 ( .A(n405), .B(n404), .Z(n579)); + AN2 U440 ( .A(pi21), .B(n579), .Z(n582)); + OR2 U441 ( .A(pi21), .B(n579), .Z(n584)); + AN2 U442 ( .A(n406), .B(pi55), .Z(n429)); + IV2 U443 ( .A(pi28), .Z(n409)); + AN2 U444 ( .A(n407), .B(pi20), .Z(n408)); + OR2 U445 ( .A(n409), .B(n408), .Z(n423)); + AN2 U446 ( .A(pi50), .B(n423), .Z(n411)); + AN2 U447 ( .A(pi42), .B(n424), .Z(n410)); + OR2 U448 ( .A(n411), .B(n410), .Z(n412)); + OR2 U449 ( .A(n429), .B(n412), .Z(n514)); + AN2 U450 ( .A(pi15), .B(n514), .Z(n517)); + OR2 U451 ( .A(pi15), .B(n514), .Z(n519)); + AN2 U452 ( .A(pi45), .B(n423), .Z(n414)); + AN2 U453 ( .A(pi40), .B(n424), .Z(n413)); + OR2 U454 ( .A(n414), .B(n413), .Z(n416)); + OR2 U455 ( .A(n429), .B(n416), .Z(n556)); + AN2 U456 ( .A(pi03), .B(n556), .Z(n559)); + OR2 U457 ( .A(pi03), .B(n556), .Z(n561)); + AN2 U458 ( .A(pi29), .B(n423), .Z(n418)); + AN2 U459 ( .A(pi04), .B(n424), .Z(n417)); + OR2 U460 ( .A(n418), .B(n417), .Z(n419)); + OR2 U461 ( .A(n429), .B(n419), .Z(n471)); + AN2 U462 ( .A(pi10), .B(n471), .Z(n480)); + OR2 U463 ( .A(pi10), .B(n471), .Z(n482)); + AN2 U464 ( .A(pi46), .B(n482), .Z(n420)); + OR2 U465 ( .A(n480), .B(n420), .Z(n562)); + AN2 U466 ( .A(n561), .B(n562), .Z(n421)); + OR2 U467 ( .A(n559), .B(n421), .Z(n520)); + AN2 U468 ( .A(n519), .B(n520), .Z(n422)); + OR2 U469 ( .A(n517), .B(n422), .Z(n449)); + AN2 U470 ( .A(pi44), .B(n423), .Z(n426)); + AN2 U471 ( .A(pi49), .B(n424), .Z(n425)); + OR2 U472 ( .A(n426), .B(n425), .Z(n428)); + OR2 U473 ( .A(n429), .B(n428), .Z(n464)); + AN2 U474 ( .A(n449), .B(n464), .Z(n432)); + OR2 U475 ( .A(n449), .B(n464), .Z(n430)); + AN2 U476 ( .A(pi09), .B(n430), .Z(n431)); + OR2 U477 ( .A(n432), .B(n431), .Z(n585)); + AN2 U478 ( .A(n584), .B(n585), .Z(n433)); + OR2 U479 ( .A(n582), .B(n433), .Z(n542)); + AN2 U480 ( .A(n541), .B(n542), .Z(n434)); + OR2 U481 ( .A(n539), .B(n434), .Z(n500)); + AN2 U482 ( .A(n499), .B(n500), .Z(n435)); + OR2 U483 ( .A(n497), .B(n435), .Z(n597)); + OR2 U484 ( .A(pi34), .B(n436), .Z(n598)); + AN2 U485 ( .A(n436), .B(pi34), .Z(n600)); + IV2 U486 ( .A(n600), .Z(n437)); + AN2 U487 ( .A(n598), .B(n437), .Z(n442)); + OR2 U488 ( .A(n597), .B(n442), .Z(n440)); + AN2 U489 ( .A(n597), .B(n442), .Z(n438)); + IV2 U490 ( .A(n438), .Z(n439)); + AN2 U491 ( .A(n440), .B(n439), .Z(n441)); + AN2 U492 ( .A(pi12), .B(n441), .Z(n444)); + AN2 U493 ( .A(n442), .B(pi19), .Z(n443)); + OR2 U494 ( .A(n444), .B(n443), .Z(n445)); + OR2 U495 ( .A(n446), .B(n445), .Z(n447)); + OR2 U496 ( .A(n448), .B(n447), .Z(n137)); + IV2 U497 ( .A(n464), .Z(n459)); + AN2 U498 ( .A(pi12), .B(n449), .Z(n456)); + AN2 U499 ( .A(n459), .B(n456), .Z(n453)); + IV2 U500 ( .A(n449), .Z(n450)); + AN2 U501 ( .A(n450), .B(pi12), .Z(n451)); + OR2 U502 ( .A(pi19), .B(n451), .Z(n458)); + AN2 U503 ( .A(n464), .B(n458), .Z(n452)); + OR2 U504 ( .A(n453), .B(n452), .Z(n455)); + IV2 U505 ( .A(pi09), .Z(n612)); + AN2 U506 ( .A(n455), .B(n612), .Z(n470)); + OR2 U507 ( .A(pi26), .B(n456), .Z(n457)); + AN2 U508 ( .A(n464), .B(n457), .Z(n462)); + AN2 U509 ( .A(n459), .B(n458), .Z(n460)); + OR2 U510 ( .A(n577), .B(n460), .Z(n461)); + OR2 U511 ( .A(n462), .B(n461), .Z(n463)); + AN2 U512 ( .A(pi09), .B(n463), .Z(n468)); + AN2 U513 ( .A(pi23), .B(pi05), .Z(n466)); + AN2 U514 ( .A(pi32), .B(n464), .Z(n465)); + OR2 U515 ( .A(n466), .B(n465), .Z(n467)); + OR2 U516 ( .A(n468), .B(n467), .Z(n469)); + OR2 U517 ( .A(n470), .B(n469), .Z(n295)); + AN2 U518 ( .A(pi26), .B(n480), .Z(n479)); + AN2 U519 ( .A(pi40), .B(pi05), .Z(n473)); + AN2 U520 ( .A(pi32), .B(n471), .Z(n472)); + OR2 U521 ( .A(n473), .B(n472), .Z(n477)); + AN2 U522 ( .A(pi38), .B(pi36), .Z(n475)); + AN2 U523 ( .A(pi10), .B(n577), .Z(n474)); + OR2 U524 ( .A(n475), .B(n474), .Z(n476)); + OR2 U525 ( .A(n477), .B(n476), .Z(n478)); + OR2 U526 ( .A(n479), .B(n478), .Z(n491)); + IV2 U527 ( .A(n480), .Z(n481)); + AN2 U528 ( .A(n482), .B(n481), .Z(n487)); + OR2 U529 ( .A(pi46), .B(n487), .Z(n485)); + AN2 U530 ( .A(pi46), .B(n487), .Z(n483)); + IV2 U531 ( .A(n483), .Z(n484)); + AN2 U532 ( .A(n485), .B(n484), .Z(n486)); + AN2 U533 ( .A(pi12), .B(n486), .Z(n489)); + AN2 U534 ( .A(n487), .B(pi19), .Z(n488)); + OR2 U535 ( .A(n489), .B(n488), .Z(n490)); + OR2 U536 ( .A(n491), .B(n490), .Z(n351)); + AN2 U537 ( .A(pi26), .B(n494), .Z(n492)); + OR2 U538 ( .A(n577), .B(n492), .Z(n493)); + AN2 U539 ( .A(pi27), .B(n493), .Z(n511)); + AN2 U540 ( .A(pi14), .B(pi05), .Z(n496)); + AN2 U541 ( .A(pi32), .B(n494), .Z(n495)); + OR2 U542 ( .A(n496), .B(n495), .Z(n509)); + IV2 U543 ( .A(n497), .Z(n498)); + AN2 U544 ( .A(n499), .B(n498), .Z(n505)); + OR2 U545 ( .A(n500), .B(n505), .Z(n503)); + AN2 U546 ( .A(n500), .B(n505), .Z(n501)); + IV2 U547 ( .A(n501), .Z(n502)); + AN2 U548 ( .A(n503), .B(n502), .Z(n504)); + AN2 U549 ( .A(pi12), .B(n504), .Z(n507)); + AN2 U550 ( .A(n505), .B(pi19), .Z(n506)); + OR2 U551 ( .A(n507), .B(n506), .Z(n508)); + OR2 U552 ( .A(n509), .B(n508), .Z(n510)); + OR2 U553 ( .A(n511), .B(n510), .Z(n364)); + AN2 U554 ( .A(pi26), .B(n514), .Z(n512)); + OR2 U555 ( .A(n577), .B(n512), .Z(n513)); + AN2 U556 ( .A(pi15), .B(n513), .Z(n533)); + AN2 U557 ( .A(pi49), .B(pi05), .Z(n531)); + AN2 U558 ( .A(pi33), .B(pi36), .Z(n516)); + AN2 U559 ( .A(pi32), .B(n514), .Z(n515)); + OR2 U560 ( .A(n516), .B(n515), .Z(n529)); + IV2 U561 ( .A(n517), .Z(n518)); + AN2 U562 ( .A(n519), .B(n518), .Z(n525)); + OR2 U563 ( .A(n520), .B(n525), .Z(n523)); + AN2 U564 ( .A(n520), .B(n525), .Z(n521)); + IV2 U565 ( .A(n521), .Z(n522)); + AN2 U566 ( .A(n523), .B(n522), .Z(n524)); + AN2 U567 ( .A(pi12), .B(n524), .Z(n527)); + AN2 U568 ( .A(n525), .B(pi19), .Z(n526)); + OR2 U569 ( .A(n527), .B(n526), .Z(n528)); + OR2 U570 ( .A(n529), .B(n528), .Z(n530)); + OR2 U571 ( .A(n531), .B(n530), .Z(n532)); + OR2 U572 ( .A(n533), .B(n532), .Z(n377)); + AN2 U573 ( .A(pi26), .B(n536), .Z(n534)); + OR2 U574 ( .A(n577), .B(n534), .Z(n535)); + AN2 U575 ( .A(pi17), .B(n535), .Z(n553)); + AN2 U576 ( .A(pi18), .B(pi05), .Z(n538)); + AN2 U577 ( .A(pi32), .B(n536), .Z(n537)); + OR2 U578 ( .A(n538), .B(n537), .Z(n551)); + IV2 U579 ( .A(n539), .Z(n540)); + AN2 U580 ( .A(n541), .B(n540), .Z(n547)); + OR2 U581 ( .A(n542), .B(n547), .Z(n545)); + AN2 U582 ( .A(n542), .B(n547), .Z(n543)); + IV2 U583 ( .A(n543), .Z(n544)); + AN2 U584 ( .A(n545), .B(n544), .Z(n546)); + AN2 U585 ( .A(pi12), .B(n546), .Z(n549)); + AN2 U586 ( .A(n547), .B(pi19), .Z(n548)); + OR2 U587 ( .A(n549), .B(n548), .Z(n550)); + OR2 U588 ( .A(n551), .B(n550), .Z(n552)); + OR2 U589 ( .A(n553), .B(n552), .Z(n415)); + AN2 U590 ( .A(pi26), .B(n556), .Z(n554)); + OR2 U591 ( .A(n577), .B(n554), .Z(n555)); + AN2 U592 ( .A(pi03), .B(n555), .Z(n575)); + AN2 U593 ( .A(pi42), .B(pi05), .Z(n573)); + AN2 U594 ( .A(pi47), .B(pi36), .Z(n558)); + AN2 U595 ( .A(pi32), .B(n556), .Z(n557)); + OR2 U596 ( .A(n558), .B(n557), .Z(n571)); + IV2 U597 ( .A(n559), .Z(n560)); + AN2 U598 ( .A(n561), .B(n560), .Z(n567)); + OR2 U599 ( .A(n562), .B(n567), .Z(n565)); + AN2 U600 ( .A(n562), .B(n567), .Z(n563)); + IV2 U601 ( .A(n563), .Z(n564)); + AN2 U602 ( .A(n565), .B(n564), .Z(n566)); + AN2 U603 ( .A(pi12), .B(n566), .Z(n569)); + AN2 U604 ( .A(n567), .B(pi19), .Z(n568)); + OR2 U605 ( .A(n569), .B(n568), .Z(n570)); + OR2 U606 ( .A(n571), .B(n570), .Z(n572)); + OR2 U607 ( .A(n573), .B(n572), .Z(n574)); + OR2 U608 ( .A(n575), .B(n574), .Z(n427)); + AN2 U609 ( .A(pi26), .B(n579), .Z(n576)); + OR2 U610 ( .A(n577), .B(n576), .Z(n578)); + AN2 U611 ( .A(pi21), .B(n578), .Z(n596)); + AN2 U612 ( .A(pi22), .B(pi05), .Z(n581)); + AN2 U613 ( .A(pi32), .B(n579), .Z(n580)); + OR2 U614 ( .A(n581), .B(n580), .Z(n594)); + IV2 U615 ( .A(n582), .Z(n583)); + AN2 U616 ( .A(n584), .B(n583), .Z(n590)); + OR2 U617 ( .A(n585), .B(n590), .Z(n588)); + AN2 U618 ( .A(n585), .B(n590), .Z(n586)); + IV2 U619 ( .A(n586), .Z(n587)); + AN2 U620 ( .A(n588), .B(n587), .Z(n589)); + AN2 U621 ( .A(pi12), .B(n589), .Z(n592)); + AN2 U622 ( .A(n590), .B(pi19), .Z(n591)); + OR2 U623 ( .A(n592), .B(n591), .Z(n593)); + OR2 U624 ( .A(n594), .B(n593), .Z(n595)); + OR2 U625 ( .A(n596), .B(n595), .Z(n454)); + AN2 U626 ( .A(n598), .B(n597), .Z(n599)); + OR2 U627 ( .A(n600), .B(n599), .Z(po07)); + OR2 U628 ( .A(pi58), .B(pi00), .Z(n609)); + AN2 U629 ( .A(pi59), .B(n609), .Z(po24)); + AN2 U630 ( .A(n602), .B(pi57), .Z(n601)); + AN2 U631 ( .A(pi41), .B(n601), .Z(po13)); + AN2 U632 ( .A(pi48), .B(n602), .Z(po08)); + AN2 U633 ( .A(n603), .B(pi31), .Z(po03)); + AN2 U634 ( .A(pi48), .B(pi16), .Z(n610)); + AN2 U635 ( .A(pi25), .B(n610), .Z(po25)); + AN2 U636 ( .A(pi11), .B(n604), .Z(n605)); + IV2 U637 ( .A(n605), .Z(n606)); + OR2 U638 ( .A(n607), .B(n606), .Z(n691)); + OR2 U639 ( .A(po25), .B(n691), .Z(po02)); + AN2 U640 ( .A(n608), .B(pi25), .Z(po10)); + AN2 U641 ( .A(pi13), .B(n609), .Z(po12)); + AN2 U642 ( .A(pi07), .B(n610), .Z(po14)); + IV2 U643 ( .A(pi15), .Z(n611)); + AN2 U644 ( .A(pi09), .B(n611), .Z(n614)); + AN2 U645 ( .A(pi15), .B(n612), .Z(n613)); + OR2 U646 ( .A(n614), .B(n613), .Z(n618)); + IV2 U647 ( .A(pi35), .Z(n654)); + OR2 U648 ( .A(n654), .B(pi06), .Z(n617)); + IV2 U649 ( .A(pi06), .Z(n615)); + OR2 U650 ( .A(n615), .B(pi35), .Z(n616)); + AN2 U651 ( .A(n617), .B(n616), .Z(n619)); + OR2 U652 ( .A(n618), .B(n619), .Z(n622)); + AN2 U653 ( .A(n619), .B(n618), .Z(n620)); + IV2 U654 ( .A(n620), .Z(n621)); + AN2 U655 ( .A(n622), .B(n621), .Z(n628)); + IV2 U656 ( .A(pi10), .Z(n624)); + OR2 U657 ( .A(n624), .B(pi03), .Z(n623)); + IV2 U658 ( .A(n623), .Z(n626)); + AN2 U659 ( .A(pi03), .B(n624), .Z(n625)); + OR2 U660 ( .A(n626), .B(n625), .Z(n627)); + OR2 U661 ( .A(n628), .B(n627), .Z(n631)); + AN2 U662 ( .A(n628), .B(n627), .Z(n629)); + IV2 U663 ( .A(n629), .Z(n630)); + AN2 U664 ( .A(n631), .B(n630), .Z(n637)); + IV2 U665 ( .A(pi34), .Z(n632)); + AN2 U666 ( .A(pi27), .B(n632), .Z(n635)); + OR2 U667 ( .A(n632), .B(pi27), .Z(n633)); + IV2 U668 ( .A(n633), .Z(n634)); + OR2 U669 ( .A(n635), .B(n634), .Z(n636)); + OR2 U670 ( .A(n637), .B(n636), .Z(n640)); + AN2 U671 ( .A(n637), .B(n636), .Z(n638)); + IV2 U672 ( .A(n638), .Z(n639)); + AN2 U673 ( .A(n640), .B(n639), .Z(n647)); + IV2 U674 ( .A(pi21), .Z(n642)); + OR2 U675 ( .A(n642), .B(pi17), .Z(n641)); + IV2 U676 ( .A(n641), .Z(n644)); + AN2 U677 ( .A(pi17), .B(n642), .Z(n643)); + OR2 U678 ( .A(n644), .B(n643), .Z(n646)); + OR2 U679 ( .A(n647), .B(n646), .Z(n645)); + IV2 U680 ( .A(n645), .Z(n649)); + AN2 U681 ( .A(n647), .B(n646), .Z(n648)); + OR2 U682 ( .A(n649), .B(n648), .Z(po15)); + IV2 U683 ( .A(pi42), .Z(n650)); + AN2 U684 ( .A(pi49), .B(n650), .Z(n653)); + IV2 U685 ( .A(pi49), .Z(n651)); + AN2 U686 ( .A(pi42), .B(n651), .Z(n652)); + OR2 U687 ( .A(n653), .B(n652), .Z(n658)); + OR2 U688 ( .A(n654), .B(pi39), .Z(n657)); + IV2 U689 ( .A(pi39), .Z(n655)); + OR2 U690 ( .A(n655), .B(pi35), .Z(n656)); + AN2 U691 ( .A(n657), .B(n656), .Z(n659)); + OR2 U692 ( .A(n658), .B(n659), .Z(n662)); + AN2 U693 ( .A(n659), .B(n658), .Z(n660)); + IV2 U694 ( .A(n660), .Z(n661)); + AN2 U695 ( .A(n662), .B(n661), .Z(n668)); + IV2 U696 ( .A(pi04), .Z(n664)); + OR2 U697 ( .A(n664), .B(pi18), .Z(n663)); + IV2 U698 ( .A(n663), .Z(n666)); + AN2 U699 ( .A(pi18), .B(n664), .Z(n665)); + OR2 U700 ( .A(n666), .B(n665), .Z(n667)); + OR2 U701 ( .A(n668), .B(n667), .Z(n671)); + AN2 U702 ( .A(n668), .B(n667), .Z(n669)); + IV2 U703 ( .A(n669), .Z(n670)); + AN2 U704 ( .A(n671), .B(n670), .Z(n677)); + IV2 U705 ( .A(pi22), .Z(n673)); + OR2 U706 ( .A(n673), .B(pi14), .Z(n672)); + IV2 U707 ( .A(n672), .Z(n675)); + AN2 U708 ( .A(pi14), .B(n673), .Z(n674)); + OR2 U709 ( .A(n675), .B(n674), .Z(n676)); + OR2 U710 ( .A(n677), .B(n676), .Z(n680)); + AN2 U711 ( .A(n677), .B(n676), .Z(n678)); + IV2 U712 ( .A(n678), .Z(n679)); + AN2 U713 ( .A(n680), .B(n679), .Z(n687)); + IV2 U714 ( .A(pi40), .Z(n682)); + OR2 U715 ( .A(n682), .B(pi23), .Z(n681)); + IV2 U716 ( .A(n681), .Z(n684)); + AN2 U717 ( .A(pi23), .B(n682), .Z(n683)); + OR2 U718 ( .A(n684), .B(n683), .Z(n686)); + OR2 U719 ( .A(n687), .B(n686), .Z(n685)); + IV2 U720 ( .A(n685), .Z(n689)); + AN2 U721 ( .A(n687), .B(n686), .Z(n688)); + OR2 U722 ( .A(n689), .B(n688), .Z(po20)); + AN2 U723 ( .A(pi01), .B(pi02), .Z(po21)); + IV2 U724 ( .A(po25), .Z(n690)); + OR2 U725 ( .A(n691), .B(n690), .Z(po23)); + IV2 U726 ( .A(pi16), .Z(n696)); + OR2 U727 ( .A(n692), .B(n696), .Z(po11)); + AN2 U728 ( .A(pi07), .B(pi41), .Z(n693)); + IV2 U729 ( .A(n693), .Z(n695)); + OR2 U730 ( .A(n694), .B(n695), .Z(po01)); + OR2 U731 ( .A(n696), .B(n695), .Z(po05)); + +endmodule + +module IV2(A, Z); + input A; + output Z; + + assign Z = ~A; +endmodule + +module AN2(A, B, Z); + input A, B; + output Z; + + assign Z = A & B; +endmodule + +module OR2(A, B, Z); + input A, B; + output Z; + + assign Z = A | B; +endmodule diff --git a/techlibs/gatemate/arith_map.v b/techlibs/gatemate/arith_map.v index a3ab9c186..4d7e6c37a 100644 --- a/techlibs/gatemate/arith_map.v +++ b/techlibs/gatemate/arith_map.v @@ -1,69 +1,69 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -(* techmap_celltype = "$alu" *) -module _80_gatemate_alu(A, B, CI, BI, X, Y, CO); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; - - (* force_downto *) - input [A_WIDTH-1:0] A; - (* force_downto *) - input [B_WIDTH-1:0] B; - (* force_downto *) - output [Y_WIDTH-1:0] X, Y; - - input CI, BI; - (* force_downto *) - output [Y_WIDTH-1:0] CO; - - wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; - - (* force_downto *) - wire [Y_WIDTH-1:0] A_buf, B_buf; - \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); - \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - - (* force_downto *) - wire [Y_WIDTH-1:0] AA = A_buf; - (* force_downto *) - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; - (* force_downto *) - wire [Y_WIDTH-1:0] C = {CO, CI}; - - genvar i; - generate - for (i = 0; i < Y_WIDTH; i = i + 1) - begin: slice - CC_ADDF addf_i ( - .A(AA[i]), - .B(BB[i]), - .CI(C[i]), - .CO(CO[i]), - .S(Y[i]) - ); - end - endgenerate - - assign X = AA ^ BB; - -endmodule +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_gatemate_alu(A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] C = {CO, CI}; + + genvar i; + generate + for (i = 0; i < Y_WIDTH; i = i + 1) + begin: slice + CC_ADDF addf_i ( + .A(AA[i]), + .B(BB[i]), + .CI(C[i]), + .CO(CO[i]), + .S(Y[i]) + ); + end + endgenerate + + assign X = AA ^ BB; + +endmodule diff --git a/techlibs/gatemate/brams_map.v b/techlibs/gatemate/brams_map.v index 0b039db35..01c6b5db7 100644 --- a/techlibs/gatemate/brams_map.v +++ b/techlibs/gatemate/brams_map.v @@ -1,882 +1,882 @@ -module $__CC_BRAM_TDP_(...); - -parameter INIT = 0; -parameter OPTION_MODE = "20K"; - -parameter PORT_A_CLK_POL = 1; -parameter PORT_A_RD_USED = 1; -parameter PORT_A_WR_USED = 1; -parameter PORT_A_RD_WIDTH = 1; -parameter PORT_A_WR_WIDTH = 1; -parameter PORT_A_WR_BE_WIDTH = 1; -parameter PORT_A_OPTION_WR_MODE = "NO_CHANGE"; - -parameter PORT_B_CLK_POL = 1; -parameter PORT_B_RD_USED = 1; -parameter PORT_B_WR_USED = 1; -parameter PORT_B_RD_WIDTH = 1; -parameter PORT_B_WR_WIDTH = 1; -parameter PORT_B_WR_BE_WIDTH = 1; -parameter PORT_B_OPTION_WR_MODE = "NO_CHANGE"; - -input PORT_A_CLK; -input PORT_A_CLK_EN; -input PORT_A_WR_EN; -input [15:0] PORT_A_ADDR; -input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; -input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA; -output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA; - -input PORT_B_CLK; -input PORT_B_CLK_EN; -input PORT_B_WR_EN; -input [15:0] PORT_B_ADDR; -input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; -input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA; -output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA; - -generate - if (OPTION_MODE == "20K") begin - CC_BRAM_20K #( - .INIT_00(INIT['h00*320+:320]), - .INIT_01(INIT['h01*320+:320]), - .INIT_02(INIT['h02*320+:320]), - .INIT_03(INIT['h03*320+:320]), - .INIT_04(INIT['h04*320+:320]), - .INIT_05(INIT['h05*320+:320]), - .INIT_06(INIT['h06*320+:320]), - .INIT_07(INIT['h07*320+:320]), - .INIT_08(INIT['h08*320+:320]), - .INIT_09(INIT['h09*320+:320]), - .INIT_0A(INIT['h0a*320+:320]), - .INIT_0B(INIT['h0b*320+:320]), - .INIT_0C(INIT['h0c*320+:320]), - .INIT_0D(INIT['h0d*320+:320]), - .INIT_0E(INIT['h0e*320+:320]), - .INIT_0F(INIT['h0f*320+:320]), - .INIT_10(INIT['h10*320+:320]), - .INIT_11(INIT['h11*320+:320]), - .INIT_12(INIT['h12*320+:320]), - .INIT_13(INIT['h13*320+:320]), - .INIT_14(INIT['h14*320+:320]), - .INIT_15(INIT['h15*320+:320]), - .INIT_16(INIT['h16*320+:320]), - .INIT_17(INIT['h17*320+:320]), - .INIT_18(INIT['h18*320+:320]), - .INIT_19(INIT['h19*320+:320]), - .INIT_1A(INIT['h1a*320+:320]), - .INIT_1B(INIT['h1b*320+:320]), - .INIT_1C(INIT['h1c*320+:320]), - .INIT_1D(INIT['h1d*320+:320]), - .INIT_1E(INIT['h1e*320+:320]), - .INIT_1F(INIT['h1f*320+:320]), - .INIT_20(INIT['h20*320+:320]), - .INIT_21(INIT['h21*320+:320]), - .INIT_22(INIT['h22*320+:320]), - .INIT_23(INIT['h23*320+:320]), - .INIT_24(INIT['h24*320+:320]), - .INIT_25(INIT['h25*320+:320]), - .INIT_26(INIT['h26*320+:320]), - .INIT_27(INIT['h27*320+:320]), - .INIT_28(INIT['h28*320+:320]), - .INIT_29(INIT['h29*320+:320]), - .INIT_2A(INIT['h2a*320+:320]), - .INIT_2B(INIT['h2b*320+:320]), - .INIT_2C(INIT['h2c*320+:320]), - .INIT_2D(INIT['h2d*320+:320]), - .INIT_2E(INIT['h2e*320+:320]), - .INIT_2F(INIT['h2f*320+:320]), - .INIT_30(INIT['h30*320+:320]), - .INIT_31(INIT['h31*320+:320]), - .INIT_32(INIT['h32*320+:320]), - .INIT_33(INIT['h33*320+:320]), - .INIT_34(INIT['h34*320+:320]), - .INIT_35(INIT['h35*320+:320]), - .INIT_36(INIT['h36*320+:320]), - .INIT_37(INIT['h37*320+:320]), - .INIT_38(INIT['h38*320+:320]), - .INIT_39(INIT['h39*320+:320]), - .INIT_3A(INIT['h3a*320+:320]), - .INIT_3B(INIT['h3b*320+:320]), - .INIT_3C(INIT['h3c*320+:320]), - .INIT_3D(INIT['h3d*320+:320]), - .INIT_3E(INIT['h3e*320+:320]), - .INIT_3F(INIT['h3f*320+:320]), - .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), - .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), - .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), - .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), - .RAM_MODE("TDP"), - .A_WR_MODE(PORT_A_OPTION_WR_MODE), - .B_WR_MODE(PORT_B_OPTION_WR_MODE), - .A_CLK_INV(!PORT_A_CLK_POL), - .B_CLK_INV(!PORT_B_CLK_POL), - ) _TECHMAP_REPLACE_ ( - .A_CLK(PORT_A_CLK), - .A_EN(PORT_A_CLK_EN), - .A_WE(PORT_A_WR_EN), - .A_BM({{(20-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), - .A_DI({{(20-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), - .A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}), - .A_DO(PORT_A_RD_DATA), - .B_CLK(PORT_B_CLK), - .B_EN(PORT_B_CLK_EN), - .B_WE(PORT_B_WR_EN), - .B_BM({{(20-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), - .B_DI({{(20-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), - .B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}), - .B_DO(PORT_B_RD_DATA), - ); - end else if (OPTION_MODE == "40K") begin - CC_BRAM_40K #( - .INIT_00(INIT['h00*320+:320]), - .INIT_01(INIT['h01*320+:320]), - .INIT_02(INIT['h02*320+:320]), - .INIT_03(INIT['h03*320+:320]), - .INIT_04(INIT['h04*320+:320]), - .INIT_05(INIT['h05*320+:320]), - .INIT_06(INIT['h06*320+:320]), - .INIT_07(INIT['h07*320+:320]), - .INIT_08(INIT['h08*320+:320]), - .INIT_09(INIT['h09*320+:320]), - .INIT_0A(INIT['h0a*320+:320]), - .INIT_0B(INIT['h0b*320+:320]), - .INIT_0C(INIT['h0c*320+:320]), - .INIT_0D(INIT['h0d*320+:320]), - .INIT_0E(INIT['h0e*320+:320]), - .INIT_0F(INIT['h0f*320+:320]), - .INIT_10(INIT['h10*320+:320]), - .INIT_11(INIT['h11*320+:320]), - .INIT_12(INIT['h12*320+:320]), - .INIT_13(INIT['h13*320+:320]), - .INIT_14(INIT['h14*320+:320]), - .INIT_15(INIT['h15*320+:320]), - .INIT_16(INIT['h16*320+:320]), - .INIT_17(INIT['h17*320+:320]), - .INIT_18(INIT['h18*320+:320]), - .INIT_19(INIT['h19*320+:320]), - .INIT_1A(INIT['h1a*320+:320]), - .INIT_1B(INIT['h1b*320+:320]), - .INIT_1C(INIT['h1c*320+:320]), - .INIT_1D(INIT['h1d*320+:320]), - .INIT_1E(INIT['h1e*320+:320]), - .INIT_1F(INIT['h1f*320+:320]), - .INIT_20(INIT['h20*320+:320]), - .INIT_21(INIT['h21*320+:320]), - .INIT_22(INIT['h22*320+:320]), - .INIT_23(INIT['h23*320+:320]), - .INIT_24(INIT['h24*320+:320]), - .INIT_25(INIT['h25*320+:320]), - .INIT_26(INIT['h26*320+:320]), - .INIT_27(INIT['h27*320+:320]), - .INIT_28(INIT['h28*320+:320]), - .INIT_29(INIT['h29*320+:320]), - .INIT_2A(INIT['h2a*320+:320]), - .INIT_2B(INIT['h2b*320+:320]), - .INIT_2C(INIT['h2c*320+:320]), - .INIT_2D(INIT['h2d*320+:320]), - .INIT_2E(INIT['h2e*320+:320]), - .INIT_2F(INIT['h2f*320+:320]), - .INIT_30(INIT['h30*320+:320]), - .INIT_31(INIT['h31*320+:320]), - .INIT_32(INIT['h32*320+:320]), - .INIT_33(INIT['h33*320+:320]), - .INIT_34(INIT['h34*320+:320]), - .INIT_35(INIT['h35*320+:320]), - .INIT_36(INIT['h36*320+:320]), - .INIT_37(INIT['h37*320+:320]), - .INIT_38(INIT['h38*320+:320]), - .INIT_39(INIT['h39*320+:320]), - .INIT_3A(INIT['h3a*320+:320]), - .INIT_3B(INIT['h3b*320+:320]), - .INIT_3C(INIT['h3c*320+:320]), - .INIT_3D(INIT['h3d*320+:320]), - .INIT_3E(INIT['h3e*320+:320]), - .INIT_3F(INIT['h3f*320+:320]), - .INIT_40(INIT['h40*320+:320]), - .INIT_41(INIT['h41*320+:320]), - .INIT_42(INIT['h42*320+:320]), - .INIT_43(INIT['h43*320+:320]), - .INIT_44(INIT['h44*320+:320]), - .INIT_45(INIT['h45*320+:320]), - .INIT_46(INIT['h46*320+:320]), - .INIT_47(INIT['h47*320+:320]), - .INIT_48(INIT['h48*320+:320]), - .INIT_49(INIT['h49*320+:320]), - .INIT_4A(INIT['h4a*320+:320]), - .INIT_4B(INIT['h4b*320+:320]), - .INIT_4C(INIT['h4c*320+:320]), - .INIT_4D(INIT['h4d*320+:320]), - .INIT_4E(INIT['h4e*320+:320]), - .INIT_4F(INIT['h4f*320+:320]), - .INIT_50(INIT['h50*320+:320]), - .INIT_51(INIT['h51*320+:320]), - .INIT_52(INIT['h52*320+:320]), - .INIT_53(INIT['h53*320+:320]), - .INIT_54(INIT['h54*320+:320]), - .INIT_55(INIT['h55*320+:320]), - .INIT_56(INIT['h56*320+:320]), - .INIT_57(INIT['h57*320+:320]), - .INIT_58(INIT['h58*320+:320]), - .INIT_59(INIT['h59*320+:320]), - .INIT_5A(INIT['h5a*320+:320]), - .INIT_5B(INIT['h5b*320+:320]), - .INIT_5C(INIT['h5c*320+:320]), - .INIT_5D(INIT['h5d*320+:320]), - .INIT_5E(INIT['h5e*320+:320]), - .INIT_5F(INIT['h5f*320+:320]), - .INIT_60(INIT['h60*320+:320]), - .INIT_61(INIT['h61*320+:320]), - .INIT_62(INIT['h62*320+:320]), - .INIT_63(INIT['h63*320+:320]), - .INIT_64(INIT['h64*320+:320]), - .INIT_65(INIT['h65*320+:320]), - .INIT_66(INIT['h66*320+:320]), - .INIT_67(INIT['h67*320+:320]), - .INIT_68(INIT['h68*320+:320]), - .INIT_69(INIT['h69*320+:320]), - .INIT_6A(INIT['h6a*320+:320]), - .INIT_6B(INIT['h6b*320+:320]), - .INIT_6C(INIT['h6c*320+:320]), - .INIT_6D(INIT['h6d*320+:320]), - .INIT_6E(INIT['h6e*320+:320]), - .INIT_6F(INIT['h6f*320+:320]), - .INIT_70(INIT['h70*320+:320]), - .INIT_71(INIT['h71*320+:320]), - .INIT_72(INIT['h72*320+:320]), - .INIT_73(INIT['h73*320+:320]), - .INIT_74(INIT['h74*320+:320]), - .INIT_75(INIT['h75*320+:320]), - .INIT_76(INIT['h76*320+:320]), - .INIT_77(INIT['h77*320+:320]), - .INIT_78(INIT['h78*320+:320]), - .INIT_79(INIT['h79*320+:320]), - .INIT_7A(INIT['h7a*320+:320]), - .INIT_7B(INIT['h7b*320+:320]), - .INIT_7C(INIT['h7c*320+:320]), - .INIT_7D(INIT['h7d*320+:320]), - .INIT_7E(INIT['h7e*320+:320]), - .INIT_7F(INIT['h7f*320+:320]), - .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), - .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), - .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), - .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), - .RAM_MODE("TDP"), - .A_WR_MODE(PORT_A_OPTION_WR_MODE), - .B_WR_MODE(PORT_B_OPTION_WR_MODE), - .A_CLK_INV(!PORT_A_CLK_POL), - .B_CLK_INV(!PORT_B_CLK_POL), - ) _TECHMAP_REPLACE_ ( - .A_CLK(PORT_A_CLK), - .A_EN(PORT_A_CLK_EN), - .A_WE(PORT_A_WR_EN), - .A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), - .A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), - .A_ADDR({PORT_A_ADDR[14:0], 1'b0}), - .A_DO(PORT_A_RD_DATA), - .B_CLK(PORT_B_CLK), - .B_EN(PORT_B_CLK_EN), - .B_WE(PORT_B_WR_EN), - .B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), - .B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), - .B_ADDR({PORT_B_ADDR[14:0], 1'b0}), - .B_DO(PORT_B_RD_DATA), - ); - end else begin - wire CAS_A, CAS_B; - CC_BRAM_40K #( - .INIT_00(INIT['h00*320+:320]), - .INIT_01(INIT['h01*320+:320]), - .INIT_02(INIT['h02*320+:320]), - .INIT_03(INIT['h03*320+:320]), - .INIT_04(INIT['h04*320+:320]), - .INIT_05(INIT['h05*320+:320]), - .INIT_06(INIT['h06*320+:320]), - .INIT_07(INIT['h07*320+:320]), - .INIT_08(INIT['h08*320+:320]), - .INIT_09(INIT['h09*320+:320]), - .INIT_0A(INIT['h0a*320+:320]), - .INIT_0B(INIT['h0b*320+:320]), - .INIT_0C(INIT['h0c*320+:320]), - .INIT_0D(INIT['h0d*320+:320]), - .INIT_0E(INIT['h0e*320+:320]), - .INIT_0F(INIT['h0f*320+:320]), - .INIT_10(INIT['h10*320+:320]), - .INIT_11(INIT['h11*320+:320]), - .INIT_12(INIT['h12*320+:320]), - .INIT_13(INIT['h13*320+:320]), - .INIT_14(INIT['h14*320+:320]), - .INIT_15(INIT['h15*320+:320]), - .INIT_16(INIT['h16*320+:320]), - .INIT_17(INIT['h17*320+:320]), - .INIT_18(INIT['h18*320+:320]), - .INIT_19(INIT['h19*320+:320]), - .INIT_1A(INIT['h1a*320+:320]), - .INIT_1B(INIT['h1b*320+:320]), - .INIT_1C(INIT['h1c*320+:320]), - .INIT_1D(INIT['h1d*320+:320]), - .INIT_1E(INIT['h1e*320+:320]), - .INIT_1F(INIT['h1f*320+:320]), - .INIT_20(INIT['h20*320+:320]), - .INIT_21(INIT['h21*320+:320]), - .INIT_22(INIT['h22*320+:320]), - .INIT_23(INIT['h23*320+:320]), - .INIT_24(INIT['h24*320+:320]), - .INIT_25(INIT['h25*320+:320]), - .INIT_26(INIT['h26*320+:320]), - .INIT_27(INIT['h27*320+:320]), - .INIT_28(INIT['h28*320+:320]), - .INIT_29(INIT['h29*320+:320]), - .INIT_2A(INIT['h2a*320+:320]), - .INIT_2B(INIT['h2b*320+:320]), - .INIT_2C(INIT['h2c*320+:320]), - .INIT_2D(INIT['h2d*320+:320]), - .INIT_2E(INIT['h2e*320+:320]), - .INIT_2F(INIT['h2f*320+:320]), - .INIT_30(INIT['h30*320+:320]), - .INIT_31(INIT['h31*320+:320]), - .INIT_32(INIT['h32*320+:320]), - .INIT_33(INIT['h33*320+:320]), - .INIT_34(INIT['h34*320+:320]), - .INIT_35(INIT['h35*320+:320]), - .INIT_36(INIT['h36*320+:320]), - .INIT_37(INIT['h37*320+:320]), - .INIT_38(INIT['h38*320+:320]), - .INIT_39(INIT['h39*320+:320]), - .INIT_3A(INIT['h3a*320+:320]), - .INIT_3B(INIT['h3b*320+:320]), - .INIT_3C(INIT['h3c*320+:320]), - .INIT_3D(INIT['h3d*320+:320]), - .INIT_3E(INIT['h3e*320+:320]), - .INIT_3F(INIT['h3f*320+:320]), - .INIT_40(INIT['h40*320+:320]), - .INIT_41(INIT['h41*320+:320]), - .INIT_42(INIT['h42*320+:320]), - .INIT_43(INIT['h43*320+:320]), - .INIT_44(INIT['h44*320+:320]), - .INIT_45(INIT['h45*320+:320]), - .INIT_46(INIT['h46*320+:320]), - .INIT_47(INIT['h47*320+:320]), - .INIT_48(INIT['h48*320+:320]), - .INIT_49(INIT['h49*320+:320]), - .INIT_4A(INIT['h4a*320+:320]), - .INIT_4B(INIT['h4b*320+:320]), - .INIT_4C(INIT['h4c*320+:320]), - .INIT_4D(INIT['h4d*320+:320]), - .INIT_4E(INIT['h4e*320+:320]), - .INIT_4F(INIT['h4f*320+:320]), - .INIT_50(INIT['h50*320+:320]), - .INIT_51(INIT['h51*320+:320]), - .INIT_52(INIT['h52*320+:320]), - .INIT_53(INIT['h53*320+:320]), - .INIT_54(INIT['h54*320+:320]), - .INIT_55(INIT['h55*320+:320]), - .INIT_56(INIT['h56*320+:320]), - .INIT_57(INIT['h57*320+:320]), - .INIT_58(INIT['h58*320+:320]), - .INIT_59(INIT['h59*320+:320]), - .INIT_5A(INIT['h5a*320+:320]), - .INIT_5B(INIT['h5b*320+:320]), - .INIT_5C(INIT['h5c*320+:320]), - .INIT_5D(INIT['h5d*320+:320]), - .INIT_5E(INIT['h5e*320+:320]), - .INIT_5F(INIT['h5f*320+:320]), - .INIT_60(INIT['h60*320+:320]), - .INIT_61(INIT['h61*320+:320]), - .INIT_62(INIT['h62*320+:320]), - .INIT_63(INIT['h63*320+:320]), - .INIT_64(INIT['h64*320+:320]), - .INIT_65(INIT['h65*320+:320]), - .INIT_66(INIT['h66*320+:320]), - .INIT_67(INIT['h67*320+:320]), - .INIT_68(INIT['h68*320+:320]), - .INIT_69(INIT['h69*320+:320]), - .INIT_6A(INIT['h6a*320+:320]), - .INIT_6B(INIT['h6b*320+:320]), - .INIT_6C(INIT['h6c*320+:320]), - .INIT_6D(INIT['h6d*320+:320]), - .INIT_6E(INIT['h6e*320+:320]), - .INIT_6F(INIT['h6f*320+:320]), - .INIT_70(INIT['h70*320+:320]), - .INIT_71(INIT['h71*320+:320]), - .INIT_72(INIT['h72*320+:320]), - .INIT_73(INIT['h73*320+:320]), - .INIT_74(INIT['h74*320+:320]), - .INIT_75(INIT['h75*320+:320]), - .INIT_76(INIT['h76*320+:320]), - .INIT_77(INIT['h77*320+:320]), - .INIT_78(INIT['h78*320+:320]), - .INIT_79(INIT['h79*320+:320]), - .INIT_7A(INIT['h7a*320+:320]), - .INIT_7B(INIT['h7b*320+:320]), - .INIT_7C(INIT['h7c*320+:320]), - .INIT_7D(INIT['h7d*320+:320]), - .INIT_7E(INIT['h7e*320+:320]), - .INIT_7F(INIT['h7f*320+:320]), - .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), - .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), - .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), - .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), - .RAM_MODE("TDP"), - .A_WR_MODE(PORT_A_OPTION_WR_MODE), - .B_WR_MODE(PORT_B_OPTION_WR_MODE), - .A_CLK_INV(!PORT_A_CLK_POL), - .B_CLK_INV(!PORT_B_CLK_POL), - .CAS("LOWER"), - ) lower ( - .A_CO(CAS_A), - .B_CO(CAS_B), - .A_CLK(PORT_A_CLK), - .A_EN(PORT_A_CLK_EN), - .A_WE(PORT_A_WR_EN), - .A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), - .A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), - .A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}), - .B_CLK(PORT_B_CLK), - .B_EN(PORT_B_CLK_EN), - .B_WE(PORT_B_WR_EN), - .B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), - .B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), - .B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}), - ); - CC_BRAM_40K #( - .INIT_00(INIT['h80*320+:320]), - .INIT_01(INIT['h81*320+:320]), - .INIT_02(INIT['h82*320+:320]), - .INIT_03(INIT['h83*320+:320]), - .INIT_04(INIT['h84*320+:320]), - .INIT_05(INIT['h85*320+:320]), - .INIT_06(INIT['h86*320+:320]), - .INIT_07(INIT['h87*320+:320]), - .INIT_08(INIT['h88*320+:320]), - .INIT_09(INIT['h89*320+:320]), - .INIT_0A(INIT['h8a*320+:320]), - .INIT_0B(INIT['h8b*320+:320]), - .INIT_0C(INIT['h8c*320+:320]), - .INIT_0D(INIT['h8d*320+:320]), - .INIT_0E(INIT['h8e*320+:320]), - .INIT_0F(INIT['h8f*320+:320]), - .INIT_10(INIT['h90*320+:320]), - .INIT_11(INIT['h91*320+:320]), - .INIT_12(INIT['h92*320+:320]), - .INIT_13(INIT['h93*320+:320]), - .INIT_14(INIT['h94*320+:320]), - .INIT_15(INIT['h95*320+:320]), - .INIT_16(INIT['h96*320+:320]), - .INIT_17(INIT['h97*320+:320]), - .INIT_18(INIT['h98*320+:320]), - .INIT_19(INIT['h99*320+:320]), - .INIT_1A(INIT['h9a*320+:320]), - .INIT_1B(INIT['h9b*320+:320]), - .INIT_1C(INIT['h9c*320+:320]), - .INIT_1D(INIT['h9d*320+:320]), - .INIT_1E(INIT['h9e*320+:320]), - .INIT_1F(INIT['h9f*320+:320]), - .INIT_20(INIT['ha0*320+:320]), - .INIT_21(INIT['ha1*320+:320]), - .INIT_22(INIT['ha2*320+:320]), - .INIT_23(INIT['ha3*320+:320]), - .INIT_24(INIT['ha4*320+:320]), - .INIT_25(INIT['ha5*320+:320]), - .INIT_26(INIT['ha6*320+:320]), - .INIT_27(INIT['ha7*320+:320]), - .INIT_28(INIT['ha8*320+:320]), - .INIT_29(INIT['ha9*320+:320]), - .INIT_2A(INIT['haa*320+:320]), - .INIT_2B(INIT['hab*320+:320]), - .INIT_2C(INIT['hac*320+:320]), - .INIT_2D(INIT['had*320+:320]), - .INIT_2E(INIT['hae*320+:320]), - .INIT_2F(INIT['haf*320+:320]), - .INIT_30(INIT['hb0*320+:320]), - .INIT_31(INIT['hb1*320+:320]), - .INIT_32(INIT['hb2*320+:320]), - .INIT_33(INIT['hb3*320+:320]), - .INIT_34(INIT['hb4*320+:320]), - .INIT_35(INIT['hb5*320+:320]), - .INIT_36(INIT['hb6*320+:320]), - .INIT_37(INIT['hb7*320+:320]), - .INIT_38(INIT['hb8*320+:320]), - .INIT_39(INIT['hb9*320+:320]), - .INIT_3A(INIT['hba*320+:320]), - .INIT_3B(INIT['hbb*320+:320]), - .INIT_3C(INIT['hbc*320+:320]), - .INIT_3D(INIT['hbd*320+:320]), - .INIT_3E(INIT['hbe*320+:320]), - .INIT_3F(INIT['hbf*320+:320]), - .INIT_40(INIT['hc0*320+:320]), - .INIT_41(INIT['hc1*320+:320]), - .INIT_42(INIT['hc2*320+:320]), - .INIT_43(INIT['hc3*320+:320]), - .INIT_44(INIT['hc4*320+:320]), - .INIT_45(INIT['hc5*320+:320]), - .INIT_46(INIT['hc6*320+:320]), - .INIT_47(INIT['hc7*320+:320]), - .INIT_48(INIT['hc8*320+:320]), - .INIT_49(INIT['hc9*320+:320]), - .INIT_4A(INIT['hca*320+:320]), - .INIT_4B(INIT['hcb*320+:320]), - .INIT_4C(INIT['hcc*320+:320]), - .INIT_4D(INIT['hcd*320+:320]), - .INIT_4E(INIT['hce*320+:320]), - .INIT_4F(INIT['hcf*320+:320]), - .INIT_50(INIT['hd0*320+:320]), - .INIT_51(INIT['hd1*320+:320]), - .INIT_52(INIT['hd2*320+:320]), - .INIT_53(INIT['hd3*320+:320]), - .INIT_54(INIT['hd4*320+:320]), - .INIT_55(INIT['hd5*320+:320]), - .INIT_56(INIT['hd6*320+:320]), - .INIT_57(INIT['hd7*320+:320]), - .INIT_58(INIT['hd8*320+:320]), - .INIT_59(INIT['hd9*320+:320]), - .INIT_5A(INIT['hda*320+:320]), - .INIT_5B(INIT['hdb*320+:320]), - .INIT_5C(INIT['hdc*320+:320]), - .INIT_5D(INIT['hdd*320+:320]), - .INIT_5E(INIT['hde*320+:320]), - .INIT_5F(INIT['hdf*320+:320]), - .INIT_60(INIT['he0*320+:320]), - .INIT_61(INIT['he1*320+:320]), - .INIT_62(INIT['he2*320+:320]), - .INIT_63(INIT['he3*320+:320]), - .INIT_64(INIT['he4*320+:320]), - .INIT_65(INIT['he5*320+:320]), - .INIT_66(INIT['he6*320+:320]), - .INIT_67(INIT['he7*320+:320]), - .INIT_68(INIT['he8*320+:320]), - .INIT_69(INIT['he9*320+:320]), - .INIT_6A(INIT['hea*320+:320]), - .INIT_6B(INIT['heb*320+:320]), - .INIT_6C(INIT['hec*320+:320]), - .INIT_6D(INIT['hed*320+:320]), - .INIT_6E(INIT['hee*320+:320]), - .INIT_6F(INIT['hef*320+:320]), - .INIT_70(INIT['hf0*320+:320]), - .INIT_71(INIT['hf1*320+:320]), - .INIT_72(INIT['hf2*320+:320]), - .INIT_73(INIT['hf3*320+:320]), - .INIT_74(INIT['hf4*320+:320]), - .INIT_75(INIT['hf5*320+:320]), - .INIT_76(INIT['hf6*320+:320]), - .INIT_77(INIT['hf7*320+:320]), - .INIT_78(INIT['hf8*320+:320]), - .INIT_79(INIT['hf9*320+:320]), - .INIT_7A(INIT['hfa*320+:320]), - .INIT_7B(INIT['hfb*320+:320]), - .INIT_7C(INIT['hfc*320+:320]), - .INIT_7D(INIT['hfd*320+:320]), - .INIT_7E(INIT['hfe*320+:320]), - .INIT_7F(INIT['hff*320+:320]), - .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), - .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), - .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), - .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), - .RAM_MODE("TDP"), - .A_WR_MODE(PORT_A_OPTION_WR_MODE), - .B_WR_MODE(PORT_B_OPTION_WR_MODE), - .A_CLK_INV(!PORT_A_CLK_POL), - .B_CLK_INV(!PORT_B_CLK_POL), - .CAS("UPPER"), - ) upper ( - .A_CI(CAS_A), - .B_CI(CAS_B), - .A_CLK(PORT_A_CLK), - .A_EN(PORT_A_CLK_EN), - .A_WE(PORT_A_WR_EN), - .A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), - .A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), - .A_DO(PORT_A_RD_DATA), - .A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}), - .B_CLK(PORT_B_CLK), - .B_EN(PORT_B_CLK_EN), - .B_WE(PORT_B_WR_EN), - .B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), - .B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), - .B_DO(PORT_B_RD_DATA), - .B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}), - ); - end -endgenerate - -endmodule - - -module $__CC_BRAM_SDP_(...); - -parameter INIT = 0; -parameter OPTION_MODE = "20K"; -parameter OPTION_WR_MODE = "NO_CHANGE"; - -parameter PORT_W_CLK_POL = 1; -parameter PORT_W_USED = 1; -parameter PORT_W_WIDTH = 40; -parameter PORT_W_WR_BE_WIDTH = 40; - -parameter PORT_R_CLK_POL = 1; -parameter PORT_R_USED = 1; -parameter PORT_R_WIDTH = 40; - -input PORT_W_CLK; -input PORT_W_CLK_EN; -input PORT_W_WR_EN; -input [15:0] PORT_W_ADDR; -input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; -input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; - -input PORT_R_CLK; -input PORT_R_CLK_EN; -input [15:0] PORT_R_ADDR; -output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; - -generate - if (OPTION_MODE == "20K") begin - CC_BRAM_20K #( - .INIT_00(INIT['h00*320+:320]), - .INIT_01(INIT['h01*320+:320]), - .INIT_02(INIT['h02*320+:320]), - .INIT_03(INIT['h03*320+:320]), - .INIT_04(INIT['h04*320+:320]), - .INIT_05(INIT['h05*320+:320]), - .INIT_06(INIT['h06*320+:320]), - .INIT_07(INIT['h07*320+:320]), - .INIT_08(INIT['h08*320+:320]), - .INIT_09(INIT['h09*320+:320]), - .INIT_0A(INIT['h0a*320+:320]), - .INIT_0B(INIT['h0b*320+:320]), - .INIT_0C(INIT['h0c*320+:320]), - .INIT_0D(INIT['h0d*320+:320]), - .INIT_0E(INIT['h0e*320+:320]), - .INIT_0F(INIT['h0f*320+:320]), - .INIT_10(INIT['h10*320+:320]), - .INIT_11(INIT['h11*320+:320]), - .INIT_12(INIT['h12*320+:320]), - .INIT_13(INIT['h13*320+:320]), - .INIT_14(INIT['h14*320+:320]), - .INIT_15(INIT['h15*320+:320]), - .INIT_16(INIT['h16*320+:320]), - .INIT_17(INIT['h17*320+:320]), - .INIT_18(INIT['h18*320+:320]), - .INIT_19(INIT['h19*320+:320]), - .INIT_1A(INIT['h1a*320+:320]), - .INIT_1B(INIT['h1b*320+:320]), - .INIT_1C(INIT['h1c*320+:320]), - .INIT_1D(INIT['h1d*320+:320]), - .INIT_1E(INIT['h1e*320+:320]), - .INIT_1F(INIT['h1f*320+:320]), - .INIT_20(INIT['h20*320+:320]), - .INIT_21(INIT['h21*320+:320]), - .INIT_22(INIT['h22*320+:320]), - .INIT_23(INIT['h23*320+:320]), - .INIT_24(INIT['h24*320+:320]), - .INIT_25(INIT['h25*320+:320]), - .INIT_26(INIT['h26*320+:320]), - .INIT_27(INIT['h27*320+:320]), - .INIT_28(INIT['h28*320+:320]), - .INIT_29(INIT['h29*320+:320]), - .INIT_2A(INIT['h2a*320+:320]), - .INIT_2B(INIT['h2b*320+:320]), - .INIT_2C(INIT['h2c*320+:320]), - .INIT_2D(INIT['h2d*320+:320]), - .INIT_2E(INIT['h2e*320+:320]), - .INIT_2F(INIT['h2f*320+:320]), - .INIT_30(INIT['h30*320+:320]), - .INIT_31(INIT['h31*320+:320]), - .INIT_32(INIT['h32*320+:320]), - .INIT_33(INIT['h33*320+:320]), - .INIT_34(INIT['h34*320+:320]), - .INIT_35(INIT['h35*320+:320]), - .INIT_36(INIT['h36*320+:320]), - .INIT_37(INIT['h37*320+:320]), - .INIT_38(INIT['h38*320+:320]), - .INIT_39(INIT['h39*320+:320]), - .INIT_3A(INIT['h3a*320+:320]), - .INIT_3B(INIT['h3b*320+:320]), - .INIT_3C(INIT['h3c*320+:320]), - .INIT_3D(INIT['h3d*320+:320]), - .INIT_3E(INIT['h3e*320+:320]), - .INIT_3F(INIT['h3f*320+:320]), - .A_RD_WIDTH(0), - .A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0), - .B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0), - .B_WR_WIDTH(0), - .RAM_MODE("SDP"), - .A_WR_MODE(OPTION_WR_MODE), - .B_WR_MODE(OPTION_WR_MODE), - .A_CLK_INV(!PORT_W_CLK_POL), - .B_CLK_INV(!PORT_R_CLK_POL), - ) _TECHMAP_REPLACE_ ( - .A_CLK(PORT_W_CLK), - .A_EN(PORT_W_CLK_EN), - .A_WE(PORT_W_WR_EN), - .A_BM(PORT_W_WR_BE[19:0]), - .B_BM({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[39:20]}), - .A_DI(PORT_W_WR_DATA[19:0]), - .B_DI({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[39:20]}), - .A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}), - .B_CLK(PORT_R_CLK), - .B_EN(PORT_R_CLK_EN), - .B_WE(1'b0), - .B_ADDR({PORT_R_ADDR[13:5], 1'b0, PORT_R_ADDR[4:0], 1'b0}), - .A_DO(PORT_R_RD_DATA[19:0]), - .B_DO(PORT_R_RD_DATA[39:20]), - ); - end else if (OPTION_MODE == "40K") begin - CC_BRAM_40K #( - .INIT_00(INIT['h00*320+:320]), - .INIT_01(INIT['h01*320+:320]), - .INIT_02(INIT['h02*320+:320]), - .INIT_03(INIT['h03*320+:320]), - .INIT_04(INIT['h04*320+:320]), - .INIT_05(INIT['h05*320+:320]), - .INIT_06(INIT['h06*320+:320]), - .INIT_07(INIT['h07*320+:320]), - .INIT_08(INIT['h08*320+:320]), - .INIT_09(INIT['h09*320+:320]), - .INIT_0A(INIT['h0a*320+:320]), - .INIT_0B(INIT['h0b*320+:320]), - .INIT_0C(INIT['h0c*320+:320]), - .INIT_0D(INIT['h0d*320+:320]), - .INIT_0E(INIT['h0e*320+:320]), - .INIT_0F(INIT['h0f*320+:320]), - .INIT_10(INIT['h10*320+:320]), - .INIT_11(INIT['h11*320+:320]), - .INIT_12(INIT['h12*320+:320]), - .INIT_13(INIT['h13*320+:320]), - .INIT_14(INIT['h14*320+:320]), - .INIT_15(INIT['h15*320+:320]), - .INIT_16(INIT['h16*320+:320]), - .INIT_17(INIT['h17*320+:320]), - .INIT_18(INIT['h18*320+:320]), - .INIT_19(INIT['h19*320+:320]), - .INIT_1A(INIT['h1a*320+:320]), - .INIT_1B(INIT['h1b*320+:320]), - .INIT_1C(INIT['h1c*320+:320]), - .INIT_1D(INIT['h1d*320+:320]), - .INIT_1E(INIT['h1e*320+:320]), - .INIT_1F(INIT['h1f*320+:320]), - .INIT_20(INIT['h20*320+:320]), - .INIT_21(INIT['h21*320+:320]), - .INIT_22(INIT['h22*320+:320]), - .INIT_23(INIT['h23*320+:320]), - .INIT_24(INIT['h24*320+:320]), - .INIT_25(INIT['h25*320+:320]), - .INIT_26(INIT['h26*320+:320]), - .INIT_27(INIT['h27*320+:320]), - .INIT_28(INIT['h28*320+:320]), - .INIT_29(INIT['h29*320+:320]), - .INIT_2A(INIT['h2a*320+:320]), - .INIT_2B(INIT['h2b*320+:320]), - .INIT_2C(INIT['h2c*320+:320]), - .INIT_2D(INIT['h2d*320+:320]), - .INIT_2E(INIT['h2e*320+:320]), - .INIT_2F(INIT['h2f*320+:320]), - .INIT_30(INIT['h30*320+:320]), - .INIT_31(INIT['h31*320+:320]), - .INIT_32(INIT['h32*320+:320]), - .INIT_33(INIT['h33*320+:320]), - .INIT_34(INIT['h34*320+:320]), - .INIT_35(INIT['h35*320+:320]), - .INIT_36(INIT['h36*320+:320]), - .INIT_37(INIT['h37*320+:320]), - .INIT_38(INIT['h38*320+:320]), - .INIT_39(INIT['h39*320+:320]), - .INIT_3A(INIT['h3a*320+:320]), - .INIT_3B(INIT['h3b*320+:320]), - .INIT_3C(INIT['h3c*320+:320]), - .INIT_3D(INIT['h3d*320+:320]), - .INIT_3E(INIT['h3e*320+:320]), - .INIT_3F(INIT['h3f*320+:320]), - .INIT_40(INIT['h40*320+:320]), - .INIT_41(INIT['h41*320+:320]), - .INIT_42(INIT['h42*320+:320]), - .INIT_43(INIT['h43*320+:320]), - .INIT_44(INIT['h44*320+:320]), - .INIT_45(INIT['h45*320+:320]), - .INIT_46(INIT['h46*320+:320]), - .INIT_47(INIT['h47*320+:320]), - .INIT_48(INIT['h48*320+:320]), - .INIT_49(INIT['h49*320+:320]), - .INIT_4A(INIT['h4a*320+:320]), - .INIT_4B(INIT['h4b*320+:320]), - .INIT_4C(INIT['h4c*320+:320]), - .INIT_4D(INIT['h4d*320+:320]), - .INIT_4E(INIT['h4e*320+:320]), - .INIT_4F(INIT['h4f*320+:320]), - .INIT_50(INIT['h50*320+:320]), - .INIT_51(INIT['h51*320+:320]), - .INIT_52(INIT['h52*320+:320]), - .INIT_53(INIT['h53*320+:320]), - .INIT_54(INIT['h54*320+:320]), - .INIT_55(INIT['h55*320+:320]), - .INIT_56(INIT['h56*320+:320]), - .INIT_57(INIT['h57*320+:320]), - .INIT_58(INIT['h58*320+:320]), - .INIT_59(INIT['h59*320+:320]), - .INIT_5A(INIT['h5a*320+:320]), - .INIT_5B(INIT['h5b*320+:320]), - .INIT_5C(INIT['h5c*320+:320]), - .INIT_5D(INIT['h5d*320+:320]), - .INIT_5E(INIT['h5e*320+:320]), - .INIT_5F(INIT['h5f*320+:320]), - .INIT_60(INIT['h60*320+:320]), - .INIT_61(INIT['h61*320+:320]), - .INIT_62(INIT['h62*320+:320]), - .INIT_63(INIT['h63*320+:320]), - .INIT_64(INIT['h64*320+:320]), - .INIT_65(INIT['h65*320+:320]), - .INIT_66(INIT['h66*320+:320]), - .INIT_67(INIT['h67*320+:320]), - .INIT_68(INIT['h68*320+:320]), - .INIT_69(INIT['h69*320+:320]), - .INIT_6A(INIT['h6a*320+:320]), - .INIT_6B(INIT['h6b*320+:320]), - .INIT_6C(INIT['h6c*320+:320]), - .INIT_6D(INIT['h6d*320+:320]), - .INIT_6E(INIT['h6e*320+:320]), - .INIT_6F(INIT['h6f*320+:320]), - .INIT_70(INIT['h70*320+:320]), - .INIT_71(INIT['h71*320+:320]), - .INIT_72(INIT['h72*320+:320]), - .INIT_73(INIT['h73*320+:320]), - .INIT_74(INIT['h74*320+:320]), - .INIT_75(INIT['h75*320+:320]), - .INIT_76(INIT['h76*320+:320]), - .INIT_77(INIT['h77*320+:320]), - .INIT_78(INIT['h78*320+:320]), - .INIT_79(INIT['h79*320+:320]), - .INIT_7A(INIT['h7a*320+:320]), - .INIT_7B(INIT['h7b*320+:320]), - .INIT_7C(INIT['h7c*320+:320]), - .INIT_7D(INIT['h7d*320+:320]), - .INIT_7E(INIT['h7e*320+:320]), - .INIT_7F(INIT['h7f*320+:320]), - .A_RD_WIDTH(0), - .A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0), - .B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0), - .B_WR_WIDTH(0), - .RAM_MODE("SDP"), - .A_WR_MODE(OPTION_WR_MODE), - .B_WR_MODE(OPTION_WR_MODE), - .A_CLK_INV(!PORT_W_CLK_POL), - .B_CLK_INV(!PORT_R_CLK_POL), - ) _TECHMAP_REPLACE_ ( - .A_CLK(PORT_W_CLK), - .A_EN(PORT_W_CLK_EN), - .A_WE(PORT_W_WR_EN), - .A_BM(PORT_W_WR_BE[39:0]), - .B_BM({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[79:40]}), - .A_DI(PORT_W_WR_DATA[39:0]), - .B_DI({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[79:40]}), - .A_ADDR({PORT_W_ADDR[14:0], 1'b0}), - .B_CLK(PORT_R_CLK), - .B_EN(PORT_R_CLK_EN), - .B_WE(1'b0), - .B_ADDR({PORT_R_ADDR[14:0], 1'b0}), - .A_DO(PORT_R_RD_DATA[39:0]), - .B_DO(PORT_R_RD_DATA[79:40]), - ); - end -endgenerate - -endmodule +module $__CC_BRAM_TDP_(...); + +parameter INIT = 0; +parameter OPTION_MODE = "20K"; + +parameter PORT_A_CLK_POL = 1; +parameter PORT_A_RD_USED = 1; +parameter PORT_A_WR_USED = 1; +parameter PORT_A_RD_WIDTH = 1; +parameter PORT_A_WR_WIDTH = 1; +parameter PORT_A_WR_BE_WIDTH = 1; +parameter PORT_A_OPTION_WR_MODE = "NO_CHANGE"; + +parameter PORT_B_CLK_POL = 1; +parameter PORT_B_RD_USED = 1; +parameter PORT_B_WR_USED = 1; +parameter PORT_B_RD_WIDTH = 1; +parameter PORT_B_WR_WIDTH = 1; +parameter PORT_B_WR_BE_WIDTH = 1; +parameter PORT_B_OPTION_WR_MODE = "NO_CHANGE"; + +input PORT_A_CLK; +input PORT_A_CLK_EN; +input PORT_A_WR_EN; +input [15:0] PORT_A_ADDR; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; +input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA; +output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA; + +input PORT_B_CLK; +input PORT_B_CLK_EN; +input PORT_B_WR_EN; +input [15:0] PORT_B_ADDR; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; +input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA; +output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA; + +generate + if (OPTION_MODE == "20K") begin + CC_BRAM_20K #( + .INIT_00(INIT['h00*320+:320]), + .INIT_01(INIT['h01*320+:320]), + .INIT_02(INIT['h02*320+:320]), + .INIT_03(INIT['h03*320+:320]), + .INIT_04(INIT['h04*320+:320]), + .INIT_05(INIT['h05*320+:320]), + .INIT_06(INIT['h06*320+:320]), + .INIT_07(INIT['h07*320+:320]), + .INIT_08(INIT['h08*320+:320]), + .INIT_09(INIT['h09*320+:320]), + .INIT_0A(INIT['h0a*320+:320]), + .INIT_0B(INIT['h0b*320+:320]), + .INIT_0C(INIT['h0c*320+:320]), + .INIT_0D(INIT['h0d*320+:320]), + .INIT_0E(INIT['h0e*320+:320]), + .INIT_0F(INIT['h0f*320+:320]), + .INIT_10(INIT['h10*320+:320]), + .INIT_11(INIT['h11*320+:320]), + .INIT_12(INIT['h12*320+:320]), + .INIT_13(INIT['h13*320+:320]), + .INIT_14(INIT['h14*320+:320]), + .INIT_15(INIT['h15*320+:320]), + .INIT_16(INIT['h16*320+:320]), + .INIT_17(INIT['h17*320+:320]), + .INIT_18(INIT['h18*320+:320]), + .INIT_19(INIT['h19*320+:320]), + .INIT_1A(INIT['h1a*320+:320]), + .INIT_1B(INIT['h1b*320+:320]), + .INIT_1C(INIT['h1c*320+:320]), + .INIT_1D(INIT['h1d*320+:320]), + .INIT_1E(INIT['h1e*320+:320]), + .INIT_1F(INIT['h1f*320+:320]), + .INIT_20(INIT['h20*320+:320]), + .INIT_21(INIT['h21*320+:320]), + .INIT_22(INIT['h22*320+:320]), + .INIT_23(INIT['h23*320+:320]), + .INIT_24(INIT['h24*320+:320]), + .INIT_25(INIT['h25*320+:320]), + .INIT_26(INIT['h26*320+:320]), + .INIT_27(INIT['h27*320+:320]), + .INIT_28(INIT['h28*320+:320]), + .INIT_29(INIT['h29*320+:320]), + .INIT_2A(INIT['h2a*320+:320]), + .INIT_2B(INIT['h2b*320+:320]), + .INIT_2C(INIT['h2c*320+:320]), + .INIT_2D(INIT['h2d*320+:320]), + .INIT_2E(INIT['h2e*320+:320]), + .INIT_2F(INIT['h2f*320+:320]), + .INIT_30(INIT['h30*320+:320]), + .INIT_31(INIT['h31*320+:320]), + .INIT_32(INIT['h32*320+:320]), + .INIT_33(INIT['h33*320+:320]), + .INIT_34(INIT['h34*320+:320]), + .INIT_35(INIT['h35*320+:320]), + .INIT_36(INIT['h36*320+:320]), + .INIT_37(INIT['h37*320+:320]), + .INIT_38(INIT['h38*320+:320]), + .INIT_39(INIT['h39*320+:320]), + .INIT_3A(INIT['h3a*320+:320]), + .INIT_3B(INIT['h3b*320+:320]), + .INIT_3C(INIT['h3c*320+:320]), + .INIT_3D(INIT['h3d*320+:320]), + .INIT_3E(INIT['h3e*320+:320]), + .INIT_3F(INIT['h3f*320+:320]), + .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), + .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), + .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), + .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), + .RAM_MODE("TDP"), + .A_WR_MODE(PORT_A_OPTION_WR_MODE), + .B_WR_MODE(PORT_B_OPTION_WR_MODE), + .A_CLK_INV(!PORT_A_CLK_POL), + .B_CLK_INV(!PORT_B_CLK_POL), + ) _TECHMAP_REPLACE_ ( + .A_CLK(PORT_A_CLK), + .A_EN(PORT_A_CLK_EN), + .A_WE(PORT_A_WR_EN), + .A_BM({{(20-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), + .A_DI({{(20-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), + .A_ADDR({PORT_A_ADDR[13:5], 1'b0, PORT_A_ADDR[4:0], 1'b0}), + .A_DO(PORT_A_RD_DATA), + .B_CLK(PORT_B_CLK), + .B_EN(PORT_B_CLK_EN), + .B_WE(PORT_B_WR_EN), + .B_BM({{(20-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), + .B_DI({{(20-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), + .B_ADDR({PORT_B_ADDR[13:5], 1'b0, PORT_B_ADDR[4:0], 1'b0}), + .B_DO(PORT_B_RD_DATA), + ); + end else if (OPTION_MODE == "40K") begin + CC_BRAM_40K #( + .INIT_00(INIT['h00*320+:320]), + .INIT_01(INIT['h01*320+:320]), + .INIT_02(INIT['h02*320+:320]), + .INIT_03(INIT['h03*320+:320]), + .INIT_04(INIT['h04*320+:320]), + .INIT_05(INIT['h05*320+:320]), + .INIT_06(INIT['h06*320+:320]), + .INIT_07(INIT['h07*320+:320]), + .INIT_08(INIT['h08*320+:320]), + .INIT_09(INIT['h09*320+:320]), + .INIT_0A(INIT['h0a*320+:320]), + .INIT_0B(INIT['h0b*320+:320]), + .INIT_0C(INIT['h0c*320+:320]), + .INIT_0D(INIT['h0d*320+:320]), + .INIT_0E(INIT['h0e*320+:320]), + .INIT_0F(INIT['h0f*320+:320]), + .INIT_10(INIT['h10*320+:320]), + .INIT_11(INIT['h11*320+:320]), + .INIT_12(INIT['h12*320+:320]), + .INIT_13(INIT['h13*320+:320]), + .INIT_14(INIT['h14*320+:320]), + .INIT_15(INIT['h15*320+:320]), + .INIT_16(INIT['h16*320+:320]), + .INIT_17(INIT['h17*320+:320]), + .INIT_18(INIT['h18*320+:320]), + .INIT_19(INIT['h19*320+:320]), + .INIT_1A(INIT['h1a*320+:320]), + .INIT_1B(INIT['h1b*320+:320]), + .INIT_1C(INIT['h1c*320+:320]), + .INIT_1D(INIT['h1d*320+:320]), + .INIT_1E(INIT['h1e*320+:320]), + .INIT_1F(INIT['h1f*320+:320]), + .INIT_20(INIT['h20*320+:320]), + .INIT_21(INIT['h21*320+:320]), + .INIT_22(INIT['h22*320+:320]), + .INIT_23(INIT['h23*320+:320]), + .INIT_24(INIT['h24*320+:320]), + .INIT_25(INIT['h25*320+:320]), + .INIT_26(INIT['h26*320+:320]), + .INIT_27(INIT['h27*320+:320]), + .INIT_28(INIT['h28*320+:320]), + .INIT_29(INIT['h29*320+:320]), + .INIT_2A(INIT['h2a*320+:320]), + .INIT_2B(INIT['h2b*320+:320]), + .INIT_2C(INIT['h2c*320+:320]), + .INIT_2D(INIT['h2d*320+:320]), + .INIT_2E(INIT['h2e*320+:320]), + .INIT_2F(INIT['h2f*320+:320]), + .INIT_30(INIT['h30*320+:320]), + .INIT_31(INIT['h31*320+:320]), + .INIT_32(INIT['h32*320+:320]), + .INIT_33(INIT['h33*320+:320]), + .INIT_34(INIT['h34*320+:320]), + .INIT_35(INIT['h35*320+:320]), + .INIT_36(INIT['h36*320+:320]), + .INIT_37(INIT['h37*320+:320]), + .INIT_38(INIT['h38*320+:320]), + .INIT_39(INIT['h39*320+:320]), + .INIT_3A(INIT['h3a*320+:320]), + .INIT_3B(INIT['h3b*320+:320]), + .INIT_3C(INIT['h3c*320+:320]), + .INIT_3D(INIT['h3d*320+:320]), + .INIT_3E(INIT['h3e*320+:320]), + .INIT_3F(INIT['h3f*320+:320]), + .INIT_40(INIT['h40*320+:320]), + .INIT_41(INIT['h41*320+:320]), + .INIT_42(INIT['h42*320+:320]), + .INIT_43(INIT['h43*320+:320]), + .INIT_44(INIT['h44*320+:320]), + .INIT_45(INIT['h45*320+:320]), + .INIT_46(INIT['h46*320+:320]), + .INIT_47(INIT['h47*320+:320]), + .INIT_48(INIT['h48*320+:320]), + .INIT_49(INIT['h49*320+:320]), + .INIT_4A(INIT['h4a*320+:320]), + .INIT_4B(INIT['h4b*320+:320]), + .INIT_4C(INIT['h4c*320+:320]), + .INIT_4D(INIT['h4d*320+:320]), + .INIT_4E(INIT['h4e*320+:320]), + .INIT_4F(INIT['h4f*320+:320]), + .INIT_50(INIT['h50*320+:320]), + .INIT_51(INIT['h51*320+:320]), + .INIT_52(INIT['h52*320+:320]), + .INIT_53(INIT['h53*320+:320]), + .INIT_54(INIT['h54*320+:320]), + .INIT_55(INIT['h55*320+:320]), + .INIT_56(INIT['h56*320+:320]), + .INIT_57(INIT['h57*320+:320]), + .INIT_58(INIT['h58*320+:320]), + .INIT_59(INIT['h59*320+:320]), + .INIT_5A(INIT['h5a*320+:320]), + .INIT_5B(INIT['h5b*320+:320]), + .INIT_5C(INIT['h5c*320+:320]), + .INIT_5D(INIT['h5d*320+:320]), + .INIT_5E(INIT['h5e*320+:320]), + .INIT_5F(INIT['h5f*320+:320]), + .INIT_60(INIT['h60*320+:320]), + .INIT_61(INIT['h61*320+:320]), + .INIT_62(INIT['h62*320+:320]), + .INIT_63(INIT['h63*320+:320]), + .INIT_64(INIT['h64*320+:320]), + .INIT_65(INIT['h65*320+:320]), + .INIT_66(INIT['h66*320+:320]), + .INIT_67(INIT['h67*320+:320]), + .INIT_68(INIT['h68*320+:320]), + .INIT_69(INIT['h69*320+:320]), + .INIT_6A(INIT['h6a*320+:320]), + .INIT_6B(INIT['h6b*320+:320]), + .INIT_6C(INIT['h6c*320+:320]), + .INIT_6D(INIT['h6d*320+:320]), + .INIT_6E(INIT['h6e*320+:320]), + .INIT_6F(INIT['h6f*320+:320]), + .INIT_70(INIT['h70*320+:320]), + .INIT_71(INIT['h71*320+:320]), + .INIT_72(INIT['h72*320+:320]), + .INIT_73(INIT['h73*320+:320]), + .INIT_74(INIT['h74*320+:320]), + .INIT_75(INIT['h75*320+:320]), + .INIT_76(INIT['h76*320+:320]), + .INIT_77(INIT['h77*320+:320]), + .INIT_78(INIT['h78*320+:320]), + .INIT_79(INIT['h79*320+:320]), + .INIT_7A(INIT['h7a*320+:320]), + .INIT_7B(INIT['h7b*320+:320]), + .INIT_7C(INIT['h7c*320+:320]), + .INIT_7D(INIT['h7d*320+:320]), + .INIT_7E(INIT['h7e*320+:320]), + .INIT_7F(INIT['h7f*320+:320]), + .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), + .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), + .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), + .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), + .RAM_MODE("TDP"), + .A_WR_MODE(PORT_A_OPTION_WR_MODE), + .B_WR_MODE(PORT_B_OPTION_WR_MODE), + .A_CLK_INV(!PORT_A_CLK_POL), + .B_CLK_INV(!PORT_B_CLK_POL), + ) _TECHMAP_REPLACE_ ( + .A_CLK(PORT_A_CLK), + .A_EN(PORT_A_CLK_EN), + .A_WE(PORT_A_WR_EN), + .A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), + .A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), + .A_ADDR({PORT_A_ADDR[14:0], 1'b0}), + .A_DO(PORT_A_RD_DATA), + .B_CLK(PORT_B_CLK), + .B_EN(PORT_B_CLK_EN), + .B_WE(PORT_B_WR_EN), + .B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), + .B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), + .B_ADDR({PORT_B_ADDR[14:0], 1'b0}), + .B_DO(PORT_B_RD_DATA), + ); + end else begin + wire CAS_A, CAS_B; + CC_BRAM_40K #( + .INIT_00(INIT['h00*320+:320]), + .INIT_01(INIT['h01*320+:320]), + .INIT_02(INIT['h02*320+:320]), + .INIT_03(INIT['h03*320+:320]), + .INIT_04(INIT['h04*320+:320]), + .INIT_05(INIT['h05*320+:320]), + .INIT_06(INIT['h06*320+:320]), + .INIT_07(INIT['h07*320+:320]), + .INIT_08(INIT['h08*320+:320]), + .INIT_09(INIT['h09*320+:320]), + .INIT_0A(INIT['h0a*320+:320]), + .INIT_0B(INIT['h0b*320+:320]), + .INIT_0C(INIT['h0c*320+:320]), + .INIT_0D(INIT['h0d*320+:320]), + .INIT_0E(INIT['h0e*320+:320]), + .INIT_0F(INIT['h0f*320+:320]), + .INIT_10(INIT['h10*320+:320]), + .INIT_11(INIT['h11*320+:320]), + .INIT_12(INIT['h12*320+:320]), + .INIT_13(INIT['h13*320+:320]), + .INIT_14(INIT['h14*320+:320]), + .INIT_15(INIT['h15*320+:320]), + .INIT_16(INIT['h16*320+:320]), + .INIT_17(INIT['h17*320+:320]), + .INIT_18(INIT['h18*320+:320]), + .INIT_19(INIT['h19*320+:320]), + .INIT_1A(INIT['h1a*320+:320]), + .INIT_1B(INIT['h1b*320+:320]), + .INIT_1C(INIT['h1c*320+:320]), + .INIT_1D(INIT['h1d*320+:320]), + .INIT_1E(INIT['h1e*320+:320]), + .INIT_1F(INIT['h1f*320+:320]), + .INIT_20(INIT['h20*320+:320]), + .INIT_21(INIT['h21*320+:320]), + .INIT_22(INIT['h22*320+:320]), + .INIT_23(INIT['h23*320+:320]), + .INIT_24(INIT['h24*320+:320]), + .INIT_25(INIT['h25*320+:320]), + .INIT_26(INIT['h26*320+:320]), + .INIT_27(INIT['h27*320+:320]), + .INIT_28(INIT['h28*320+:320]), + .INIT_29(INIT['h29*320+:320]), + .INIT_2A(INIT['h2a*320+:320]), + .INIT_2B(INIT['h2b*320+:320]), + .INIT_2C(INIT['h2c*320+:320]), + .INIT_2D(INIT['h2d*320+:320]), + .INIT_2E(INIT['h2e*320+:320]), + .INIT_2F(INIT['h2f*320+:320]), + .INIT_30(INIT['h30*320+:320]), + .INIT_31(INIT['h31*320+:320]), + .INIT_32(INIT['h32*320+:320]), + .INIT_33(INIT['h33*320+:320]), + .INIT_34(INIT['h34*320+:320]), + .INIT_35(INIT['h35*320+:320]), + .INIT_36(INIT['h36*320+:320]), + .INIT_37(INIT['h37*320+:320]), + .INIT_38(INIT['h38*320+:320]), + .INIT_39(INIT['h39*320+:320]), + .INIT_3A(INIT['h3a*320+:320]), + .INIT_3B(INIT['h3b*320+:320]), + .INIT_3C(INIT['h3c*320+:320]), + .INIT_3D(INIT['h3d*320+:320]), + .INIT_3E(INIT['h3e*320+:320]), + .INIT_3F(INIT['h3f*320+:320]), + .INIT_40(INIT['h40*320+:320]), + .INIT_41(INIT['h41*320+:320]), + .INIT_42(INIT['h42*320+:320]), + .INIT_43(INIT['h43*320+:320]), + .INIT_44(INIT['h44*320+:320]), + .INIT_45(INIT['h45*320+:320]), + .INIT_46(INIT['h46*320+:320]), + .INIT_47(INIT['h47*320+:320]), + .INIT_48(INIT['h48*320+:320]), + .INIT_49(INIT['h49*320+:320]), + .INIT_4A(INIT['h4a*320+:320]), + .INIT_4B(INIT['h4b*320+:320]), + .INIT_4C(INIT['h4c*320+:320]), + .INIT_4D(INIT['h4d*320+:320]), + .INIT_4E(INIT['h4e*320+:320]), + .INIT_4F(INIT['h4f*320+:320]), + .INIT_50(INIT['h50*320+:320]), + .INIT_51(INIT['h51*320+:320]), + .INIT_52(INIT['h52*320+:320]), + .INIT_53(INIT['h53*320+:320]), + .INIT_54(INIT['h54*320+:320]), + .INIT_55(INIT['h55*320+:320]), + .INIT_56(INIT['h56*320+:320]), + .INIT_57(INIT['h57*320+:320]), + .INIT_58(INIT['h58*320+:320]), + .INIT_59(INIT['h59*320+:320]), + .INIT_5A(INIT['h5a*320+:320]), + .INIT_5B(INIT['h5b*320+:320]), + .INIT_5C(INIT['h5c*320+:320]), + .INIT_5D(INIT['h5d*320+:320]), + .INIT_5E(INIT['h5e*320+:320]), + .INIT_5F(INIT['h5f*320+:320]), + .INIT_60(INIT['h60*320+:320]), + .INIT_61(INIT['h61*320+:320]), + .INIT_62(INIT['h62*320+:320]), + .INIT_63(INIT['h63*320+:320]), + .INIT_64(INIT['h64*320+:320]), + .INIT_65(INIT['h65*320+:320]), + .INIT_66(INIT['h66*320+:320]), + .INIT_67(INIT['h67*320+:320]), + .INIT_68(INIT['h68*320+:320]), + .INIT_69(INIT['h69*320+:320]), + .INIT_6A(INIT['h6a*320+:320]), + .INIT_6B(INIT['h6b*320+:320]), + .INIT_6C(INIT['h6c*320+:320]), + .INIT_6D(INIT['h6d*320+:320]), + .INIT_6E(INIT['h6e*320+:320]), + .INIT_6F(INIT['h6f*320+:320]), + .INIT_70(INIT['h70*320+:320]), + .INIT_71(INIT['h71*320+:320]), + .INIT_72(INIT['h72*320+:320]), + .INIT_73(INIT['h73*320+:320]), + .INIT_74(INIT['h74*320+:320]), + .INIT_75(INIT['h75*320+:320]), + .INIT_76(INIT['h76*320+:320]), + .INIT_77(INIT['h77*320+:320]), + .INIT_78(INIT['h78*320+:320]), + .INIT_79(INIT['h79*320+:320]), + .INIT_7A(INIT['h7a*320+:320]), + .INIT_7B(INIT['h7b*320+:320]), + .INIT_7C(INIT['h7c*320+:320]), + .INIT_7D(INIT['h7d*320+:320]), + .INIT_7E(INIT['h7e*320+:320]), + .INIT_7F(INIT['h7f*320+:320]), + .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), + .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), + .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), + .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), + .RAM_MODE("TDP"), + .A_WR_MODE(PORT_A_OPTION_WR_MODE), + .B_WR_MODE(PORT_B_OPTION_WR_MODE), + .A_CLK_INV(!PORT_A_CLK_POL), + .B_CLK_INV(!PORT_B_CLK_POL), + .CAS("LOWER"), + ) lower ( + .A_CO(CAS_A), + .B_CO(CAS_B), + .A_CLK(PORT_A_CLK), + .A_EN(PORT_A_CLK_EN), + .A_WE(PORT_A_WR_EN), + .A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), + .A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), + .A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}), + .B_CLK(PORT_B_CLK), + .B_EN(PORT_B_CLK_EN), + .B_WE(PORT_B_WR_EN), + .B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), + .B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), + .B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}), + ); + CC_BRAM_40K #( + .INIT_00(INIT['h80*320+:320]), + .INIT_01(INIT['h81*320+:320]), + .INIT_02(INIT['h82*320+:320]), + .INIT_03(INIT['h83*320+:320]), + .INIT_04(INIT['h84*320+:320]), + .INIT_05(INIT['h85*320+:320]), + .INIT_06(INIT['h86*320+:320]), + .INIT_07(INIT['h87*320+:320]), + .INIT_08(INIT['h88*320+:320]), + .INIT_09(INIT['h89*320+:320]), + .INIT_0A(INIT['h8a*320+:320]), + .INIT_0B(INIT['h8b*320+:320]), + .INIT_0C(INIT['h8c*320+:320]), + .INIT_0D(INIT['h8d*320+:320]), + .INIT_0E(INIT['h8e*320+:320]), + .INIT_0F(INIT['h8f*320+:320]), + .INIT_10(INIT['h90*320+:320]), + .INIT_11(INIT['h91*320+:320]), + .INIT_12(INIT['h92*320+:320]), + .INIT_13(INIT['h93*320+:320]), + .INIT_14(INIT['h94*320+:320]), + .INIT_15(INIT['h95*320+:320]), + .INIT_16(INIT['h96*320+:320]), + .INIT_17(INIT['h97*320+:320]), + .INIT_18(INIT['h98*320+:320]), + .INIT_19(INIT['h99*320+:320]), + .INIT_1A(INIT['h9a*320+:320]), + .INIT_1B(INIT['h9b*320+:320]), + .INIT_1C(INIT['h9c*320+:320]), + .INIT_1D(INIT['h9d*320+:320]), + .INIT_1E(INIT['h9e*320+:320]), + .INIT_1F(INIT['h9f*320+:320]), + .INIT_20(INIT['ha0*320+:320]), + .INIT_21(INIT['ha1*320+:320]), + .INIT_22(INIT['ha2*320+:320]), + .INIT_23(INIT['ha3*320+:320]), + .INIT_24(INIT['ha4*320+:320]), + .INIT_25(INIT['ha5*320+:320]), + .INIT_26(INIT['ha6*320+:320]), + .INIT_27(INIT['ha7*320+:320]), + .INIT_28(INIT['ha8*320+:320]), + .INIT_29(INIT['ha9*320+:320]), + .INIT_2A(INIT['haa*320+:320]), + .INIT_2B(INIT['hab*320+:320]), + .INIT_2C(INIT['hac*320+:320]), + .INIT_2D(INIT['had*320+:320]), + .INIT_2E(INIT['hae*320+:320]), + .INIT_2F(INIT['haf*320+:320]), + .INIT_30(INIT['hb0*320+:320]), + .INIT_31(INIT['hb1*320+:320]), + .INIT_32(INIT['hb2*320+:320]), + .INIT_33(INIT['hb3*320+:320]), + .INIT_34(INIT['hb4*320+:320]), + .INIT_35(INIT['hb5*320+:320]), + .INIT_36(INIT['hb6*320+:320]), + .INIT_37(INIT['hb7*320+:320]), + .INIT_38(INIT['hb8*320+:320]), + .INIT_39(INIT['hb9*320+:320]), + .INIT_3A(INIT['hba*320+:320]), + .INIT_3B(INIT['hbb*320+:320]), + .INIT_3C(INIT['hbc*320+:320]), + .INIT_3D(INIT['hbd*320+:320]), + .INIT_3E(INIT['hbe*320+:320]), + .INIT_3F(INIT['hbf*320+:320]), + .INIT_40(INIT['hc0*320+:320]), + .INIT_41(INIT['hc1*320+:320]), + .INIT_42(INIT['hc2*320+:320]), + .INIT_43(INIT['hc3*320+:320]), + .INIT_44(INIT['hc4*320+:320]), + .INIT_45(INIT['hc5*320+:320]), + .INIT_46(INIT['hc6*320+:320]), + .INIT_47(INIT['hc7*320+:320]), + .INIT_48(INIT['hc8*320+:320]), + .INIT_49(INIT['hc9*320+:320]), + .INIT_4A(INIT['hca*320+:320]), + .INIT_4B(INIT['hcb*320+:320]), + .INIT_4C(INIT['hcc*320+:320]), + .INIT_4D(INIT['hcd*320+:320]), + .INIT_4E(INIT['hce*320+:320]), + .INIT_4F(INIT['hcf*320+:320]), + .INIT_50(INIT['hd0*320+:320]), + .INIT_51(INIT['hd1*320+:320]), + .INIT_52(INIT['hd2*320+:320]), + .INIT_53(INIT['hd3*320+:320]), + .INIT_54(INIT['hd4*320+:320]), + .INIT_55(INIT['hd5*320+:320]), + .INIT_56(INIT['hd6*320+:320]), + .INIT_57(INIT['hd7*320+:320]), + .INIT_58(INIT['hd8*320+:320]), + .INIT_59(INIT['hd9*320+:320]), + .INIT_5A(INIT['hda*320+:320]), + .INIT_5B(INIT['hdb*320+:320]), + .INIT_5C(INIT['hdc*320+:320]), + .INIT_5D(INIT['hdd*320+:320]), + .INIT_5E(INIT['hde*320+:320]), + .INIT_5F(INIT['hdf*320+:320]), + .INIT_60(INIT['he0*320+:320]), + .INIT_61(INIT['he1*320+:320]), + .INIT_62(INIT['he2*320+:320]), + .INIT_63(INIT['he3*320+:320]), + .INIT_64(INIT['he4*320+:320]), + .INIT_65(INIT['he5*320+:320]), + .INIT_66(INIT['he6*320+:320]), + .INIT_67(INIT['he7*320+:320]), + .INIT_68(INIT['he8*320+:320]), + .INIT_69(INIT['he9*320+:320]), + .INIT_6A(INIT['hea*320+:320]), + .INIT_6B(INIT['heb*320+:320]), + .INIT_6C(INIT['hec*320+:320]), + .INIT_6D(INIT['hed*320+:320]), + .INIT_6E(INIT['hee*320+:320]), + .INIT_6F(INIT['hef*320+:320]), + .INIT_70(INIT['hf0*320+:320]), + .INIT_71(INIT['hf1*320+:320]), + .INIT_72(INIT['hf2*320+:320]), + .INIT_73(INIT['hf3*320+:320]), + .INIT_74(INIT['hf4*320+:320]), + .INIT_75(INIT['hf5*320+:320]), + .INIT_76(INIT['hf6*320+:320]), + .INIT_77(INIT['hf7*320+:320]), + .INIT_78(INIT['hf8*320+:320]), + .INIT_79(INIT['hf9*320+:320]), + .INIT_7A(INIT['hfa*320+:320]), + .INIT_7B(INIT['hfb*320+:320]), + .INIT_7C(INIT['hfc*320+:320]), + .INIT_7D(INIT['hfd*320+:320]), + .INIT_7E(INIT['hfe*320+:320]), + .INIT_7F(INIT['hff*320+:320]), + .A_RD_WIDTH(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), + .A_WR_WIDTH(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), + .B_RD_WIDTH(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), + .B_WR_WIDTH(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), + .RAM_MODE("TDP"), + .A_WR_MODE(PORT_A_OPTION_WR_MODE), + .B_WR_MODE(PORT_B_OPTION_WR_MODE), + .A_CLK_INV(!PORT_A_CLK_POL), + .B_CLK_INV(!PORT_B_CLK_POL), + .CAS("UPPER"), + ) upper ( + .A_CI(CAS_A), + .B_CI(CAS_B), + .A_CLK(PORT_A_CLK), + .A_EN(PORT_A_CLK_EN), + .A_WE(PORT_A_WR_EN), + .A_BM({{(40-PORT_A_WR_BE_WIDTH){1'bx}}, PORT_A_WR_BE}), + .A_DI({{(40-PORT_A_WR_WIDTH){1'bx}}, PORT_A_WR_DATA}), + .A_DO(PORT_A_RD_DATA), + .A_ADDR({PORT_A_ADDR[14:0], PORT_A_ADDR[15]}), + .B_CLK(PORT_B_CLK), + .B_EN(PORT_B_CLK_EN), + .B_WE(PORT_B_WR_EN), + .B_BM({{(40-PORT_B_WR_BE_WIDTH){1'bx}}, PORT_B_WR_BE}), + .B_DI({{(40-PORT_B_WR_WIDTH){1'bx}}, PORT_B_WR_DATA}), + .B_DO(PORT_B_RD_DATA), + .B_ADDR({PORT_B_ADDR[14:0], PORT_B_ADDR[15]}), + ); + end +endgenerate + +endmodule + + +module $__CC_BRAM_SDP_(...); + +parameter INIT = 0; +parameter OPTION_MODE = "20K"; +parameter OPTION_WR_MODE = "NO_CHANGE"; + +parameter PORT_W_CLK_POL = 1; +parameter PORT_W_USED = 1; +parameter PORT_W_WIDTH = 40; +parameter PORT_W_WR_BE_WIDTH = 40; + +parameter PORT_R_CLK_POL = 1; +parameter PORT_R_USED = 1; +parameter PORT_R_WIDTH = 40; + +input PORT_W_CLK; +input PORT_W_CLK_EN; +input PORT_W_WR_EN; +input [15:0] PORT_W_ADDR; +input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE; +input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA; + +input PORT_R_CLK; +input PORT_R_CLK_EN; +input [15:0] PORT_R_ADDR; +output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA; + +generate + if (OPTION_MODE == "20K") begin + CC_BRAM_20K #( + .INIT_00(INIT['h00*320+:320]), + .INIT_01(INIT['h01*320+:320]), + .INIT_02(INIT['h02*320+:320]), + .INIT_03(INIT['h03*320+:320]), + .INIT_04(INIT['h04*320+:320]), + .INIT_05(INIT['h05*320+:320]), + .INIT_06(INIT['h06*320+:320]), + .INIT_07(INIT['h07*320+:320]), + .INIT_08(INIT['h08*320+:320]), + .INIT_09(INIT['h09*320+:320]), + .INIT_0A(INIT['h0a*320+:320]), + .INIT_0B(INIT['h0b*320+:320]), + .INIT_0C(INIT['h0c*320+:320]), + .INIT_0D(INIT['h0d*320+:320]), + .INIT_0E(INIT['h0e*320+:320]), + .INIT_0F(INIT['h0f*320+:320]), + .INIT_10(INIT['h10*320+:320]), + .INIT_11(INIT['h11*320+:320]), + .INIT_12(INIT['h12*320+:320]), + .INIT_13(INIT['h13*320+:320]), + .INIT_14(INIT['h14*320+:320]), + .INIT_15(INIT['h15*320+:320]), + .INIT_16(INIT['h16*320+:320]), + .INIT_17(INIT['h17*320+:320]), + .INIT_18(INIT['h18*320+:320]), + .INIT_19(INIT['h19*320+:320]), + .INIT_1A(INIT['h1a*320+:320]), + .INIT_1B(INIT['h1b*320+:320]), + .INIT_1C(INIT['h1c*320+:320]), + .INIT_1D(INIT['h1d*320+:320]), + .INIT_1E(INIT['h1e*320+:320]), + .INIT_1F(INIT['h1f*320+:320]), + .INIT_20(INIT['h20*320+:320]), + .INIT_21(INIT['h21*320+:320]), + .INIT_22(INIT['h22*320+:320]), + .INIT_23(INIT['h23*320+:320]), + .INIT_24(INIT['h24*320+:320]), + .INIT_25(INIT['h25*320+:320]), + .INIT_26(INIT['h26*320+:320]), + .INIT_27(INIT['h27*320+:320]), + .INIT_28(INIT['h28*320+:320]), + .INIT_29(INIT['h29*320+:320]), + .INIT_2A(INIT['h2a*320+:320]), + .INIT_2B(INIT['h2b*320+:320]), + .INIT_2C(INIT['h2c*320+:320]), + .INIT_2D(INIT['h2d*320+:320]), + .INIT_2E(INIT['h2e*320+:320]), + .INIT_2F(INIT['h2f*320+:320]), + .INIT_30(INIT['h30*320+:320]), + .INIT_31(INIT['h31*320+:320]), + .INIT_32(INIT['h32*320+:320]), + .INIT_33(INIT['h33*320+:320]), + .INIT_34(INIT['h34*320+:320]), + .INIT_35(INIT['h35*320+:320]), + .INIT_36(INIT['h36*320+:320]), + .INIT_37(INIT['h37*320+:320]), + .INIT_38(INIT['h38*320+:320]), + .INIT_39(INIT['h39*320+:320]), + .INIT_3A(INIT['h3a*320+:320]), + .INIT_3B(INIT['h3b*320+:320]), + .INIT_3C(INIT['h3c*320+:320]), + .INIT_3D(INIT['h3d*320+:320]), + .INIT_3E(INIT['h3e*320+:320]), + .INIT_3F(INIT['h3f*320+:320]), + .A_RD_WIDTH(0), + .A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0), + .B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0), + .B_WR_WIDTH(0), + .RAM_MODE("SDP"), + .A_WR_MODE(OPTION_WR_MODE), + .B_WR_MODE(OPTION_WR_MODE), + .A_CLK_INV(!PORT_W_CLK_POL), + .B_CLK_INV(!PORT_R_CLK_POL), + ) _TECHMAP_REPLACE_ ( + .A_CLK(PORT_W_CLK), + .A_EN(PORT_W_CLK_EN), + .A_WE(PORT_W_WR_EN), + .A_BM(PORT_W_WR_BE[19:0]), + .B_BM({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[39:20]}), + .A_DI(PORT_W_WR_DATA[19:0]), + .B_DI({{(40-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[39:20]}), + .A_ADDR({PORT_W_ADDR[13:5], 1'b0, PORT_W_ADDR[4:0], 1'b0}), + .B_CLK(PORT_R_CLK), + .B_EN(PORT_R_CLK_EN), + .B_WE(1'b0), + .B_ADDR({PORT_R_ADDR[13:5], 1'b0, PORT_R_ADDR[4:0], 1'b0}), + .A_DO(PORT_R_RD_DATA[19:0]), + .B_DO(PORT_R_RD_DATA[39:20]), + ); + end else if (OPTION_MODE == "40K") begin + CC_BRAM_40K #( + .INIT_00(INIT['h00*320+:320]), + .INIT_01(INIT['h01*320+:320]), + .INIT_02(INIT['h02*320+:320]), + .INIT_03(INIT['h03*320+:320]), + .INIT_04(INIT['h04*320+:320]), + .INIT_05(INIT['h05*320+:320]), + .INIT_06(INIT['h06*320+:320]), + .INIT_07(INIT['h07*320+:320]), + .INIT_08(INIT['h08*320+:320]), + .INIT_09(INIT['h09*320+:320]), + .INIT_0A(INIT['h0a*320+:320]), + .INIT_0B(INIT['h0b*320+:320]), + .INIT_0C(INIT['h0c*320+:320]), + .INIT_0D(INIT['h0d*320+:320]), + .INIT_0E(INIT['h0e*320+:320]), + .INIT_0F(INIT['h0f*320+:320]), + .INIT_10(INIT['h10*320+:320]), + .INIT_11(INIT['h11*320+:320]), + .INIT_12(INIT['h12*320+:320]), + .INIT_13(INIT['h13*320+:320]), + .INIT_14(INIT['h14*320+:320]), + .INIT_15(INIT['h15*320+:320]), + .INIT_16(INIT['h16*320+:320]), + .INIT_17(INIT['h17*320+:320]), + .INIT_18(INIT['h18*320+:320]), + .INIT_19(INIT['h19*320+:320]), + .INIT_1A(INIT['h1a*320+:320]), + .INIT_1B(INIT['h1b*320+:320]), + .INIT_1C(INIT['h1c*320+:320]), + .INIT_1D(INIT['h1d*320+:320]), + .INIT_1E(INIT['h1e*320+:320]), + .INIT_1F(INIT['h1f*320+:320]), + .INIT_20(INIT['h20*320+:320]), + .INIT_21(INIT['h21*320+:320]), + .INIT_22(INIT['h22*320+:320]), + .INIT_23(INIT['h23*320+:320]), + .INIT_24(INIT['h24*320+:320]), + .INIT_25(INIT['h25*320+:320]), + .INIT_26(INIT['h26*320+:320]), + .INIT_27(INIT['h27*320+:320]), + .INIT_28(INIT['h28*320+:320]), + .INIT_29(INIT['h29*320+:320]), + .INIT_2A(INIT['h2a*320+:320]), + .INIT_2B(INIT['h2b*320+:320]), + .INIT_2C(INIT['h2c*320+:320]), + .INIT_2D(INIT['h2d*320+:320]), + .INIT_2E(INIT['h2e*320+:320]), + .INIT_2F(INIT['h2f*320+:320]), + .INIT_30(INIT['h30*320+:320]), + .INIT_31(INIT['h31*320+:320]), + .INIT_32(INIT['h32*320+:320]), + .INIT_33(INIT['h33*320+:320]), + .INIT_34(INIT['h34*320+:320]), + .INIT_35(INIT['h35*320+:320]), + .INIT_36(INIT['h36*320+:320]), + .INIT_37(INIT['h37*320+:320]), + .INIT_38(INIT['h38*320+:320]), + .INIT_39(INIT['h39*320+:320]), + .INIT_3A(INIT['h3a*320+:320]), + .INIT_3B(INIT['h3b*320+:320]), + .INIT_3C(INIT['h3c*320+:320]), + .INIT_3D(INIT['h3d*320+:320]), + .INIT_3E(INIT['h3e*320+:320]), + .INIT_3F(INIT['h3f*320+:320]), + .INIT_40(INIT['h40*320+:320]), + .INIT_41(INIT['h41*320+:320]), + .INIT_42(INIT['h42*320+:320]), + .INIT_43(INIT['h43*320+:320]), + .INIT_44(INIT['h44*320+:320]), + .INIT_45(INIT['h45*320+:320]), + .INIT_46(INIT['h46*320+:320]), + .INIT_47(INIT['h47*320+:320]), + .INIT_48(INIT['h48*320+:320]), + .INIT_49(INIT['h49*320+:320]), + .INIT_4A(INIT['h4a*320+:320]), + .INIT_4B(INIT['h4b*320+:320]), + .INIT_4C(INIT['h4c*320+:320]), + .INIT_4D(INIT['h4d*320+:320]), + .INIT_4E(INIT['h4e*320+:320]), + .INIT_4F(INIT['h4f*320+:320]), + .INIT_50(INIT['h50*320+:320]), + .INIT_51(INIT['h51*320+:320]), + .INIT_52(INIT['h52*320+:320]), + .INIT_53(INIT['h53*320+:320]), + .INIT_54(INIT['h54*320+:320]), + .INIT_55(INIT['h55*320+:320]), + .INIT_56(INIT['h56*320+:320]), + .INIT_57(INIT['h57*320+:320]), + .INIT_58(INIT['h58*320+:320]), + .INIT_59(INIT['h59*320+:320]), + .INIT_5A(INIT['h5a*320+:320]), + .INIT_5B(INIT['h5b*320+:320]), + .INIT_5C(INIT['h5c*320+:320]), + .INIT_5D(INIT['h5d*320+:320]), + .INIT_5E(INIT['h5e*320+:320]), + .INIT_5F(INIT['h5f*320+:320]), + .INIT_60(INIT['h60*320+:320]), + .INIT_61(INIT['h61*320+:320]), + .INIT_62(INIT['h62*320+:320]), + .INIT_63(INIT['h63*320+:320]), + .INIT_64(INIT['h64*320+:320]), + .INIT_65(INIT['h65*320+:320]), + .INIT_66(INIT['h66*320+:320]), + .INIT_67(INIT['h67*320+:320]), + .INIT_68(INIT['h68*320+:320]), + .INIT_69(INIT['h69*320+:320]), + .INIT_6A(INIT['h6a*320+:320]), + .INIT_6B(INIT['h6b*320+:320]), + .INIT_6C(INIT['h6c*320+:320]), + .INIT_6D(INIT['h6d*320+:320]), + .INIT_6E(INIT['h6e*320+:320]), + .INIT_6F(INIT['h6f*320+:320]), + .INIT_70(INIT['h70*320+:320]), + .INIT_71(INIT['h71*320+:320]), + .INIT_72(INIT['h72*320+:320]), + .INIT_73(INIT['h73*320+:320]), + .INIT_74(INIT['h74*320+:320]), + .INIT_75(INIT['h75*320+:320]), + .INIT_76(INIT['h76*320+:320]), + .INIT_77(INIT['h77*320+:320]), + .INIT_78(INIT['h78*320+:320]), + .INIT_79(INIT['h79*320+:320]), + .INIT_7A(INIT['h7a*320+:320]), + .INIT_7B(INIT['h7b*320+:320]), + .INIT_7C(INIT['h7c*320+:320]), + .INIT_7D(INIT['h7d*320+:320]), + .INIT_7E(INIT['h7e*320+:320]), + .INIT_7F(INIT['h7f*320+:320]), + .A_RD_WIDTH(0), + .A_WR_WIDTH(PORT_W_USED ? PORT_W_WIDTH : 0), + .B_RD_WIDTH(PORT_R_USED ? PORT_R_WIDTH : 0), + .B_WR_WIDTH(0), + .RAM_MODE("SDP"), + .A_WR_MODE(OPTION_WR_MODE), + .B_WR_MODE(OPTION_WR_MODE), + .A_CLK_INV(!PORT_W_CLK_POL), + .B_CLK_INV(!PORT_R_CLK_POL), + ) _TECHMAP_REPLACE_ ( + .A_CLK(PORT_W_CLK), + .A_EN(PORT_W_CLK_EN), + .A_WE(PORT_W_WR_EN), + .A_BM(PORT_W_WR_BE[39:0]), + .B_BM({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_BE[79:40]}), + .A_DI(PORT_W_WR_DATA[39:0]), + .B_DI({{(80-PORT_W_WIDTH){1'bx}}, PORT_W_WR_DATA[79:40]}), + .A_ADDR({PORT_W_ADDR[14:0], 1'b0}), + .B_CLK(PORT_R_CLK), + .B_EN(PORT_R_CLK_EN), + .B_WE(1'b0), + .B_ADDR({PORT_R_ADDR[14:0], 1'b0}), + .A_DO(PORT_R_RD_DATA[39:0]), + .B_DO(PORT_R_RD_DATA[79:40]), + ); + end +endgenerate + +endmodule diff --git a/techlibs/gatemate/cells_bb.v b/techlibs/gatemate/cells_bb.v index 63629c836..dacda4c86 100644 --- a/techlibs/gatemate/cells_bb.v +++ b/techlibs/gatemate/cells_bb.v @@ -1,340 +1,340 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -(* blackbox *) -module CC_PLL #( - parameter REF_CLK = "", // e.g. "10.0" - parameter OUT_CLK = "", // e.g. "50.0" - parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED - parameter LOCK_REQ = 1, - parameter CLK270_DOUB = 0, - parameter CLK180_DOUB = 0, - parameter LOW_JITTER = 1, - parameter CI_FILTER_CONST = 2, - parameter CP_FILTER_CONST = 4 -)( - input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, - input USR_LOCKED_STDY_RST, - output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, - output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT -); -endmodule - -(* blackbox *) -module CC_PLL_ADV #( - parameter [95:0] PLL_CFG_A = 96'bx, - parameter [95:0] PLL_CFG_B = 96'bx -)( - input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, - input USR_LOCKED_STDY_RST, USR_SEL_A_B, - output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, - output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT -); -endmodule - -(* blackbox *) (* keep *) -module CC_SERDES #( - parameter [4:0] RX_BUF_RESET_TIME = 3, - parameter [4:0] RX_PCS_RESET_TIME = 3, - parameter [4:0] RX_RESET_TIMER_PRESC = 0, - parameter [0:0] RX_RESET_DONE_GATE = 0, - parameter [4:0] RX_CDR_RESET_TIME = 3, - parameter [4:0] RX_EQA_RESET_TIME = 3, - parameter [4:0] RX_PMA_RESET_TIME = 3, - parameter [0:0] RX_WAIT_CDR_LOCK = 1, - parameter [0:0] RX_CALIB_EN = 0, - parameter [0:0] RX_CALIB_OVR = 0, - parameter [3:0] RX_CALIB_VAL = 0, - parameter [2:0] RX_RTERM_VCMSEL = 4, - parameter [0:0] RX_RTERM_PD = 0, - parameter [7:0] RX_EQA_CKP_LF = 8'hA3, - parameter [7:0] RX_EQA_CKP_HF = 8'hA3, - parameter [7:0] RX_EQA_CKP_OFFSET = 8'h01, - parameter [0:0] RX_EN_EQA = 0, - parameter [3:0] RX_EQA_LOCK_CFG = 0, - parameter [4:0] RX_TH_MON1 = 8, - parameter [3:0] RX_EN_EQA_EXT_VALUE = 0, - parameter [4:0] RX_TH_MON2 = 8, - parameter [4:0] RX_TAPW = 8, - parameter [4:0] RX_AFE_OFFSET = 8, - parameter [15:0] RX_EQA_CONFIG = 16'h01C0, - parameter [4:0] RX_AFE_PEAK = 16, - parameter [3:0] RX_AFE_GAIN = 8, - parameter [2:0] RX_AFE_VCMSEL = 4, - parameter [7:0] RX_CDR_CKP = 8'hF8, - parameter [7:0] RX_CDR_CKI = 0, - parameter [6:0] RX_CDR_TRANS_TH = 7'h08, - parameter [7:0] RX_CDR_LOCK_CFG = 8'hD5, - parameter [14:0] RX_CDR_FREQ_ACC = 0, - parameter [15:0] RX_CDR_PHASE_ACC = 0, - parameter [1:0] RX_CDR_SET_ACC_CONFIG = 0, - parameter [0:0] RX_CDR_FORCE_LOCK = 0, - parameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283, - parameter [0:0] RX_MCOMMA_ALIGN_OVR = 0, - parameter [0:0] RX_MCOMMA_ALIGN = 0, - parameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C, - parameter [0:0] RX_PCOMMA_ALIGN_OVR = 0, - parameter [0:0] RX_PCOMMA_ALIGN = 0, - parameter [1:0] RX_ALIGN_COMMA_WORD = 0, - parameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF, - parameter [1:0] RX_SLIDE_MODE = 0, - parameter [0:0] RX_COMMA_DETECT_EN_OVR = 0, - parameter [0:0] RX_COMMA_DETECT_EN = 0, - parameter [1:0] RX_SLIDE = 0, - parameter [0:0] RX_EYE_MEAS_EN = 0, - parameter [14:0] RX_EYE_MEAS_CFG = 0, - parameter [5:0] RX_MON_PH_OFFSET = 0, - parameter [3:0] RX_EI_BIAS = 0, - parameter [3:0] RX_EI_BW_SEL = 4, - parameter [0:0] RX_EN_EI_DETECTOR_OVR = 0, - parameter [0:0] RX_EN_EI_DETECTOR = 0, - parameter [0:0] RX_DATA_SEL = 0, - parameter [0:0] RX_BUF_BYPASS = 0, - parameter [0:0] RX_CLKCOR_USE = 0, - parameter [5:0] RX_CLKCOR_MIN_LAT = 32, - parameter [5:0] RX_CLKCOR_MAX_LAT = 39, - parameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7, - parameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7, - parameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7, - parameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7, - parameter [0:0] RX_PMA_LOOPBACK = 0, - parameter [0:0] RX_PCS_LOOPBACK = 0, - parameter [1:0] RX_DATAPATH_SEL = 3, - parameter [0:0] RX_PRBS_OVR = 0, - parameter [2:0] RX_PRBS_SEL = 0, - parameter [0:0] RX_LOOPBACK_OVR = 0, - parameter [0:0] RX_PRBS_CNT_RESET = 0, - parameter [0:0] RX_POWER_DOWN_OVR = 0, - parameter [0:0] RX_POWER_DOWN_N = 0, - parameter [0:0] RX_RESET_OVR = 0, - parameter [0:0] RX_RESET = 0, - parameter [0:0] RX_PMA_RESET_OVR = 0, - parameter [0:0] RX_PMA_RESET = 0, - parameter [0:0] RX_EQA_RESET_OVR = 0, - parameter [0:0] RX_EQA_RESET = 0, - parameter [0:0] RX_CDR_RESET_OVR = 0, - parameter [0:0] RX_CDR_RESET = 0, - parameter [0:0] RX_PCS_RESET_OVR = 0, - parameter [0:0] RX_PCS_RESET = 0, - parameter [0:0] RX_BUF_RESET_OVR = 0, - parameter [0:0] RX_BUF_RESET = 0, - parameter [0:0] RX_POLARITY_OVR = 0, - parameter [0:0] RX_POLARITY = 0, - parameter [0:0] RX_8B10B_EN_OVR = 0, - parameter [0:0] RX_8B10B_EN = 0, - parameter [7:0] RX_8B10B_BYPASS = 0, - parameter [0:0] RX_BYTE_REALIGN = 0, - parameter [0:0] RX_DBG_EN = 0, - parameter [1:0] RX_DBG_SEL = 0, - parameter [0:0] RX_DBG_MODE = 0, - parameter [5:0] RX_DBG_SRAM_DELAY = 6'h05, - parameter [9:0] RX_DBG_ADDR = 0, - parameter [0:0] RX_DBG_RE = 0, - parameter [0:0] RX_DBG_WE = 0, - parameter [19:0] RX_DBG_DATA = 0, - parameter [4:0] TX_SEL_PRE = 0, - parameter [4:0] TX_SEL_POST = 0, - parameter [4:0] TX_AMP = 15, - parameter [4:0] TX_BRANCH_EN_PRE = 0, - parameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F, - parameter [4:0] TX_BRANCH_EN_POST = 0, - parameter [2:0] TX_TAIL_CASCODE = 4, - parameter [6:0] TX_DC_ENABLE = 63, - parameter [4:0] TX_DC_OFFSET = 0, - parameter [4:0] TX_CM_RAISE = 0, - parameter [4:0] TX_CM_THRESHOLD_0 = 14, - parameter [4:0] TX_CM_THRESHOLD_1 = 16, - parameter [4:0] TX_SEL_PRE_EI = 0, - parameter [4:0] TX_SEL_POST_EI = 0, - parameter [4:0] TX_AMP_EI = 15, - parameter [4:0] TX_BRANCH_EN_PRE_EI = 0, - parameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F, - parameter [4:0] TX_BRANCH_EN_POST_EI = 0, - parameter [2:0] TX_TAIL_CASCODE_EI = 4, - parameter [6:0] TX_DC_ENABLE_EI = 63, - parameter [4:0] TX_DC_OFFSET_EI = 0, - parameter [4:0] TX_CM_RAISE_EI = 0, - parameter [4:0] TX_CM_THRESHOLD_0_EI = 14, - parameter [4:0] TX_CM_THRESHOLD_1_EI = 16, - parameter [4:0] TX_SEL_PRE_RXDET = 0, - parameter [4:0] TX_SEL_POST_RXDET = 0, - parameter [4:0] TX_AMP_RXDET = 15, - parameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0, - parameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F, - parameter [4:0] TX_BRANCH_EN_POST_RXDET = 0, - parameter [2:0] TX_TAIL_CASCODE_RXDET = 4, - parameter [6:0] TX_DC_ENABLE_RXDET = 63, - parameter [4:0] TX_DC_OFFSET_RXDET = 0, - parameter [4:0] TX_CM_RAISE_RXDET = 0, - parameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14, - parameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16, - parameter [0:0] TX_CALIB_EN = 0, - parameter [0:0] TX_CALIB_OVR = 0, - parameter [3:0] TX_CALIB_VAL = 0, - parameter [7:0] TX_CM_REG_KI = 8'h80, - parameter [0:0] TX_CM_SAR_EN = 0, - parameter [0:0] TX_CM_REG_EN = 1, - parameter [4:0] TX_PMA_RESET_TIME = 3, - parameter [4:0] TX_PCS_RESET_TIME = 3, - parameter [0:0] TX_PCS_RESET_OVR = 0, - parameter [0:0] TX_PCS_RESET = 0, - parameter [0:0] TX_PMA_RESET_OVR = 0, - parameter [0:0] TX_PMA_RESET = 0, - parameter [0:0] TX_RESET_OVR = 0, - parameter [0:0] TX_RESET = 0, - parameter [1:0] TX_PMA_LOOPBACK = 0, - parameter [0:0] TX_PCS_LOOPBACK = 0, - parameter [1:0] TX_DATAPATH_SEL = 3, - parameter [0:0] TX_PRBS_OVR = 0, - parameter [2:0] TX_PRBS_SEL = 0, - parameter [0:0] TX_PRBS_FORCE_ERR = 0, - parameter [0:0] TX_LOOPBACK_OVR = 0, - parameter [0:0] TX_POWER_DOWN_OVR = 0, - parameter [0:0] TX_POWER_DOWN_N = 0, - parameter [0:0] TX_ELEC_IDLE_OVR = 0, - parameter [0:0] TX_ELEC_IDLE = 0, - parameter [0:0] TX_DETECT_RX_OVR = 0, - parameter [0:0] TX_DETECT_RX = 0, - parameter [0:0] TX_POLARITY_OVR = 0, - parameter [0:0] TX_POLARITY = 0, - parameter [0:0] TX_8B10B_EN_OVR = 0, - parameter [0:0] TX_8B10B_EN = 0, - parameter [0:0] TX_DATA_OVR = 0, - parameter [2:0] TX_DATA_CNT = 0, - parameter [0:0] TX_DATA_VALID = 0, - parameter [0:0] PLL_EN_ADPLL_CTRL = 0, - parameter [0:0] PLL_CONFIG_SEL = 0, - parameter [0:0] PLL_SET_OP_LOCK = 0, - parameter [0:0] PLL_ENFORCE_LOCK = 0, - parameter [0:0] PLL_DISABLE_LOCK = 0, - parameter [0:0] PLL_LOCK_WINDOW = 1, - parameter [0:0] PLL_FAST_LOCK = 1, - parameter [0:0] PLL_SYNC_BYPASS = 0, - parameter [0:0] PLL_PFD_SELECT = 0, - parameter [0:0] PLL_REF_BYPASS = 0, - parameter [0:0] PLL_REF_SEL = 0, - parameter [0:0] PLL_REF_RTERM = 1, - parameter [5:0] PLL_FCNTRL = 58, - parameter [5:0] PLL_MAIN_DIVSEL = 27, - parameter [1:0] PLL_OUT_DIVSEL = 0, - parameter [4:0] PLL_CI = 3, - parameter [9:0] PLL_CP = 80, - parameter [3:0] PLL_AO = 0, - parameter [2:0] PLL_SCAP = 0, - parameter [1:0] PLL_FILTER_SHIFT = 2, - parameter [2:0] PLL_SAR_LIMIT = 2, - parameter [10:0] PLL_FT = 512, - parameter [0:0] PLL_OPEN_LOOP = 0, - parameter [0:0] PLL_SCAP_AUTO_CAL = 1, - parameter [2:0] PLL_BISC_MODE = 4, - parameter [3:0] PLL_BISC_TIMER_MAX = 15, - parameter [0:0] PLL_BISC_OPT_DET_IND = 0, - parameter [0:0] PLL_BISC_PFD_SEL = 0, - parameter [0:0] PLL_BISC_DLY_DIR = 0, - parameter [2:0] PLL_BISC_COR_DLY = 1, - parameter [0:0] PLL_BISC_CAL_SIGN = 0, - parameter [0:0] PLL_BISC_CAL_AUTO = 1, - parameter [4:0] PLL_BISC_CP_MIN = 4, - parameter [4:0] PLL_BISC_CP_MAX = 18, - parameter [4:0] PLL_BISC_CP_START = 12, - parameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0, - parameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2, - parameter [0:0] SERDES_ENABLE = 0, - parameter [0:0] SERDES_AUTO_INIT = 0, - parameter [0:0] SERDES_TESTMODE = 0 -)( - input [63:0] TX_DATA_I, - input TX_RESET_I, - input TX_PCS_RESET_I, - input TX_PMA_RESET_I, - input PLL_RESET_I, - input TX_POWER_DOWN_N_I, - input TX_POLARITY_I, - input [2:0] TX_PRBS_SEL_I, - input TX_PRBS_FORCE_ERR_I, - input TX_8B10B_EN_I, - input [7:0] TX_8B10B_BYPASS_I, - input [7:0] TX_CHAR_IS_K_I, - input [7:0] TX_CHAR_DISPMODE_I, - input [7:0] TX_CHAR_DISPVAL_I, - input TX_ELEC_IDLE_I, - input TX_DETECT_RX_I, - input [2:0] LOOPBACK_I, - input TX_CLK_I, - input RX_CLK_I, - input RX_RESET_I, - input RX_PMA_RESET_I, - input RX_EQA_RESET_I, - input RX_CDR_RESET_I, - input RX_PCS_RESET_I, - input RX_BUF_RESET_I, - input RX_POWER_DOWN_N_I, - input RX_POLARITY_I, - input [2:0] RX_PRBS_SEL_I, - input RX_PRBS_CNT_RESET_I, - input RX_8B10B_EN_I, - input [7:0] RX_8B10B_BYPASS_I, - input RX_EN_EI_DETECTOR_I, - input RX_COMMA_DETECT_EN_I, - input RX_SLIDE_I, - input RX_MCOMMA_ALIGN_I, - input RX_PCOMMA_ALIGN_I, - input REGFILE_CLK_I, - input REGFILE_WE_I, - input REGFILE_EN_I, - input [7:0] REGFILE_ADDR_I, - input [15:0] REGFILE_DI_I, - input [15:0] REGFILE_MASK_I, - output [63:0] RX_DATA_O, - output [7:0] RX_NOT_IN_TABLE_O, - output [7:0] RX_CHAR_IS_COMMA_O, - output [7:0] RX_CHAR_IS_K_O, - output [7:0] RX_DISP_ERR_O, - output TX_DETECT_RX_DONE_O, - output TX_DETECT_RX_PRESENT_O, - output TX_BUF_ERR_O, - output TX_RESET_DONE_O, - output RX_PRBS_ERR_O, - output RX_BUF_ERR_O, - output RX_BYTE_IS_ALIGNED_O, - output RX_BYTE_REALIGN_O, - output RX_RESET_DONE_O, - output RX_EI_EN_O, - output RX_CLK_O, - output PLL_CLK_O, - output [15:0] REGFILE_DO_O, - output REGFILE_RDY_O -); -endmodule - -(* blackbox *) (* keep *) -module CC_CFG_CTRL( - input [7:0] DATA, - input CLK, - input EN, - input RECFG, - input VALID -); -endmodule - -(* blackbox *) (* keep *) -module CC_USR_RSTN ( - output USR_RSTN -); -endmodule +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* blackbox *) +module CC_PLL #( + parameter REF_CLK = "", // e.g. "10.0" + parameter OUT_CLK = "", // e.g. "50.0" + parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED + parameter LOCK_REQ = 1, + parameter CLK270_DOUB = 0, + parameter CLK180_DOUB = 0, + parameter LOW_JITTER = 1, + parameter CI_FILTER_CONST = 2, + parameter CP_FILTER_CONST = 4 +)( + input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, + input USR_LOCKED_STDY_RST, + output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, + output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT +); +endmodule + +(* blackbox *) +module CC_PLL_ADV #( + parameter [95:0] PLL_CFG_A = 96'bx, + parameter [95:0] PLL_CFG_B = 96'bx +)( + input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, + input USR_LOCKED_STDY_RST, USR_SEL_A_B, + output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, + output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT +); +endmodule + +(* blackbox *) (* keep *) +module CC_SERDES #( + parameter [4:0] RX_BUF_RESET_TIME = 3, + parameter [4:0] RX_PCS_RESET_TIME = 3, + parameter [4:0] RX_RESET_TIMER_PRESC = 0, + parameter [0:0] RX_RESET_DONE_GATE = 0, + parameter [4:0] RX_CDR_RESET_TIME = 3, + parameter [4:0] RX_EQA_RESET_TIME = 3, + parameter [4:0] RX_PMA_RESET_TIME = 3, + parameter [0:0] RX_WAIT_CDR_LOCK = 1, + parameter [0:0] RX_CALIB_EN = 0, + parameter [0:0] RX_CALIB_OVR = 0, + parameter [3:0] RX_CALIB_VAL = 0, + parameter [2:0] RX_RTERM_VCMSEL = 4, + parameter [0:0] RX_RTERM_PD = 0, + parameter [7:0] RX_EQA_CKP_LF = 8'hA3, + parameter [7:0] RX_EQA_CKP_HF = 8'hA3, + parameter [7:0] RX_EQA_CKP_OFFSET = 8'h01, + parameter [0:0] RX_EN_EQA = 0, + parameter [3:0] RX_EQA_LOCK_CFG = 0, + parameter [4:0] RX_TH_MON1 = 8, + parameter [3:0] RX_EN_EQA_EXT_VALUE = 0, + parameter [4:0] RX_TH_MON2 = 8, + parameter [4:0] RX_TAPW = 8, + parameter [4:0] RX_AFE_OFFSET = 8, + parameter [15:0] RX_EQA_CONFIG = 16'h01C0, + parameter [4:0] RX_AFE_PEAK = 16, + parameter [3:0] RX_AFE_GAIN = 8, + parameter [2:0] RX_AFE_VCMSEL = 4, + parameter [7:0] RX_CDR_CKP = 8'hF8, + parameter [7:0] RX_CDR_CKI = 0, + parameter [6:0] RX_CDR_TRANS_TH = 7'h08, + parameter [7:0] RX_CDR_LOCK_CFG = 8'hD5, + parameter [14:0] RX_CDR_FREQ_ACC = 0, + parameter [15:0] RX_CDR_PHASE_ACC = 0, + parameter [1:0] RX_CDR_SET_ACC_CONFIG = 0, + parameter [0:0] RX_CDR_FORCE_LOCK = 0, + parameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283, + parameter [0:0] RX_MCOMMA_ALIGN_OVR = 0, + parameter [0:0] RX_MCOMMA_ALIGN = 0, + parameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C, + parameter [0:0] RX_PCOMMA_ALIGN_OVR = 0, + parameter [0:0] RX_PCOMMA_ALIGN = 0, + parameter [1:0] RX_ALIGN_COMMA_WORD = 0, + parameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF, + parameter [1:0] RX_SLIDE_MODE = 0, + parameter [0:0] RX_COMMA_DETECT_EN_OVR = 0, + parameter [0:0] RX_COMMA_DETECT_EN = 0, + parameter [1:0] RX_SLIDE = 0, + parameter [0:0] RX_EYE_MEAS_EN = 0, + parameter [14:0] RX_EYE_MEAS_CFG = 0, + parameter [5:0] RX_MON_PH_OFFSET = 0, + parameter [3:0] RX_EI_BIAS = 0, + parameter [3:0] RX_EI_BW_SEL = 4, + parameter [0:0] RX_EN_EI_DETECTOR_OVR = 0, + parameter [0:0] RX_EN_EI_DETECTOR = 0, + parameter [0:0] RX_DATA_SEL = 0, + parameter [0:0] RX_BUF_BYPASS = 0, + parameter [0:0] RX_CLKCOR_USE = 0, + parameter [5:0] RX_CLKCOR_MIN_LAT = 32, + parameter [5:0] RX_CLKCOR_MAX_LAT = 39, + parameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7, + parameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7, + parameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7, + parameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7, + parameter [0:0] RX_PMA_LOOPBACK = 0, + parameter [0:0] RX_PCS_LOOPBACK = 0, + parameter [1:0] RX_DATAPATH_SEL = 3, + parameter [0:0] RX_PRBS_OVR = 0, + parameter [2:0] RX_PRBS_SEL = 0, + parameter [0:0] RX_LOOPBACK_OVR = 0, + parameter [0:0] RX_PRBS_CNT_RESET = 0, + parameter [0:0] RX_POWER_DOWN_OVR = 0, + parameter [0:0] RX_POWER_DOWN_N = 0, + parameter [0:0] RX_RESET_OVR = 0, + parameter [0:0] RX_RESET = 0, + parameter [0:0] RX_PMA_RESET_OVR = 0, + parameter [0:0] RX_PMA_RESET = 0, + parameter [0:0] RX_EQA_RESET_OVR = 0, + parameter [0:0] RX_EQA_RESET = 0, + parameter [0:0] RX_CDR_RESET_OVR = 0, + parameter [0:0] RX_CDR_RESET = 0, + parameter [0:0] RX_PCS_RESET_OVR = 0, + parameter [0:0] RX_PCS_RESET = 0, + parameter [0:0] RX_BUF_RESET_OVR = 0, + parameter [0:0] RX_BUF_RESET = 0, + parameter [0:0] RX_POLARITY_OVR = 0, + parameter [0:0] RX_POLARITY = 0, + parameter [0:0] RX_8B10B_EN_OVR = 0, + parameter [0:0] RX_8B10B_EN = 0, + parameter [7:0] RX_8B10B_BYPASS = 0, + parameter [0:0] RX_BYTE_REALIGN = 0, + parameter [0:0] RX_DBG_EN = 0, + parameter [1:0] RX_DBG_SEL = 0, + parameter [0:0] RX_DBG_MODE = 0, + parameter [5:0] RX_DBG_SRAM_DELAY = 6'h05, + parameter [9:0] RX_DBG_ADDR = 0, + parameter [0:0] RX_DBG_RE = 0, + parameter [0:0] RX_DBG_WE = 0, + parameter [19:0] RX_DBG_DATA = 0, + parameter [4:0] TX_SEL_PRE = 0, + parameter [4:0] TX_SEL_POST = 0, + parameter [4:0] TX_AMP = 15, + parameter [4:0] TX_BRANCH_EN_PRE = 0, + parameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F, + parameter [4:0] TX_BRANCH_EN_POST = 0, + parameter [2:0] TX_TAIL_CASCODE = 4, + parameter [6:0] TX_DC_ENABLE = 63, + parameter [4:0] TX_DC_OFFSET = 0, + parameter [4:0] TX_CM_RAISE = 0, + parameter [4:0] TX_CM_THRESHOLD_0 = 14, + parameter [4:0] TX_CM_THRESHOLD_1 = 16, + parameter [4:0] TX_SEL_PRE_EI = 0, + parameter [4:0] TX_SEL_POST_EI = 0, + parameter [4:0] TX_AMP_EI = 15, + parameter [4:0] TX_BRANCH_EN_PRE_EI = 0, + parameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F, + parameter [4:0] TX_BRANCH_EN_POST_EI = 0, + parameter [2:0] TX_TAIL_CASCODE_EI = 4, + parameter [6:0] TX_DC_ENABLE_EI = 63, + parameter [4:0] TX_DC_OFFSET_EI = 0, + parameter [4:0] TX_CM_RAISE_EI = 0, + parameter [4:0] TX_CM_THRESHOLD_0_EI = 14, + parameter [4:0] TX_CM_THRESHOLD_1_EI = 16, + parameter [4:0] TX_SEL_PRE_RXDET = 0, + parameter [4:0] TX_SEL_POST_RXDET = 0, + parameter [4:0] TX_AMP_RXDET = 15, + parameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0, + parameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F, + parameter [4:0] TX_BRANCH_EN_POST_RXDET = 0, + parameter [2:0] TX_TAIL_CASCODE_RXDET = 4, + parameter [6:0] TX_DC_ENABLE_RXDET = 63, + parameter [4:0] TX_DC_OFFSET_RXDET = 0, + parameter [4:0] TX_CM_RAISE_RXDET = 0, + parameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14, + parameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16, + parameter [0:0] TX_CALIB_EN = 0, + parameter [0:0] TX_CALIB_OVR = 0, + parameter [3:0] TX_CALIB_VAL = 0, + parameter [7:0] TX_CM_REG_KI = 8'h80, + parameter [0:0] TX_CM_SAR_EN = 0, + parameter [0:0] TX_CM_REG_EN = 1, + parameter [4:0] TX_PMA_RESET_TIME = 3, + parameter [4:0] TX_PCS_RESET_TIME = 3, + parameter [0:0] TX_PCS_RESET_OVR = 0, + parameter [0:0] TX_PCS_RESET = 0, + parameter [0:0] TX_PMA_RESET_OVR = 0, + parameter [0:0] TX_PMA_RESET = 0, + parameter [0:0] TX_RESET_OVR = 0, + parameter [0:0] TX_RESET = 0, + parameter [1:0] TX_PMA_LOOPBACK = 0, + parameter [0:0] TX_PCS_LOOPBACK = 0, + parameter [1:0] TX_DATAPATH_SEL = 3, + parameter [0:0] TX_PRBS_OVR = 0, + parameter [2:0] TX_PRBS_SEL = 0, + parameter [0:0] TX_PRBS_FORCE_ERR = 0, + parameter [0:0] TX_LOOPBACK_OVR = 0, + parameter [0:0] TX_POWER_DOWN_OVR = 0, + parameter [0:0] TX_POWER_DOWN_N = 0, + parameter [0:0] TX_ELEC_IDLE_OVR = 0, + parameter [0:0] TX_ELEC_IDLE = 0, + parameter [0:0] TX_DETECT_RX_OVR = 0, + parameter [0:0] TX_DETECT_RX = 0, + parameter [0:0] TX_POLARITY_OVR = 0, + parameter [0:0] TX_POLARITY = 0, + parameter [0:0] TX_8B10B_EN_OVR = 0, + parameter [0:0] TX_8B10B_EN = 0, + parameter [0:0] TX_DATA_OVR = 0, + parameter [2:0] TX_DATA_CNT = 0, + parameter [0:0] TX_DATA_VALID = 0, + parameter [0:0] PLL_EN_ADPLL_CTRL = 0, + parameter [0:0] PLL_CONFIG_SEL = 0, + parameter [0:0] PLL_SET_OP_LOCK = 0, + parameter [0:0] PLL_ENFORCE_LOCK = 0, + parameter [0:0] PLL_DISABLE_LOCK = 0, + parameter [0:0] PLL_LOCK_WINDOW = 1, + parameter [0:0] PLL_FAST_LOCK = 1, + parameter [0:0] PLL_SYNC_BYPASS = 0, + parameter [0:0] PLL_PFD_SELECT = 0, + parameter [0:0] PLL_REF_BYPASS = 0, + parameter [0:0] PLL_REF_SEL = 0, + parameter [0:0] PLL_REF_RTERM = 1, + parameter [5:0] PLL_FCNTRL = 58, + parameter [5:0] PLL_MAIN_DIVSEL = 27, + parameter [1:0] PLL_OUT_DIVSEL = 0, + parameter [4:0] PLL_CI = 3, + parameter [9:0] PLL_CP = 80, + parameter [3:0] PLL_AO = 0, + parameter [2:0] PLL_SCAP = 0, + parameter [1:0] PLL_FILTER_SHIFT = 2, + parameter [2:0] PLL_SAR_LIMIT = 2, + parameter [10:0] PLL_FT = 512, + parameter [0:0] PLL_OPEN_LOOP = 0, + parameter [0:0] PLL_SCAP_AUTO_CAL = 1, + parameter [2:0] PLL_BISC_MODE = 4, + parameter [3:0] PLL_BISC_TIMER_MAX = 15, + parameter [0:0] PLL_BISC_OPT_DET_IND = 0, + parameter [0:0] PLL_BISC_PFD_SEL = 0, + parameter [0:0] PLL_BISC_DLY_DIR = 0, + parameter [2:0] PLL_BISC_COR_DLY = 1, + parameter [0:0] PLL_BISC_CAL_SIGN = 0, + parameter [0:0] PLL_BISC_CAL_AUTO = 1, + parameter [4:0] PLL_BISC_CP_MIN = 4, + parameter [4:0] PLL_BISC_CP_MAX = 18, + parameter [4:0] PLL_BISC_CP_START = 12, + parameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0, + parameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2, + parameter [0:0] SERDES_ENABLE = 0, + parameter [0:0] SERDES_AUTO_INIT = 0, + parameter [0:0] SERDES_TESTMODE = 0 +)( + input [63:0] TX_DATA_I, + input TX_RESET_I, + input TX_PCS_RESET_I, + input TX_PMA_RESET_I, + input PLL_RESET_I, + input TX_POWER_DOWN_N_I, + input TX_POLARITY_I, + input [2:0] TX_PRBS_SEL_I, + input TX_PRBS_FORCE_ERR_I, + input TX_8B10B_EN_I, + input [7:0] TX_8B10B_BYPASS_I, + input [7:0] TX_CHAR_IS_K_I, + input [7:0] TX_CHAR_DISPMODE_I, + input [7:0] TX_CHAR_DISPVAL_I, + input TX_ELEC_IDLE_I, + input TX_DETECT_RX_I, + input [2:0] LOOPBACK_I, + input TX_CLK_I, + input RX_CLK_I, + input RX_RESET_I, + input RX_PMA_RESET_I, + input RX_EQA_RESET_I, + input RX_CDR_RESET_I, + input RX_PCS_RESET_I, + input RX_BUF_RESET_I, + input RX_POWER_DOWN_N_I, + input RX_POLARITY_I, + input [2:0] RX_PRBS_SEL_I, + input RX_PRBS_CNT_RESET_I, + input RX_8B10B_EN_I, + input [7:0] RX_8B10B_BYPASS_I, + input RX_EN_EI_DETECTOR_I, + input RX_COMMA_DETECT_EN_I, + input RX_SLIDE_I, + input RX_MCOMMA_ALIGN_I, + input RX_PCOMMA_ALIGN_I, + input REGFILE_CLK_I, + input REGFILE_WE_I, + input REGFILE_EN_I, + input [7:0] REGFILE_ADDR_I, + input [15:0] REGFILE_DI_I, + input [15:0] REGFILE_MASK_I, + output [63:0] RX_DATA_O, + output [7:0] RX_NOT_IN_TABLE_O, + output [7:0] RX_CHAR_IS_COMMA_O, + output [7:0] RX_CHAR_IS_K_O, + output [7:0] RX_DISP_ERR_O, + output TX_DETECT_RX_DONE_O, + output TX_DETECT_RX_PRESENT_O, + output TX_BUF_ERR_O, + output TX_RESET_DONE_O, + output RX_PRBS_ERR_O, + output RX_BUF_ERR_O, + output RX_BYTE_IS_ALIGNED_O, + output RX_BYTE_REALIGN_O, + output RX_RESET_DONE_O, + output RX_EI_EN_O, + output RX_CLK_O, + output PLL_CLK_O, + output [15:0] REGFILE_DO_O, + output REGFILE_RDY_O +); +endmodule + +(* blackbox *) (* keep *) +module CC_CFG_CTRL( + input [7:0] DATA, + input CLK, + input EN, + input RECFG, + input VALID +); +endmodule + +(* blackbox *) (* keep *) +module CC_USR_RSTN ( + output USR_RSTN +); +endmodule diff --git a/techlibs/gatemate/cells_sim.v b/techlibs/gatemate/cells_sim.v index d930b83f8..e4b79c31b 100644 --- a/techlibs/gatemate/cells_sim.v +++ b/techlibs/gatemate/cells_sim.v @@ -1,1842 +1,1842 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`timescale 1ps/1ps - -module CC_IBUF #( - parameter PIN_NAME = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter [0:0] PULLUP = 1'bx, - parameter [0:0] PULLDOWN = 1'bx, - parameter [0:0] KEEPER = 1'bx, - parameter [0:0] SCHMITT_TRIGGER = 1'bx, - // IOSEL - parameter [3:0] DELAY_IBF = 1'bx, - parameter [0:0] FF_IBF = 1'bx -)( - (* iopad_external_pin *) - input I, - output Y -); - assign Y = I; - -endmodule - - -module CC_OBUF #( - parameter PIN_NAME = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter DRIVE = "UNDEFINED", - parameter SLEW = "UNDEFINED", - // IOSEL - parameter [3:0] DELAY_OBF = 1'bx, - parameter [0:0] FF_OBF = 1'bx -)( - input A, - (* iopad_external_pin *) - output O -); - assign O = A; - -endmodule - - -module CC_TOBUF #( - parameter PIN_NAME = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter DRIVE = "UNDEFINED", - parameter SLEW = "UNDEFINED", - parameter [0:0] PULLUP = 1'bx, - parameter [0:0] PULLDOWN = 1'bx, - parameter [0:0] KEEPER = 1'bx, - // IOSEL - parameter [3:0] DELAY_OBF = 1'bx, - parameter [0:0] FF_OBF = 1'bx -)( - input A, T, - (* iopad_external_pin *) - output O -); - assign O = T ? 1'bz : A; - -endmodule - - -module CC_IOBUF #( - parameter PIN_NAME = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter DRIVE = "UNDEFINED", - parameter SLEW = "UNDEFINED", - parameter [0:0] PULLUP = 1'bx, - parameter [0:0] PULLDOWN = 1'bx, - parameter [0:0] KEEPER = 1'bx, - parameter [0:0] SCHMITT_TRIGGER = 1'bx, - // IOSEL - parameter [3:0] DELAY_IBF = 1'bx, - parameter [3:0] DELAY_OBF = 1'bx, - parameter [0:0] FF_IBF = 1'bx, - parameter [0:0] FF_OBF = 1'bx -)( - input A, T, - output Y, - (* iopad_external_pin *) - inout IO -); - assign IO = T ? 1'bz : A; - assign Y = IO; - -endmodule - - -module CC_LVDS_IBUF #( - parameter PIN_NAME_P = "UNPLACED", - parameter PIN_NAME_N = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter [0:0] LVDS_RTERM = 1'bx, - // IOSEL - parameter [3:0] DELAY_IBF = 1'bx, - parameter [0:0] FF_IBF = 1'bx -)( - (* iopad_external_pin *) - input I_P, I_N, - output Y -); - assign Y = I_P; - -endmodule - - -module CC_LVDS_OBUF #( - parameter PIN_NAME_P = "UNPLACED", - parameter PIN_NAME_N = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter [0:0] LVDS_BOOST = 1'bx, - // IOSEL - parameter [3:0] DELAY_OBF = 1'bx, - parameter [0:0] FF_OBF = 1'bx -)( - input A, - (* iopad_external_pin *) - output O_P, O_N -); - assign O_P = A; - assign O_N = ~A; - -endmodule - - -module CC_LVDS_TOBUF #( - parameter PIN_NAME_P = "UNPLACED", - parameter PIN_NAME_N = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter [0:0] LVDS_BOOST = 1'bx, - // IOSEL - parameter [3:0] DELAY_OBF = 1'bx, - parameter [0:0] FF_OBF = 1'bx -)( - input A, T, - (* iopad_external_pin *) - output O_P, O_N -); - assign O_P = T ? 1'bz : A; - assign O_N = T ? 1'bz : ~A; - -endmodule - - -module CC_LVDS_IOBUF #( - parameter PIN_NAME_P = "UNPLACED", - parameter PIN_NAME_N = "UNPLACED", - parameter V_IO = "UNDEFINED", - parameter [0:0] LVDS_RTERM = 1'bx, - parameter [0:0] LVDS_BOOST = 1'bx, - // IOSEL - parameter [3:0] DELAY_IBF = 1'bx, - parameter [3:0] DELAY_OBF = 1'bx, - parameter [0:0] FF_IBF = 1'bx, - parameter [0:0] FF_OBF = 1'bx -)( - input A, T, - (* iopad_external_pin *) - inout IO_P, IO_N, - output Y -); - assign IO_P = T ? 1'bz : A; - assign IO_N = T ? 1'bz : ~A; - assign Y = IO_P; - -endmodule - - -module CC_IDDR #( - parameter [0:0] CLK_INV = 1'b0 -)( - input D, - (* clkbuf_sink *) - input CLK, - output reg Q0, Q1 -); - wire clk; - assign clk = (CLK_INV) ? ~CLK : CLK; - - always @(posedge clk) - begin - Q0 <= D; - end - - always @(negedge clk) - begin - Q1 <= D; - end - -endmodule - - -module CC_ODDR #( - parameter [0:0] CLK_INV = 1'b0 -)( - input D0, - input D1, - (* clkbuf_sink *) - input CLK, - (* clkbuf_sink *) - input DDR, - output Q -); - wire clk; - assign clk = (CLK_INV) ? ~CLK : CLK; - - reg q0, q1; - assign Q = (DDR) ? q0 : q1; - - always @(posedge clk) - begin - q0 <= D0; - end - - always @(negedge clk) - begin - q1 <= D1; - end - -endmodule - - -module CC_DFF #( - parameter [0:0] CLK_INV = 1'b0, - parameter [0:0] EN_INV = 1'b0, - parameter [0:0] SR_INV = 1'b0, - parameter [0:0] SR_VAL = 1'b0, - parameter [0:0] INIT = 1'bx -)( - input D, - (* clkbuf_sink *) - input CLK, - input EN, - input SR, - output reg Q -); - wire clk, en, sr; - assign clk = (CLK_INV) ? ~CLK : CLK; - assign en = (EN_INV) ? ~EN : EN; - assign sr = (SR_INV) ? ~SR : SR; - - initial Q = INIT; - - always @(posedge clk or posedge sr) - begin - if (sr) begin - Q <= SR_VAL; - end - else if (en) begin - Q <= D; - end - end - -endmodule - - -module CC_DLT #( - parameter [0:0] G_INV = 1'b0, - parameter [0:0] SR_INV = 1'b0, - parameter [0:0] SR_VAL = 1'b0, - parameter [0:0] INIT = 1'bx -)( - input D, - input G, - input SR, - output reg Q -); - wire en, sr; - assign en = (G_INV) ? ~G : G; - assign sr = (SR_INV) ? ~SR : SR; - - initial Q = INIT; - - always @(*) - begin - if (sr) begin - Q = SR_VAL; - end - else if (en) begin - Q = D; - end - end - -endmodule - - -module CC_LUT1 ( - output O, - input I0 -); - parameter [1:0] INIT = 0; - - assign O = I0 ? INIT[1] : INIT[0]; - -endmodule - - -module CC_LUT2 ( - output O, - input I0, I1 -); - parameter [3:0] INIT = 0; - - wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; - assign O = I0 ? s1[1] : s1[0]; - -endmodule - - -module CC_LUT3 ( - output O, - input I0, I1, I2 -); - parameter [7:0] INIT = 0; - - wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; - -endmodule - - -module CC_LUT4 ( - output O, - input I0, I1, I2, I3 -); - parameter [15:0] INIT = 0; - - wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; - wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; - -endmodule - - -module CC_MX2 ( - input D0, D1, - input S0, - output Y -); - assign Y = S0 ? D1 : D0; - -endmodule - - -module CC_MX4 ( - input D0, D1, D2, D3, - input S0, S1, - output Y -); - assign Y = S1 ? (S0 ? D3 : D2) : - (S0 ? D1 : D0); - -endmodule - - -module CC_MX8 ( - input D0, D1, D2, D3, - input D4, D5, D6, D7, - input S0, S1, S2, - output Y -); - assign Y = S2 ? (S1 ? (S0 ? D7 : D6) : - (S0 ? D5 : D4)) : - (S1 ? (S0 ? D3 : D2) : - (S0 ? D1 : D0)); - -endmodule - - -module CC_ADDF ( - input A, B, CI, - output CO, S -); - assign {CO, S} = A + B + CI; - -endmodule - - -module CC_MULT #( - parameter A_WIDTH = 0, - parameter B_WIDTH = 0, - parameter P_WIDTH = 0 -)( - input signed [A_WIDTH-1:0] A, - input signed [B_WIDTH-1:0] B, - output reg signed [P_WIDTH-1:0] P -); - always @(*) - begin - P = A * B; - end -endmodule - - -module CC_BUFG ( - input I, - (* clkbuf_driver *) - output O -); - assign O = I; - -endmodule - - -module CC_BRAM_20K ( - output [19:0] A_DO, - output [19:0] B_DO, - output ECC_1B_ERR, - output ECC_2B_ERR, - (* clkbuf_sink *) - input A_CLK, - (* clkbuf_sink *) - input B_CLK, - input A_EN, - input B_EN, - input A_WE, - input B_WE, - input [15:0] A_ADDR, - input [15:0] B_ADDR, - input [19:0] A_DI, - input [19:0] B_DI, - input [19:0] A_BM, - input [19:0] B_BM -); - // Location format: D(0..N-1)(0..N-1)X(0..3)Y(0..7)Z(0..1) or UNPLACED - parameter LOC = "UNPLACED"; - - // Port Widths - parameter A_RD_WIDTH = 0; - parameter B_RD_WIDTH = 0; - parameter A_WR_WIDTH = 0; - parameter B_WR_WIDTH = 0; - - // RAM and Write Modes - parameter RAM_MODE = "SDP"; - parameter A_WR_MODE = "NO_CHANGE"; - parameter B_WR_MODE = "NO_CHANGE"; - - // Inverting Control Pins - parameter A_CLK_INV = 1'b0; - parameter B_CLK_INV = 1'b0; - parameter A_EN_INV = 1'b0; - parameter B_EN_INV = 1'b0; - parameter A_WE_INV = 1'b0; - parameter B_WE_INV = 1'b0; - - // Output Register - parameter A_DO_REG = 1'b0; - parameter B_DO_REG = 1'b0; - - // Error Checking and Correction - parameter ECC_EN = 1'b0; - - // RAM Contents - parameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - - localparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH; - localparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH; - - integer i, k; - - // 512 x 40 bit - reg [20479:0] memory = 20480'b0; - - initial begin - // Check parameters - if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin - $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); - $finish(); - end - if ((A_WR_MODE != "WRITE_THROUGH") && (A_WR_MODE != "NO_CHANGE")) begin - $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); - $finish(); - end - if ((RAM_MODE == "SDP") && (A_WR_MODE == "WRITE_THROUGH")) begin - $display("ERROR: %s is not supported in %s mode.", A_WR_MODE, RAM_MODE); - $finish(); - end - if (ECC_EN != 1'b0) begin - $display("WARNING: ECC feature not supported in simulation."); - end - if ((ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (WIDTH_MODE_A != 40)) begin - $display("ERROR: Illegal ECC Port configuration. Must be SDP 40 bit, but is %s %d.", RAM_MODE, WIDTH_MODE_A); - $finish(); - end - if ((WIDTH_MODE_A == 40) && (RAM_MODE == "TDP")) begin - $display("ERROR: Port A width of 40 bits is only supported in SDP mode."); - $finish(); - end - if ((WIDTH_MODE_B == 40) && (RAM_MODE == "TDP")) begin - $display("ERROR: Port B width of 40 bits is only supported in SDP mode."); - $finish(); - end - if ((WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) && - (WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin - $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A); - $finish(); - end - if ((WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) && - (WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin - $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, WIDTH_MODE_B); - $finish(); - end - // RAM initialization - memory[320*0+319:320*0] = INIT_00; - memory[320*1+319:320*1] = INIT_01; - memory[320*2+319:320*2] = INIT_02; - memory[320*3+319:320*3] = INIT_03; - memory[320*4+319:320*4] = INIT_04; - memory[320*5+319:320*5] = INIT_05; - memory[320*6+319:320*6] = INIT_06; - memory[320*7+319:320*7] = INIT_07; - memory[320*8+319:320*8] = INIT_08; - memory[320*9+319:320*9] = INIT_09; - memory[320*10+319:320*10] = INIT_0A; - memory[320*11+319:320*11] = INIT_0B; - memory[320*12+319:320*12] = INIT_0C; - memory[320*13+319:320*13] = INIT_0D; - memory[320*14+319:320*14] = INIT_0E; - memory[320*15+319:320*15] = INIT_0F; - memory[320*16+319:320*16] = INIT_10; - memory[320*17+319:320*17] = INIT_11; - memory[320*18+319:320*18] = INIT_12; - memory[320*19+319:320*19] = INIT_13; - memory[320*20+319:320*20] = INIT_14; - memory[320*21+319:320*21] = INIT_15; - memory[320*22+319:320*22] = INIT_16; - memory[320*23+319:320*23] = INIT_17; - memory[320*24+319:320*24] = INIT_18; - memory[320*25+319:320*25] = INIT_19; - memory[320*26+319:320*26] = INIT_1A; - memory[320*27+319:320*27] = INIT_1B; - memory[320*28+319:320*28] = INIT_1C; - memory[320*29+319:320*29] = INIT_1D; - memory[320*30+319:320*30] = INIT_1E; - memory[320*31+319:320*31] = INIT_1F; - memory[320*32+319:320*32] = INIT_20; - memory[320*33+319:320*33] = INIT_21; - memory[320*34+319:320*34] = INIT_22; - memory[320*35+319:320*35] = INIT_23; - memory[320*36+319:320*36] = INIT_24; - memory[320*37+319:320*37] = INIT_25; - memory[320*38+319:320*38] = INIT_26; - memory[320*39+319:320*39] = INIT_27; - memory[320*40+319:320*40] = INIT_28; - memory[320*41+319:320*41] = INIT_29; - memory[320*42+319:320*42] = INIT_2A; - memory[320*43+319:320*43] = INIT_2B; - memory[320*44+319:320*44] = INIT_2C; - memory[320*45+319:320*45] = INIT_2D; - memory[320*46+319:320*46] = INIT_2E; - memory[320*47+319:320*47] = INIT_2F; - memory[320*48+319:320*48] = INIT_30; - memory[320*49+319:320*49] = INIT_31; - memory[320*50+319:320*50] = INIT_32; - memory[320*51+319:320*51] = INIT_33; - memory[320*52+319:320*52] = INIT_34; - memory[320*53+319:320*53] = INIT_35; - memory[320*54+319:320*54] = INIT_36; - memory[320*55+319:320*55] = INIT_37; - memory[320*56+319:320*56] = INIT_38; - memory[320*57+319:320*57] = INIT_39; - memory[320*58+319:320*58] = INIT_3A; - memory[320*59+319:320*59] = INIT_3B; - memory[320*60+319:320*60] = INIT_3C; - memory[320*61+319:320*61] = INIT_3D; - memory[320*62+319:320*62] = INIT_3E; - memory[320*63+319:320*63] = INIT_3F; - end - - // Signal inversion - wire clka = A_CLK_INV ^ A_CLK; - wire clkb = B_CLK_INV ^ B_CLK; - wire ena = A_EN_INV ^ A_EN; - wire enb = B_EN_INV ^ B_EN; - wire wea = A_WE_INV ^ A_WE; - wire web = B_WE_INV ^ B_WE; - - // Internal signals - wire [15:0] addra; - wire [15:0] addrb; - reg [19:0] A_DO_out = 0, A_DO_reg = 0; - reg [19:0] B_DO_out = 0, B_DO_reg = 0; - - generate - if (RAM_MODE == "SDP") begin - // Port A (write) - if (A_WR_WIDTH == 40) begin - assign addra = A_ADDR[15:7]*40; - end - // Port B (read) - if (B_RD_WIDTH == 40) begin - assign addrb = B_ADDR[15:7]*40; - end - end - else if (RAM_MODE == "TDP") begin - // Port A - if (WIDTH_MODE_A <= 1) begin - wire [15:0] tmpa = {2'b0, A_ADDR[15:7], A_ADDR[5:1]}; - assign addra = tmpa + (tmpa/4); - end - else if (WIDTH_MODE_A <= 2) begin - wire [15:0] tmpa = {3'b0, A_ADDR[15:7], A_ADDR[5:2]}; - assign addra = tmpa*2 + (tmpa/2); - end - else if (WIDTH_MODE_A <= 5) begin - assign addra = {4'b0, A_ADDR[15:7], A_ADDR[5:3]}*5; - end - else if (WIDTH_MODE_A <= 10) begin - assign addra = {5'b0, A_ADDR[15:7], A_ADDR[5:4]}*10; - end - else if (WIDTH_MODE_A <= 20) begin - assign addra = {6'b0, A_ADDR[15:7], A_ADDR[5]}*20; - end - // Port B - if (WIDTH_MODE_B <= 1) begin - wire [15:0] tmpb = {2'b0, B_ADDR[15:7], B_ADDR[5:1]}; - assign addrb = tmpb + (tmpb/4); - end - else if (WIDTH_MODE_B <= 2) begin - wire [15:0] tmpb = {3'b0, B_ADDR[15:7], B_ADDR[5:2]}; - assign addrb = tmpb*2 + (tmpb/2); - end - else if (WIDTH_MODE_B <= 5) begin - assign addrb = {4'b0, B_ADDR[15:7], B_ADDR[5:3]}*5; - end - else if (WIDTH_MODE_B <= 10) begin - assign addrb = {5'b0, B_ADDR[15:7], B_ADDR[5:4]}*10; - end - else if (WIDTH_MODE_B <= 20) begin - assign addrb = {6'b0, B_ADDR[15:7], B_ADDR[5]}*20; - end - end - endgenerate - - generate - if (RAM_MODE == "SDP") begin - // SDP write port - always @(posedge clka) - begin - for (k=0; k < A_WR_WIDTH; k=k+1) begin - if (k < 20) begin - if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k]; - end - else begin // use both ports - if (ena && wea && B_BM[k-20]) memory[addra+k] <= B_DI[k-20]; - end - end - end - // SDP read port - always @(posedge clkb) - begin - for (k=0; k < B_RD_WIDTH; k=k+1) begin - if (k < 20) begin - if (enb) A_DO_out[k] <= memory[addrb+k]; - end - else begin // use both ports - if (enb) B_DO_out[k-20] <= memory[addrb+k]; - end - end - end - end - else if (RAM_MODE == "TDP") begin - // TDP port A - always @(posedge clka) - begin - for (i=0; i < WIDTH_MODE_A; i=i+1) begin - if (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i]; - - if (A_WR_MODE == "NO_CHANGE") begin - if (ena && !wea) A_DO_out[i] <= memory[addra+i]; - end - else if (A_WR_MODE == "WRITE_THROUGH") begin - if (ena) begin - if (wea && A_BM[i]) begin - A_DO_out[i] <= A_DI[i]; - end - else begin - A_DO_out[i] <= memory[addra+i]; - end - end - end - end - end - // TDP port B - always @(posedge clkb) - begin - for (i=0; i < WIDTH_MODE_B; i=i+1) begin - if (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i]; - - if (B_WR_MODE == "NO_CHANGE") begin - if (enb && !web) B_DO_out[i] <= memory[addrb+i]; - end - else if (B_WR_MODE == "WRITE_THROUGH") begin - if (enb) begin - if (web && B_BM[i]) begin - B_DO_out[i] <= B_DI[i]; - end - else begin - B_DO_out[i] <= memory[addrb+i]; - end - end - end - end - end - end - endgenerate - - // Optional output register - generate - if (A_DO_REG) begin - always @(posedge clka) begin - A_DO_reg <= A_DO_out; - end - assign A_DO = A_DO_reg; - end - else begin - assign A_DO = A_DO_out; - end - if (B_DO_REG) begin - always @(posedge clkb) begin - B_DO_reg <= B_DO_out; - end - assign B_DO = B_DO_reg; - end - else begin - assign B_DO = B_DO_out; - end - endgenerate -endmodule - - -module CC_BRAM_40K ( - output [39:0] A_DO, - output [39:0] B_DO, - output A_ECC_1B_ERR, - output B_ECC_1B_ERR, - output A_ECC_2B_ERR, - output B_ECC_2B_ERR, - output reg A_CO = 0, - output reg B_CO = 0, - (* clkbuf_sink *) - input A_CLK, - (* clkbuf_sink *) - input B_CLK, - input A_EN, - input B_EN, - input A_WE, - input B_WE, - input [15:0] A_ADDR, - input [15:0] B_ADDR, - input [39:0] A_DI, - input [39:0] B_DI, - input [39:0] A_BM, - input [39:0] B_BM, - input A_CI, - input B_CI -); - // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED - parameter LOC = "UNPLACED"; - parameter CAS = "NONE"; // NONE, UPPER, LOWER - - // Port Widths - parameter A_RD_WIDTH = 0; - parameter B_RD_WIDTH = 0; - parameter A_WR_WIDTH = 0; - parameter B_WR_WIDTH = 0; - - // RAM and Write Modes - parameter RAM_MODE = "SDP"; - parameter A_WR_MODE = "NO_CHANGE"; - parameter B_WR_MODE = "NO_CHANGE"; - - // Inverting Control Pins - parameter A_CLK_INV = 1'b0; - parameter B_CLK_INV = 1'b0; - parameter A_EN_INV = 1'b0; - parameter B_EN_INV = 1'b0; - parameter A_WE_INV = 1'b0; - parameter B_WE_INV = 1'b0; - - // Output Register - parameter A_DO_REG = 1'b0; - parameter B_DO_REG = 1'b0; - - // Error Checking and Correction - parameter A_ECC_EN = 1'b0; - parameter B_ECC_EN = 1'b0; - - parameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; - - localparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH; - localparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH; - - integer i, k; - - // 512 x 80 bit - reg [40959:0] memory = 40960'b0; - - initial begin - // Check parameters - if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin - $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); - $finish(); - end - if ((A_WR_MODE != "WRITE_THROUGH") && (A_WR_MODE != "NO_CHANGE")) begin - $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); - $finish(); - end - if ((RAM_MODE == "SDP") && (A_WR_MODE == "WRITE_THROUGH")) begin - $display("ERROR: %s is not supported in %s mode.", A_WR_MODE, RAM_MODE); - $finish(); - end - if ((A_ECC_EN != 1'b0) || (B_ECC_EN != 1'b0)) begin - $display("WARNING: ECC feature not supported in simulation."); - end - if ((A_ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (WIDTH_MODE_A != 40)) begin - $display("ERROR: Illegal ECC Port A configuration. Must be SDP 40 bit, but is %s %d.", RAM_MODE, WIDTH_MODE_A); - $finish(); - end - if ((WIDTH_MODE_A == 80) && (RAM_MODE == "TDP")) begin - $display("ERROR: Port A width of 80 bits is only supported in SDP mode."); - $finish(); - end - if ((WIDTH_MODE_B == 80) && (RAM_MODE == "TDP")) begin - $display("ERROR: Port B width of 80 bits is only supported in SDP mode."); - $finish(); - end - if ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) && - (WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin - $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A); - $finish(); - end - if ((WIDTH_MODE_B != 80) && (WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) && - (WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin - $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, WIDTH_MODE_B); - $finish(); - end - if ((CAS != "NONE") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin - $display("ERROR: Cascade feature only supported in 1 bit data width mode."); - $finish(); - end - if ((CAS != "NONE") && (RAM_MODE != "TDP")) begin - $display("ERROR: Cascade feature only supported in TDP mode."); - $finish(); - end - // RAM initialization - memory[320*0+319:320*0] = INIT_00; - memory[320*1+319:320*1] = INIT_01; - memory[320*2+319:320*2] = INIT_02; - memory[320*3+319:320*3] = INIT_03; - memory[320*4+319:320*4] = INIT_04; - memory[320*5+319:320*5] = INIT_05; - memory[320*6+319:320*6] = INIT_06; - memory[320*7+319:320*7] = INIT_07; - memory[320*8+319:320*8] = INIT_08; - memory[320*9+319:320*9] = INIT_09; - memory[320*10+319:320*10] = INIT_0A; - memory[320*11+319:320*11] = INIT_0B; - memory[320*12+319:320*12] = INIT_0C; - memory[320*13+319:320*13] = INIT_0D; - memory[320*14+319:320*14] = INIT_0E; - memory[320*15+319:320*15] = INIT_0F; - memory[320*16+319:320*16] = INIT_10; - memory[320*17+319:320*17] = INIT_11; - memory[320*18+319:320*18] = INIT_12; - memory[320*19+319:320*19] = INIT_13; - memory[320*20+319:320*20] = INIT_14; - memory[320*21+319:320*21] = INIT_15; - memory[320*22+319:320*22] = INIT_16; - memory[320*23+319:320*23] = INIT_17; - memory[320*24+319:320*24] = INIT_18; - memory[320*25+319:320*25] = INIT_19; - memory[320*26+319:320*26] = INIT_1A; - memory[320*27+319:320*27] = INIT_1B; - memory[320*28+319:320*28] = INIT_1C; - memory[320*29+319:320*29] = INIT_1D; - memory[320*30+319:320*30] = INIT_1E; - memory[320*31+319:320*31] = INIT_1F; - memory[320*32+319:320*32] = INIT_20; - memory[320*33+319:320*33] = INIT_21; - memory[320*34+319:320*34] = INIT_22; - memory[320*35+319:320*35] = INIT_23; - memory[320*36+319:320*36] = INIT_24; - memory[320*37+319:320*37] = INIT_25; - memory[320*38+319:320*38] = INIT_26; - memory[320*39+319:320*39] = INIT_27; - memory[320*40+319:320*40] = INIT_28; - memory[320*41+319:320*41] = INIT_29; - memory[320*42+319:320*42] = INIT_2A; - memory[320*43+319:320*43] = INIT_2B; - memory[320*44+319:320*44] = INIT_2C; - memory[320*45+319:320*45] = INIT_2D; - memory[320*46+319:320*46] = INIT_2E; - memory[320*47+319:320*47] = INIT_2F; - memory[320*48+319:320*48] = INIT_30; - memory[320*49+319:320*49] = INIT_31; - memory[320*50+319:320*50] = INIT_32; - memory[320*51+319:320*51] = INIT_33; - memory[320*52+319:320*52] = INIT_34; - memory[320*53+319:320*53] = INIT_35; - memory[320*54+319:320*54] = INIT_36; - memory[320*55+319:320*55] = INIT_37; - memory[320*56+319:320*56] = INIT_38; - memory[320*57+319:320*57] = INIT_39; - memory[320*58+319:320*58] = INIT_3A; - memory[320*59+319:320*59] = INIT_3B; - memory[320*60+319:320*60] = INIT_3C; - memory[320*61+319:320*61] = INIT_3D; - memory[320*62+319:320*62] = INIT_3E; - memory[320*63+319:320*63] = INIT_3F; - memory[320*64+319:320*64] = INIT_40; - memory[320*65+319:320*65] = INIT_41; - memory[320*66+319:320*66] = INIT_42; - memory[320*67+319:320*67] = INIT_43; - memory[320*68+319:320*68] = INIT_44; - memory[320*69+319:320*69] = INIT_45; - memory[320*70+319:320*70] = INIT_46; - memory[320*71+319:320*71] = INIT_47; - memory[320*72+319:320*72] = INIT_48; - memory[320*73+319:320*73] = INIT_49; - memory[320*74+319:320*74] = INIT_4A; - memory[320*75+319:320*75] = INIT_4B; - memory[320*76+319:320*76] = INIT_4C; - memory[320*77+319:320*77] = INIT_4D; - memory[320*78+319:320*78] = INIT_4E; - memory[320*79+319:320*79] = INIT_4F; - memory[320*80+319:320*80] = INIT_50; - memory[320*81+319:320*81] = INIT_51; - memory[320*82+319:320*82] = INIT_52; - memory[320*83+319:320*83] = INIT_53; - memory[320*84+319:320*84] = INIT_54; - memory[320*85+319:320*85] = INIT_55; - memory[320*86+319:320*86] = INIT_56; - memory[320*87+319:320*87] = INIT_57; - memory[320*88+319:320*88] = INIT_58; - memory[320*89+319:320*89] = INIT_59; - memory[320*90+319:320*90] = INIT_5A; - memory[320*91+319:320*91] = INIT_5B; - memory[320*92+319:320*92] = INIT_5C; - memory[320*93+319:320*93] = INIT_5D; - memory[320*94+319:320*94] = INIT_5E; - memory[320*95+319:320*95] = INIT_5F; - memory[320*96+319:320*96] = INIT_60; - memory[320*97+319:320*97] = INIT_61; - memory[320*98+319:320*98] = INIT_62; - memory[320*99+319:320*99] = INIT_63; - memory[320*100+319:320*100] = INIT_64; - memory[320*101+319:320*101] = INIT_65; - memory[320*102+319:320*102] = INIT_66; - memory[320*103+319:320*103] = INIT_67; - memory[320*104+319:320*104] = INIT_68; - memory[320*105+319:320*105] = INIT_69; - memory[320*106+319:320*106] = INIT_6A; - memory[320*107+319:320*107] = INIT_6B; - memory[320*108+319:320*108] = INIT_6C; - memory[320*109+319:320*109] = INIT_6D; - memory[320*110+319:320*110] = INIT_6E; - memory[320*111+319:320*111] = INIT_6F; - memory[320*112+319:320*112] = INIT_70; - memory[320*113+319:320*113] = INIT_71; - memory[320*114+319:320*114] = INIT_72; - memory[320*115+319:320*115] = INIT_73; - memory[320*116+319:320*116] = INIT_74; - memory[320*117+319:320*117] = INIT_75; - memory[320*118+319:320*118] = INIT_76; - memory[320*119+319:320*119] = INIT_77; - memory[320*120+319:320*120] = INIT_78; - memory[320*121+319:320*121] = INIT_79; - memory[320*122+319:320*122] = INIT_7A; - memory[320*123+319:320*123] = INIT_7B; - memory[320*124+319:320*124] = INIT_7C; - memory[320*125+319:320*125] = INIT_7D; - memory[320*126+319:320*126] = INIT_7E; - memory[320*127+319:320*127] = INIT_7F; - end - - // Signal inversion - wire clka = A_CLK_INV ^ A_CLK; - wire clkb = B_CLK_INV ^ B_CLK; - wire ena = A_EN_INV ^ A_EN; - wire enb = B_EN_INV ^ B_EN; - wire wea = A_WE_INV ^ A_WE; - wire web = B_WE_INV ^ B_WE; - - // Internal signals - wire [15:0] addra; - wire [15:0] addrb; - reg [39:0] A_DO_out = 0, A_DO_reg = 0; - reg [39:0] B_DO_out = 0, B_DO_reg = 0; - - generate - if (RAM_MODE == "SDP") begin - // Port A (write) - if (A_WR_WIDTH == 80) begin - assign addra = A_ADDR[15:7]*80; - end - // Port B (read) - if (B_RD_WIDTH == 80) begin - assign addrb = B_ADDR[15:7]*80; - end - end - else if (RAM_MODE == "TDP") begin - // Port A - if (WIDTH_MODE_A <= 1) begin - wire [15:0] tmpa = {1'b0, A_ADDR[15:1]}; - assign addra = tmpa + (tmpa/4); - end - else if (WIDTH_MODE_A <= 2) begin - wire [15:0] tmpa = {2'b0, A_ADDR[15:2]}; - assign addra = tmpa*2 + (tmpa/2); - end - else if (WIDTH_MODE_A <= 5) begin - assign addra = {3'b0, A_ADDR[15:3]}*5; - end - else if (WIDTH_MODE_A <= 10) begin - assign addra = {4'b0, A_ADDR[15:4]}*10; - end - else if (WIDTH_MODE_A <= 20) begin - assign addra = {5'b0, A_ADDR[15:5]}*20; - end - else if (WIDTH_MODE_A <= 40) begin - assign addra = {6'b0, A_ADDR[15:6]}*40; - end - // Port B - if (WIDTH_MODE_B <= 1) begin - wire [15:0] tmpb = {1'b0, B_ADDR[15:1]}; - assign addrb = tmpb + (tmpb/4); - end - else if (WIDTH_MODE_B <= 2) begin - wire [15:0] tmpb = {2'b0, B_ADDR[15:2]}; - assign addrb = tmpb*2 + (tmpb/2); - end - else if (WIDTH_MODE_B <= 5) begin - assign addrb = {3'b0, B_ADDR[15:3]}*5; - end - else if (WIDTH_MODE_B <= 10) begin - assign addrb = {4'b0, B_ADDR[15:4]}*10; - end - else if (WIDTH_MODE_B <= 20) begin - assign addrb = {5'b0, B_ADDR[15:5]}*20; - end - else if (WIDTH_MODE_B <= 40) begin - assign addrb = {6'b0, B_ADDR[15:6]}*40; - end - end - endgenerate - - generate - if (RAM_MODE == "SDP") begin - // SDP write port - always @(posedge clka) - begin - for (k=0; k < A_WR_WIDTH; k=k+1) begin - if (k < 40) begin - if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k]; - end - else begin // use both ports - if (ena && wea && B_BM[k-40]) memory[addra+k] <= B_DI[k-40]; - end - end - end - // SDP read port - always @(posedge clkb) - begin - for (k=0; k < B_RD_WIDTH; k=k+1) begin - if (k < 40) begin - if (enb) A_DO_out[k] <= memory[addrb+k]; - end - else begin // use both ports - if (enb) B_DO_out[k-40] <= memory[addrb+k]; - end - end - end - end - else if (RAM_MODE == "TDP") begin - // {A,B}_ADDR[0]=0 selects lower, {A,B}_ADDR[0]=1 selects upper cascade memory - wire upper_sel_a = ((CAS == "UPPER") && (A_ADDR[0] == 1)); - wire lower_sel_a = ((CAS == "LOWER") && (A_ADDR[0] == 0)); - wire upper_sel_b = ((CAS == "UPPER") && (B_ADDR[0] == 1)); - wire lower_sel_b = ((CAS == "LOWER") && (B_ADDR[0] == 0)); - - reg dumm; - - // Cascade output port A - always @(*) - begin - if ((A_WR_MODE == "NO_CHANGE") && lower_sel_a) begin - A_CO = memory[addra]; - end - else if ((A_WR_MODE == "WRITE_THROUGH") && lower_sel_a) begin - A_CO = ((wea && A_BM[0]) ? (A_DI[0]) : (memory[addra])); - end - end - - // Cascade output port B - always @(*) - begin - if ((B_WR_MODE == "NO_CHANGE") && lower_sel_b) begin - B_CO = memory[addrb]; - end - else if ((B_WR_MODE == "WRITE_THROUGH") && lower_sel_b) begin - B_CO = ((web && B_BM[0]) ? (B_DI[0]) : (memory[addrb])); - end - end - - // TDP port A - always @(posedge clka) - begin - for (i=0; i < WIDTH_MODE_A; i=i+1) begin - if (upper_sel_a || lower_sel_a || (CAS == "NONE")) begin - if (ena && wea && A_BM[i]) - memory[addra+i] <= A_DI[i]; - end - - if (A_WR_MODE == "NO_CHANGE") begin - if (ena && !wea) begin - if (CAS == "UPPER") begin - A_DO_out[i] <= ((A_ADDR[0] == 1) ? (memory[addra+i]) : (A_CI)); - end - else if (CAS == "NONE") begin - A_DO_out[i] <= memory[addra+i]; - end - end - end - else if (A_WR_MODE == "WRITE_THROUGH") begin - if (ena) begin - if (CAS == "UPPER") begin - if (A_ADDR[0] == 1) begin - A_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i])); - end else begin - A_DO_out[i] <= A_CI; - end - end - else if (CAS == "NONE") begin - A_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i])); - end - end - end - end - end - // TDP port B - always @(posedge clkb) - begin - for (i=0; i < WIDTH_MODE_B; i=i+1) begin - if (upper_sel_b || lower_sel_b || (CAS == "NONE")) begin - if (enb && web && B_BM[i]) - memory[addrb+i] <= B_DI[i]; - end - - if (B_WR_MODE == "NO_CHANGE") begin - if (enb && !web) begin - if (CAS == "UPPER") begin - B_DO_out[i] <= ((B_ADDR[0] == 1) ? (memory[addrb+i]) : (B_CI)); - end - else if (CAS == "NONE") begin - B_DO_out[i] <= memory[addrb+i]; - end - end - end - else if (B_WR_MODE == "WRITE_THROUGH") begin - if (enb) begin - if (CAS == "UPPER") begin - if (B_ADDR[0] == 1) begin - B_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i])); - end else begin - B_DO_out[i] <= B_CI; - end - end - else if (CAS == "NONE") begin - B_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i])); - end - end - end - end - end - end - endgenerate - - // Optional output register - generate - if (A_DO_REG) begin - always @(posedge clka) begin - A_DO_reg <= A_DO_out; - end - assign A_DO = A_DO_reg; - end - else begin - assign A_DO = A_DO_out; - end - if (B_DO_REG) begin - always @(posedge clkb) begin - B_DO_reg <= B_DO_out; - end - assign B_DO = B_DO_reg; - end - else begin - assign B_DO = B_DO_out; - end - endgenerate -endmodule - -module CC_FIFO_40K ( - output A_ECC_1B_ERR, - output B_ECC_1B_ERR, - output A_ECC_2B_ERR, - output B_ECC_2B_ERR, - // FIFO pop port - output [39:0] A_DO, - output [39:0] B_DO, - (* clkbuf_sink *) - input A_CLK, - input A_EN, - // FIFO push port - input [39:0] A_DI, - input [39:0] B_DI, - input [39:0] A_BM, - input [39:0] B_BM, - (* clkbuf_sink *) - input B_CLK, - input B_EN, - input B_WE, - // FIFO control - input F_RST_N, - input [14:0] F_ALMOST_FULL_OFFSET, - input [14:0] F_ALMOST_EMPTY_OFFSET, - // FIFO status signals - output F_FULL, - output F_EMPTY, - output F_ALMOST_FULL, - output F_ALMOST_EMPTY, - output F_RD_ERROR, - output F_WR_ERROR, - output [15:0] F_RD_PTR, - output [15:0] F_WR_PTR -); - // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED - parameter LOC = "UNPLACED"; - - // Offset configuration - parameter DYN_STAT_SELECT = 1'b0; - parameter [14:0] ALMOST_FULL_OFFSET = 15'b0; - parameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0; - - // Port Widths - parameter A_WIDTH = 0; - parameter B_WIDTH = 0; - - // RAM and Write Modes - parameter RAM_MODE = "TDP"; // "TDP" or "SDP" - parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC" - - // Inverting Control Pins - parameter A_CLK_INV = 1'b0; - parameter B_CLK_INV = 1'b0; - parameter A_EN_INV = 1'b0; - parameter B_EN_INV = 1'b0; - parameter A_WE_INV = 1'b0; - parameter B_WE_INV = 1'b0; - - // Output Register - parameter A_DO_REG = 1'b0; - parameter B_DO_REG = 1'b0; - - // Error Checking and Correction - parameter A_ECC_EN = 1'b0; - parameter B_ECC_EN = 1'b0; - - integer i, k; - - // 512 x 80 bit - reg [40959:0] memory = 40960'b0; - - reg [15:0] counter_max; - reg [15:0] sram_depth; - localparam tp = (A_WIDTH == 1) ? 15 : - (A_WIDTH == 2) ? 14 : - (A_WIDTH == 5) ? 13 : - (A_WIDTH == 10) ? 12 : - (A_WIDTH == 20) ? 11 : - (A_WIDTH == 40) ? 10 : 9; - - initial begin - // Check parameters - if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin - $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); - $finish(); - end - if ((FIFO_MODE != "ASYNC") && (FIFO_MODE != "SYNC")) begin - $display("ERROR: Illegal FIFO MODE %d.", FIFO_MODE); - $finish(); - end - if ((RAM_MODE == "SDP") && (DYN_STAT_SELECT == 1)) begin - $display("ERROR: Dynamic offset configuration is not supported in %s mode.", RAM_MODE); - $finish(); - end - if ((RAM_MODE == "SDP") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin - $display("ERROR: SDP is ony supported in 80 bit mode."); - $finish(); - end - if ((A_WIDTH == 80) && (RAM_MODE == "TDP")) begin - $display("ERROR: Port A width of 80 bits is only supported in SDP mode."); - $finish(); - end - if ((B_WIDTH == 80) && (RAM_MODE == "TDP")) begin - $display("ERROR: Port B width of 80 bits is only supported in SDP mode."); - $finish(); - end - if ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) && - (A_WIDTH != 5) && (A_WIDTH != 2) && (A_WIDTH != 1) && (A_WIDTH != 0)) begin - $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, A_WIDTH); - $finish(); - end - if ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) && - (B_WIDTH != 5) && (B_WIDTH != 2) && (B_WIDTH != 1) && (B_WIDTH != 0)) begin - $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, B_WIDTH); - $finish(); - end - if (A_WIDTH != B_WIDTH) begin - $display("ERROR: The values of A_WIDTH and B_WIDTH must be equal."); - end - if ((A_ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (A_WIDTH != 40)) begin - $display("ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.", RAM_MODE, A_WIDTH); - $finish(); - end - // Set local parameters - if (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH - counter_max = 2 * 32*1024 - 1; - sram_depth = 32*1024; - end - else if (A_WIDTH == 2) begin - counter_max = 2 * 16*1024 - 1; - sram_depth = 16*1024; - end - else if (A_WIDTH == 5) begin - counter_max = 2 * 8*1024 - 1; - sram_depth = 8*1024; - end - else if (A_WIDTH == 10) begin - counter_max = 2 * 4*1024 - 1; - sram_depth = 4*1024; - end - else if (A_WIDTH == 20) begin - counter_max = 2 * 2*1024 - 1; - sram_depth = 2*1024; - end - else if (A_WIDTH == 40) begin - counter_max = 2 * 1*1024 - 1; - sram_depth = 1*1024; - end - else begin // 80 bit SDP - counter_max = 2 * 512 - 1; - sram_depth = 512; - end - end - - // Internal signals - wire fifo_rdclk = A_CLK ^ A_CLK_INV; - wire fifo_wrclk = (FIFO_MODE == "ASYNC") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV); - wire [15:0] almost_full_offset = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET : ALMOST_FULL_OFFSET; - wire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET; - reg [39:0] A_DO_out = 0, A_DO_reg = 0; - reg [39:0] B_DO_out = 0, B_DO_reg = 0; - - // Status signals - reg fifo_full; - reg fifo_empty; - reg fifo_almost_full; - reg fifo_almost_empty; - assign F_FULL = fifo_full; - assign F_EMPTY = fifo_empty; - assign F_ALMOST_FULL = fifo_almost_full; - assign F_ALMOST_EMPTY = fifo_almost_empty; - assign F_WR_ERROR = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV)); - assign F_RD_ERROR = (F_EMPTY && (A_EN ^ A_EN_INV)); - wire ram_we = (~F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV)); - wire ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV)); - - // Reset synchronizers - reg [1:0] aclk_reset_q, bclk_reset_q; - wire fifo_sync_rstn = aclk_reset_q; - wire fifo_async_wrrstn = bclk_reset_q; - wire fifo_async_rdrstn = aclk_reset_q; - - always @(posedge fifo_rdclk or negedge F_RST_N) - begin - if (F_RST_N == 1'b0) begin - aclk_reset_q <= 2'b0; - end - else begin - aclk_reset_q[1] <= aclk_reset_q[0]; - aclk_reset_q[0] <= 1'b1; - end - end - - always @(posedge fifo_wrclk or negedge F_RST_N) - begin - if (F_RST_N == 1'b0) begin - bclk_reset_q <= 2'b0; - end - else begin - bclk_reset_q[1] <= bclk_reset_q[0]; - bclk_reset_q[0] <= 1'b1; - end - end - - // Push/pop pointers - reg [15:0] rd_pointer, rd_pointer_int; - reg [15:0] wr_pointer, wr_pointer_int; - reg [15:0] rd_pointer_cmp, wr_pointer_cmp; - wire [15:0] rd_pointer_nxt; - wire [15:0] wr_pointer_nxt; - reg [15:0] fifo_rdaddr, rdaddr; - reg [15:0] fifo_wraddr, wraddr; - assign F_RD_PTR = fifo_rdaddr; - assign F_WR_PTR = fifo_wraddr; - - always @(posedge fifo_rdclk or negedge F_RST_N) - begin - if (F_RST_N == 1'b0) begin - rd_pointer <= 0; - rd_pointer_int <= 0; - end - else if (ram_en) begin - rd_pointer <= rd_pointer_nxt; - rd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0]; - end - end - - assign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1); - - always @(posedge fifo_wrclk or negedge F_RST_N) - begin - if (F_RST_N == 1'b0) begin - wr_pointer <= 0; - wr_pointer_int <= 0; - end - else if (ram_we) begin - wr_pointer <= wr_pointer_nxt; - wr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0]; - end - end - - assign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1); - - // Address synchronizers - reg [15:0] rd_pointer_sync, wr_pointer_sync; - reg [15:0] rd_pointer_sync_0, rd_pointer_sync_1; - reg [15:0] wr_pointer_sync_0, wr_pointer_sync_1; - - always @(posedge fifo_rdclk or negedge F_RST_N) - begin - if (F_RST_N == 1'b0) begin - wr_pointer_sync_0 <= 0; - wr_pointer_sync_1 <= 0; - end - else begin - wr_pointer_sync_0 <= wraddr; - wr_pointer_sync_1 <= wr_pointer_sync_0; - end - end - - always @(posedge fifo_wrclk or negedge F_RST_N) - begin - if (F_RST_N == 1'b0) begin - rd_pointer_sync_0 <= 0; - rd_pointer_sync_1 <= 0; - end - else begin - rd_pointer_sync_0 <= rdaddr; - rd_pointer_sync_1 <= rd_pointer_sync_0; - end - end - - always @(*) begin - fifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}}; - fifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}}; - - rdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]}; - wraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]}; - - if (FIFO_MODE == "ASYNC") - fifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] ); - else - fifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]); - - if (FIFO_MODE == "ASYNC") - fifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]); - else - fifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]); - - rd_pointer_cmp = (FIFO_MODE == "ASYNC") ? rd_pointer_sync : rd_pointer; - if (wr_pointer[tp] == rd_pointer_cmp[tp]) - fifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset)); - else - fifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset); - - wr_pointer_cmp = (FIFO_MODE == "ASYNC") ? wr_pointer_sync : wr_pointer; - if (wr_pointer_cmp[tp] == rd_pointer[tp]) - fifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset); - else - fifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset)); - end - - generate - always @(*) begin - wr_pointer_sync = 0; - rd_pointer_sync = 0; - for (i=tp; i >= 0; i=i-1) begin - if (i == tp) begin - wr_pointer_sync[i] = wr_pointer_sync_1[i]; - rd_pointer_sync[i] = rd_pointer_sync_1[i]; - end - else begin - wr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1]; - rd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1]; - end - end - end - if (RAM_MODE == "SDP") begin - // SDP push ports A+B - always @(posedge fifo_wrclk) - begin - for (k=0; k < A_WIDTH; k=k+1) begin - if (k < 40) begin - if (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k]; - end - else begin // use both ports - if (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40]; - end - end - end - // SDP pop ports A+B - always @(posedge fifo_rdclk) - begin - for (k=0; k < B_WIDTH; k=k+1) begin - if (k < 40) begin - if (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k]; - end - else begin // use both ports - if (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k]; - end - end - end - end - else if (RAM_MODE == "TDP") begin - // TDP pop port A - always @(posedge fifo_rdclk) - begin - for (i=0; i < A_WIDTH; i=i+1) begin - if (ram_en) begin - A_DO_out[i] <= memory[fifo_rdaddr+i]; - end - end - end - // TDP push port B - always @(posedge fifo_wrclk) - begin - for (i=0; i < B_WIDTH; i=i+1) begin - if (ram_we && B_BM[i]) - memory[fifo_wraddr+i] <= B_DI[i]; - end - end - end - endgenerate - - // Optional output register - generate - if (A_DO_REG) begin - always @(posedge fifo_rdclk) begin - A_DO_reg <= A_DO_out; - end - assign A_DO = A_DO_reg; - end - else begin - assign A_DO = A_DO_out; - end - if (B_DO_REG) begin - always @(posedge fifo_rdclk) begin - B_DO_reg <= B_DO_out; - end - assign B_DO = B_DO_reg; - end - else begin - assign B_DO = B_DO_out; - end - endgenerate -endmodule - -// Models of the LUT2 tree primitives -module CC_L2T4( - output O, - input I0, I1, I2, I3 -); - parameter [3:0] INIT_L00 = 4'b0000; - parameter [3:0] INIT_L01 = 4'b0000; - parameter [3:0] INIT_L10 = 4'b0000; - - wire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0]; - wire l00 = I0 ? l00_s1[1] : l00_s1[0]; - - wire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0]; - wire l01 = I2 ? l01_s1[1] : l01_s1[0]; - - wire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0]; - assign O = l00 ? l10_s1[1] : l10_s1[0]; - -endmodule - - -module CC_L2T5( - output O, - input I0, I1, I2, I3, I4 -); - parameter [3:0] INIT_L02 = 4'b0000; - parameter [3:0] INIT_L03 = 4'b0000; - parameter [3:0] INIT_L11 = 4'b0000; - parameter [3:0] INIT_L20 = 4'b0000; - - wire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0]; - wire l02 = I0 ? l02_s1[1] : l02_s1[0]; - - wire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0]; - wire l03 = I2 ? l03_s1[1] : l03_s1[0]; - - wire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0]; - wire l11 = l02 ? l11_s1[1] : l11_s1[0]; - - wire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0]; - assign O = I4 ? l20_s1[1] : l20_s1[0]; - -endmodule +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +`timescale 1ps/1ps + +module CC_IBUF #( + parameter PIN_NAME = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter [0:0] PULLUP = 1'bx, + parameter [0:0] PULLDOWN = 1'bx, + parameter [0:0] KEEPER = 1'bx, + parameter [0:0] SCHMITT_TRIGGER = 1'bx, + // IOSEL + parameter [3:0] DELAY_IBF = 1'bx, + parameter [0:0] FF_IBF = 1'bx +)( + (* iopad_external_pin *) + input I, + output Y +); + assign Y = I; + +endmodule + + +module CC_OBUF #( + parameter PIN_NAME = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter DRIVE = "UNDEFINED", + parameter SLEW = "UNDEFINED", + // IOSEL + parameter [3:0] DELAY_OBF = 1'bx, + parameter [0:0] FF_OBF = 1'bx +)( + input A, + (* iopad_external_pin *) + output O +); + assign O = A; + +endmodule + + +module CC_TOBUF #( + parameter PIN_NAME = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter DRIVE = "UNDEFINED", + parameter SLEW = "UNDEFINED", + parameter [0:0] PULLUP = 1'bx, + parameter [0:0] PULLDOWN = 1'bx, + parameter [0:0] KEEPER = 1'bx, + // IOSEL + parameter [3:0] DELAY_OBF = 1'bx, + parameter [0:0] FF_OBF = 1'bx +)( + input A, T, + (* iopad_external_pin *) + output O +); + assign O = T ? 1'bz : A; + +endmodule + + +module CC_IOBUF #( + parameter PIN_NAME = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter DRIVE = "UNDEFINED", + parameter SLEW = "UNDEFINED", + parameter [0:0] PULLUP = 1'bx, + parameter [0:0] PULLDOWN = 1'bx, + parameter [0:0] KEEPER = 1'bx, + parameter [0:0] SCHMITT_TRIGGER = 1'bx, + // IOSEL + parameter [3:0] DELAY_IBF = 1'bx, + parameter [3:0] DELAY_OBF = 1'bx, + parameter [0:0] FF_IBF = 1'bx, + parameter [0:0] FF_OBF = 1'bx +)( + input A, T, + output Y, + (* iopad_external_pin *) + inout IO +); + assign IO = T ? 1'bz : A; + assign Y = IO; + +endmodule + + +module CC_LVDS_IBUF #( + parameter PIN_NAME_P = "UNPLACED", + parameter PIN_NAME_N = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter [0:0] LVDS_RTERM = 1'bx, + // IOSEL + parameter [3:0] DELAY_IBF = 1'bx, + parameter [0:0] FF_IBF = 1'bx +)( + (* iopad_external_pin *) + input I_P, I_N, + output Y +); + assign Y = I_P; + +endmodule + + +module CC_LVDS_OBUF #( + parameter PIN_NAME_P = "UNPLACED", + parameter PIN_NAME_N = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter [0:0] LVDS_BOOST = 1'bx, + // IOSEL + parameter [3:0] DELAY_OBF = 1'bx, + parameter [0:0] FF_OBF = 1'bx +)( + input A, + (* iopad_external_pin *) + output O_P, O_N +); + assign O_P = A; + assign O_N = ~A; + +endmodule + + +module CC_LVDS_TOBUF #( + parameter PIN_NAME_P = "UNPLACED", + parameter PIN_NAME_N = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter [0:0] LVDS_BOOST = 1'bx, + // IOSEL + parameter [3:0] DELAY_OBF = 1'bx, + parameter [0:0] FF_OBF = 1'bx +)( + input A, T, + (* iopad_external_pin *) + output O_P, O_N +); + assign O_P = T ? 1'bz : A; + assign O_N = T ? 1'bz : ~A; + +endmodule + + +module CC_LVDS_IOBUF #( + parameter PIN_NAME_P = "UNPLACED", + parameter PIN_NAME_N = "UNPLACED", + parameter V_IO = "UNDEFINED", + parameter [0:0] LVDS_RTERM = 1'bx, + parameter [0:0] LVDS_BOOST = 1'bx, + // IOSEL + parameter [3:0] DELAY_IBF = 1'bx, + parameter [3:0] DELAY_OBF = 1'bx, + parameter [0:0] FF_IBF = 1'bx, + parameter [0:0] FF_OBF = 1'bx +)( + input A, T, + (* iopad_external_pin *) + inout IO_P, IO_N, + output Y +); + assign IO_P = T ? 1'bz : A; + assign IO_N = T ? 1'bz : ~A; + assign Y = IO_P; + +endmodule + + +module CC_IDDR #( + parameter [0:0] CLK_INV = 1'b0 +)( + input D, + (* clkbuf_sink *) + input CLK, + output reg Q0, Q1 +); + wire clk; + assign clk = (CLK_INV) ? ~CLK : CLK; + + always @(posedge clk) + begin + Q0 <= D; + end + + always @(negedge clk) + begin + Q1 <= D; + end + +endmodule + + +module CC_ODDR #( + parameter [0:0] CLK_INV = 1'b0 +)( + input D0, + input D1, + (* clkbuf_sink *) + input CLK, + (* clkbuf_sink *) + input DDR, + output Q +); + wire clk; + assign clk = (CLK_INV) ? ~CLK : CLK; + + reg q0, q1; + assign Q = (DDR) ? q0 : q1; + + always @(posedge clk) + begin + q0 <= D0; + end + + always @(negedge clk) + begin + q1 <= D1; + end + +endmodule + + +module CC_DFF #( + parameter [0:0] CLK_INV = 1'b0, + parameter [0:0] EN_INV = 1'b0, + parameter [0:0] SR_INV = 1'b0, + parameter [0:0] SR_VAL = 1'b0, + parameter [0:0] INIT = 1'bx +)( + input D, + (* clkbuf_sink *) + input CLK, + input EN, + input SR, + output reg Q +); + wire clk, en, sr; + assign clk = (CLK_INV) ? ~CLK : CLK; + assign en = (EN_INV) ? ~EN : EN; + assign sr = (SR_INV) ? ~SR : SR; + + initial Q = INIT; + + always @(posedge clk or posedge sr) + begin + if (sr) begin + Q <= SR_VAL; + end + else if (en) begin + Q <= D; + end + end + +endmodule + + +module CC_DLT #( + parameter [0:0] G_INV = 1'b0, + parameter [0:0] SR_INV = 1'b0, + parameter [0:0] SR_VAL = 1'b0, + parameter [0:0] INIT = 1'bx +)( + input D, + input G, + input SR, + output reg Q +); + wire en, sr; + assign en = (G_INV) ? ~G : G; + assign sr = (SR_INV) ? ~SR : SR; + + initial Q = INIT; + + always @(*) + begin + if (sr) begin + Q = SR_VAL; + end + else if (en) begin + Q = D; + end + end + +endmodule + + +module CC_LUT1 ( + output O, + input I0 +); + parameter [1:0] INIT = 0; + + assign O = I0 ? INIT[1] : INIT[0]; + +endmodule + + +module CC_LUT2 ( + output O, + input I0, I1 +); + parameter [3:0] INIT = 0; + + wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; + assign O = I0 ? s1[1] : s1[0]; + +endmodule + + +module CC_LUT3 ( + output O, + input I0, I1, I2 +); + parameter [7:0] INIT = 0; + + wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; + +endmodule + + +module CC_LUT4 ( + output O, + input I0, I1, I2, I3 +); + parameter [15:0] INIT = 0; + + wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; + +endmodule + + +module CC_MX2 ( + input D0, D1, + input S0, + output Y +); + assign Y = S0 ? D1 : D0; + +endmodule + + +module CC_MX4 ( + input D0, D1, D2, D3, + input S0, S1, + output Y +); + assign Y = S1 ? (S0 ? D3 : D2) : + (S0 ? D1 : D0); + +endmodule + + +module CC_MX8 ( + input D0, D1, D2, D3, + input D4, D5, D6, D7, + input S0, S1, S2, + output Y +); + assign Y = S2 ? (S1 ? (S0 ? D7 : D6) : + (S0 ? D5 : D4)) : + (S1 ? (S0 ? D3 : D2) : + (S0 ? D1 : D0)); + +endmodule + + +module CC_ADDF ( + input A, B, CI, + output CO, S +); + assign {CO, S} = A + B + CI; + +endmodule + + +module CC_MULT #( + parameter A_WIDTH = 0, + parameter B_WIDTH = 0, + parameter P_WIDTH = 0 +)( + input signed [A_WIDTH-1:0] A, + input signed [B_WIDTH-1:0] B, + output reg signed [P_WIDTH-1:0] P +); + always @(*) + begin + P = A * B; + end +endmodule + + +module CC_BUFG ( + input I, + (* clkbuf_driver *) + output O +); + assign O = I; + +endmodule + + +module CC_BRAM_20K ( + output [19:0] A_DO, + output [19:0] B_DO, + output ECC_1B_ERR, + output ECC_2B_ERR, + (* clkbuf_sink *) + input A_CLK, + (* clkbuf_sink *) + input B_CLK, + input A_EN, + input B_EN, + input A_WE, + input B_WE, + input [15:0] A_ADDR, + input [15:0] B_ADDR, + input [19:0] A_DI, + input [19:0] B_DI, + input [19:0] A_BM, + input [19:0] B_BM +); + // Location format: D(0..N-1)(0..N-1)X(0..3)Y(0..7)Z(0..1) or UNPLACED + parameter LOC = "UNPLACED"; + + // Port Widths + parameter A_RD_WIDTH = 0; + parameter B_RD_WIDTH = 0; + parameter A_WR_WIDTH = 0; + parameter B_WR_WIDTH = 0; + + // RAM and Write Modes + parameter RAM_MODE = "SDP"; + parameter A_WR_MODE = "NO_CHANGE"; + parameter B_WR_MODE = "NO_CHANGE"; + + // Inverting Control Pins + parameter A_CLK_INV = 1'b0; + parameter B_CLK_INV = 1'b0; + parameter A_EN_INV = 1'b0; + parameter B_EN_INV = 1'b0; + parameter A_WE_INV = 1'b0; + parameter B_WE_INV = 1'b0; + + // Output Register + parameter A_DO_REG = 1'b0; + parameter B_DO_REG = 1'b0; + + // Error Checking and Correction + parameter ECC_EN = 1'b0; + + // RAM Contents + parameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + + localparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH; + localparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH; + + integer i, k; + + // 512 x 40 bit + reg [20479:0] memory = 20480'b0; + + initial begin + // Check parameters + if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin + $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); + $finish(); + end + if ((A_WR_MODE != "WRITE_THROUGH") && (A_WR_MODE != "NO_CHANGE")) begin + $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); + $finish(); + end + if ((RAM_MODE == "SDP") && (A_WR_MODE == "WRITE_THROUGH")) begin + $display("ERROR: %s is not supported in %s mode.", A_WR_MODE, RAM_MODE); + $finish(); + end + if (ECC_EN != 1'b0) begin + $display("WARNING: ECC feature not supported in simulation."); + end + if ((ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (WIDTH_MODE_A != 40)) begin + $display("ERROR: Illegal ECC Port configuration. Must be SDP 40 bit, but is %s %d.", RAM_MODE, WIDTH_MODE_A); + $finish(); + end + if ((WIDTH_MODE_A == 40) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port A width of 40 bits is only supported in SDP mode."); + $finish(); + end + if ((WIDTH_MODE_B == 40) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port B width of 40 bits is only supported in SDP mode."); + $finish(); + end + if ((WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) && + (WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin + $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A); + $finish(); + end + if ((WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) && + (WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin + $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, WIDTH_MODE_B); + $finish(); + end + // RAM initialization + memory[320*0+319:320*0] = INIT_00; + memory[320*1+319:320*1] = INIT_01; + memory[320*2+319:320*2] = INIT_02; + memory[320*3+319:320*3] = INIT_03; + memory[320*4+319:320*4] = INIT_04; + memory[320*5+319:320*5] = INIT_05; + memory[320*6+319:320*6] = INIT_06; + memory[320*7+319:320*7] = INIT_07; + memory[320*8+319:320*8] = INIT_08; + memory[320*9+319:320*9] = INIT_09; + memory[320*10+319:320*10] = INIT_0A; + memory[320*11+319:320*11] = INIT_0B; + memory[320*12+319:320*12] = INIT_0C; + memory[320*13+319:320*13] = INIT_0D; + memory[320*14+319:320*14] = INIT_0E; + memory[320*15+319:320*15] = INIT_0F; + memory[320*16+319:320*16] = INIT_10; + memory[320*17+319:320*17] = INIT_11; + memory[320*18+319:320*18] = INIT_12; + memory[320*19+319:320*19] = INIT_13; + memory[320*20+319:320*20] = INIT_14; + memory[320*21+319:320*21] = INIT_15; + memory[320*22+319:320*22] = INIT_16; + memory[320*23+319:320*23] = INIT_17; + memory[320*24+319:320*24] = INIT_18; + memory[320*25+319:320*25] = INIT_19; + memory[320*26+319:320*26] = INIT_1A; + memory[320*27+319:320*27] = INIT_1B; + memory[320*28+319:320*28] = INIT_1C; + memory[320*29+319:320*29] = INIT_1D; + memory[320*30+319:320*30] = INIT_1E; + memory[320*31+319:320*31] = INIT_1F; + memory[320*32+319:320*32] = INIT_20; + memory[320*33+319:320*33] = INIT_21; + memory[320*34+319:320*34] = INIT_22; + memory[320*35+319:320*35] = INIT_23; + memory[320*36+319:320*36] = INIT_24; + memory[320*37+319:320*37] = INIT_25; + memory[320*38+319:320*38] = INIT_26; + memory[320*39+319:320*39] = INIT_27; + memory[320*40+319:320*40] = INIT_28; + memory[320*41+319:320*41] = INIT_29; + memory[320*42+319:320*42] = INIT_2A; + memory[320*43+319:320*43] = INIT_2B; + memory[320*44+319:320*44] = INIT_2C; + memory[320*45+319:320*45] = INIT_2D; + memory[320*46+319:320*46] = INIT_2E; + memory[320*47+319:320*47] = INIT_2F; + memory[320*48+319:320*48] = INIT_30; + memory[320*49+319:320*49] = INIT_31; + memory[320*50+319:320*50] = INIT_32; + memory[320*51+319:320*51] = INIT_33; + memory[320*52+319:320*52] = INIT_34; + memory[320*53+319:320*53] = INIT_35; + memory[320*54+319:320*54] = INIT_36; + memory[320*55+319:320*55] = INIT_37; + memory[320*56+319:320*56] = INIT_38; + memory[320*57+319:320*57] = INIT_39; + memory[320*58+319:320*58] = INIT_3A; + memory[320*59+319:320*59] = INIT_3B; + memory[320*60+319:320*60] = INIT_3C; + memory[320*61+319:320*61] = INIT_3D; + memory[320*62+319:320*62] = INIT_3E; + memory[320*63+319:320*63] = INIT_3F; + end + + // Signal inversion + wire clka = A_CLK_INV ^ A_CLK; + wire clkb = B_CLK_INV ^ B_CLK; + wire ena = A_EN_INV ^ A_EN; + wire enb = B_EN_INV ^ B_EN; + wire wea = A_WE_INV ^ A_WE; + wire web = B_WE_INV ^ B_WE; + + // Internal signals + wire [15:0] addra; + wire [15:0] addrb; + reg [19:0] A_DO_out = 0, A_DO_reg = 0; + reg [19:0] B_DO_out = 0, B_DO_reg = 0; + + generate + if (RAM_MODE == "SDP") begin + // Port A (write) + if (A_WR_WIDTH == 40) begin + assign addra = A_ADDR[15:7]*40; + end + // Port B (read) + if (B_RD_WIDTH == 40) begin + assign addrb = B_ADDR[15:7]*40; + end + end + else if (RAM_MODE == "TDP") begin + // Port A + if (WIDTH_MODE_A <= 1) begin + wire [15:0] tmpa = {2'b0, A_ADDR[15:7], A_ADDR[5:1]}; + assign addra = tmpa + (tmpa/4); + end + else if (WIDTH_MODE_A <= 2) begin + wire [15:0] tmpa = {3'b0, A_ADDR[15:7], A_ADDR[5:2]}; + assign addra = tmpa*2 + (tmpa/2); + end + else if (WIDTH_MODE_A <= 5) begin + assign addra = {4'b0, A_ADDR[15:7], A_ADDR[5:3]}*5; + end + else if (WIDTH_MODE_A <= 10) begin + assign addra = {5'b0, A_ADDR[15:7], A_ADDR[5:4]}*10; + end + else if (WIDTH_MODE_A <= 20) begin + assign addra = {6'b0, A_ADDR[15:7], A_ADDR[5]}*20; + end + // Port B + if (WIDTH_MODE_B <= 1) begin + wire [15:0] tmpb = {2'b0, B_ADDR[15:7], B_ADDR[5:1]}; + assign addrb = tmpb + (tmpb/4); + end + else if (WIDTH_MODE_B <= 2) begin + wire [15:0] tmpb = {3'b0, B_ADDR[15:7], B_ADDR[5:2]}; + assign addrb = tmpb*2 + (tmpb/2); + end + else if (WIDTH_MODE_B <= 5) begin + assign addrb = {4'b0, B_ADDR[15:7], B_ADDR[5:3]}*5; + end + else if (WIDTH_MODE_B <= 10) begin + assign addrb = {5'b0, B_ADDR[15:7], B_ADDR[5:4]}*10; + end + else if (WIDTH_MODE_B <= 20) begin + assign addrb = {6'b0, B_ADDR[15:7], B_ADDR[5]}*20; + end + end + endgenerate + + generate + if (RAM_MODE == "SDP") begin + // SDP write port + always @(posedge clka) + begin + for (k=0; k < A_WR_WIDTH; k=k+1) begin + if (k < 20) begin + if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k]; + end + else begin // use both ports + if (ena && wea && B_BM[k-20]) memory[addra+k] <= B_DI[k-20]; + end + end + end + // SDP read port + always @(posedge clkb) + begin + for (k=0; k < B_RD_WIDTH; k=k+1) begin + if (k < 20) begin + if (enb) A_DO_out[k] <= memory[addrb+k]; + end + else begin // use both ports + if (enb) B_DO_out[k-20] <= memory[addrb+k]; + end + end + end + end + else if (RAM_MODE == "TDP") begin + // TDP port A + always @(posedge clka) + begin + for (i=0; i < WIDTH_MODE_A; i=i+1) begin + if (ena && wea && A_BM[i]) memory[addra+i] <= A_DI[i]; + + if (A_WR_MODE == "NO_CHANGE") begin + if (ena && !wea) A_DO_out[i] <= memory[addra+i]; + end + else if (A_WR_MODE == "WRITE_THROUGH") begin + if (ena) begin + if (wea && A_BM[i]) begin + A_DO_out[i] <= A_DI[i]; + end + else begin + A_DO_out[i] <= memory[addra+i]; + end + end + end + end + end + // TDP port B + always @(posedge clkb) + begin + for (i=0; i < WIDTH_MODE_B; i=i+1) begin + if (enb && web && B_BM[i]) memory[addrb+i] <= B_DI[i]; + + if (B_WR_MODE == "NO_CHANGE") begin + if (enb && !web) B_DO_out[i] <= memory[addrb+i]; + end + else if (B_WR_MODE == "WRITE_THROUGH") begin + if (enb) begin + if (web && B_BM[i]) begin + B_DO_out[i] <= B_DI[i]; + end + else begin + B_DO_out[i] <= memory[addrb+i]; + end + end + end + end + end + end + endgenerate + + // Optional output register + generate + if (A_DO_REG) begin + always @(posedge clka) begin + A_DO_reg <= A_DO_out; + end + assign A_DO = A_DO_reg; + end + else begin + assign A_DO = A_DO_out; + end + if (B_DO_REG) begin + always @(posedge clkb) begin + B_DO_reg <= B_DO_out; + end + assign B_DO = B_DO_reg; + end + else begin + assign B_DO = B_DO_out; + end + endgenerate +endmodule + + +module CC_BRAM_40K ( + output [39:0] A_DO, + output [39:0] B_DO, + output A_ECC_1B_ERR, + output B_ECC_1B_ERR, + output A_ECC_2B_ERR, + output B_ECC_2B_ERR, + output reg A_CO = 0, + output reg B_CO = 0, + (* clkbuf_sink *) + input A_CLK, + (* clkbuf_sink *) + input B_CLK, + input A_EN, + input B_EN, + input A_WE, + input B_WE, + input [15:0] A_ADDR, + input [15:0] B_ADDR, + input [39:0] A_DI, + input [39:0] B_DI, + input [39:0] A_BM, + input [39:0] B_BM, + input A_CI, + input B_CI +); + // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED + parameter LOC = "UNPLACED"; + parameter CAS = "NONE"; // NONE, UPPER, LOWER + + // Port Widths + parameter A_RD_WIDTH = 0; + parameter B_RD_WIDTH = 0; + parameter A_WR_WIDTH = 0; + parameter B_WR_WIDTH = 0; + + // RAM and Write Modes + parameter RAM_MODE = "SDP"; + parameter A_WR_MODE = "NO_CHANGE"; + parameter B_WR_MODE = "NO_CHANGE"; + + // Inverting Control Pins + parameter A_CLK_INV = 1'b0; + parameter B_CLK_INV = 1'b0; + parameter A_EN_INV = 1'b0; + parameter B_EN_INV = 1'b0; + parameter A_WE_INV = 1'b0; + parameter B_WE_INV = 1'b0; + + // Output Register + parameter A_DO_REG = 1'b0; + parameter B_DO_REG = 1'b0; + + // Error Checking and Correction + parameter A_ECC_EN = 1'b0; + parameter B_ECC_EN = 1'b0; + + parameter INIT_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + + localparam WIDTH_MODE_A = (A_RD_WIDTH > A_WR_WIDTH) ? A_RD_WIDTH : A_WR_WIDTH; + localparam WIDTH_MODE_B = (B_RD_WIDTH > B_WR_WIDTH) ? B_RD_WIDTH : B_WR_WIDTH; + + integer i, k; + + // 512 x 80 bit + reg [40959:0] memory = 40960'b0; + + initial begin + // Check parameters + if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin + $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); + $finish(); + end + if ((A_WR_MODE != "WRITE_THROUGH") && (A_WR_MODE != "NO_CHANGE")) begin + $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); + $finish(); + end + if ((RAM_MODE == "SDP") && (A_WR_MODE == "WRITE_THROUGH")) begin + $display("ERROR: %s is not supported in %s mode.", A_WR_MODE, RAM_MODE); + $finish(); + end + if ((A_ECC_EN != 1'b0) || (B_ECC_EN != 1'b0)) begin + $display("WARNING: ECC feature not supported in simulation."); + end + if ((A_ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (WIDTH_MODE_A != 40)) begin + $display("ERROR: Illegal ECC Port A configuration. Must be SDP 40 bit, but is %s %d.", RAM_MODE, WIDTH_MODE_A); + $finish(); + end + if ((WIDTH_MODE_A == 80) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port A width of 80 bits is only supported in SDP mode."); + $finish(); + end + if ((WIDTH_MODE_B == 80) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port B width of 80 bits is only supported in SDP mode."); + $finish(); + end + if ((WIDTH_MODE_A != 80) && (WIDTH_MODE_A != 40) && (WIDTH_MODE_A != 20) && (WIDTH_MODE_A != 10) && + (WIDTH_MODE_A != 5) && (WIDTH_MODE_A != 2) && (WIDTH_MODE_A != 1) && (WIDTH_MODE_A != 0)) begin + $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, WIDTH_MODE_A); + $finish(); + end + if ((WIDTH_MODE_B != 80) && (WIDTH_MODE_B != 40) && (WIDTH_MODE_B != 20) && (WIDTH_MODE_B != 10) && + (WIDTH_MODE_B != 5) && (WIDTH_MODE_B != 2) && (WIDTH_MODE_B != 1) && (WIDTH_MODE_B != 0)) begin + $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, WIDTH_MODE_B); + $finish(); + end + if ((CAS != "NONE") && ((WIDTH_MODE_A > 1) || (WIDTH_MODE_B > 1))) begin + $display("ERROR: Cascade feature only supported in 1 bit data width mode."); + $finish(); + end + if ((CAS != "NONE") && (RAM_MODE != "TDP")) begin + $display("ERROR: Cascade feature only supported in TDP mode."); + $finish(); + end + // RAM initialization + memory[320*0+319:320*0] = INIT_00; + memory[320*1+319:320*1] = INIT_01; + memory[320*2+319:320*2] = INIT_02; + memory[320*3+319:320*3] = INIT_03; + memory[320*4+319:320*4] = INIT_04; + memory[320*5+319:320*5] = INIT_05; + memory[320*6+319:320*6] = INIT_06; + memory[320*7+319:320*7] = INIT_07; + memory[320*8+319:320*8] = INIT_08; + memory[320*9+319:320*9] = INIT_09; + memory[320*10+319:320*10] = INIT_0A; + memory[320*11+319:320*11] = INIT_0B; + memory[320*12+319:320*12] = INIT_0C; + memory[320*13+319:320*13] = INIT_0D; + memory[320*14+319:320*14] = INIT_0E; + memory[320*15+319:320*15] = INIT_0F; + memory[320*16+319:320*16] = INIT_10; + memory[320*17+319:320*17] = INIT_11; + memory[320*18+319:320*18] = INIT_12; + memory[320*19+319:320*19] = INIT_13; + memory[320*20+319:320*20] = INIT_14; + memory[320*21+319:320*21] = INIT_15; + memory[320*22+319:320*22] = INIT_16; + memory[320*23+319:320*23] = INIT_17; + memory[320*24+319:320*24] = INIT_18; + memory[320*25+319:320*25] = INIT_19; + memory[320*26+319:320*26] = INIT_1A; + memory[320*27+319:320*27] = INIT_1B; + memory[320*28+319:320*28] = INIT_1C; + memory[320*29+319:320*29] = INIT_1D; + memory[320*30+319:320*30] = INIT_1E; + memory[320*31+319:320*31] = INIT_1F; + memory[320*32+319:320*32] = INIT_20; + memory[320*33+319:320*33] = INIT_21; + memory[320*34+319:320*34] = INIT_22; + memory[320*35+319:320*35] = INIT_23; + memory[320*36+319:320*36] = INIT_24; + memory[320*37+319:320*37] = INIT_25; + memory[320*38+319:320*38] = INIT_26; + memory[320*39+319:320*39] = INIT_27; + memory[320*40+319:320*40] = INIT_28; + memory[320*41+319:320*41] = INIT_29; + memory[320*42+319:320*42] = INIT_2A; + memory[320*43+319:320*43] = INIT_2B; + memory[320*44+319:320*44] = INIT_2C; + memory[320*45+319:320*45] = INIT_2D; + memory[320*46+319:320*46] = INIT_2E; + memory[320*47+319:320*47] = INIT_2F; + memory[320*48+319:320*48] = INIT_30; + memory[320*49+319:320*49] = INIT_31; + memory[320*50+319:320*50] = INIT_32; + memory[320*51+319:320*51] = INIT_33; + memory[320*52+319:320*52] = INIT_34; + memory[320*53+319:320*53] = INIT_35; + memory[320*54+319:320*54] = INIT_36; + memory[320*55+319:320*55] = INIT_37; + memory[320*56+319:320*56] = INIT_38; + memory[320*57+319:320*57] = INIT_39; + memory[320*58+319:320*58] = INIT_3A; + memory[320*59+319:320*59] = INIT_3B; + memory[320*60+319:320*60] = INIT_3C; + memory[320*61+319:320*61] = INIT_3D; + memory[320*62+319:320*62] = INIT_3E; + memory[320*63+319:320*63] = INIT_3F; + memory[320*64+319:320*64] = INIT_40; + memory[320*65+319:320*65] = INIT_41; + memory[320*66+319:320*66] = INIT_42; + memory[320*67+319:320*67] = INIT_43; + memory[320*68+319:320*68] = INIT_44; + memory[320*69+319:320*69] = INIT_45; + memory[320*70+319:320*70] = INIT_46; + memory[320*71+319:320*71] = INIT_47; + memory[320*72+319:320*72] = INIT_48; + memory[320*73+319:320*73] = INIT_49; + memory[320*74+319:320*74] = INIT_4A; + memory[320*75+319:320*75] = INIT_4B; + memory[320*76+319:320*76] = INIT_4C; + memory[320*77+319:320*77] = INIT_4D; + memory[320*78+319:320*78] = INIT_4E; + memory[320*79+319:320*79] = INIT_4F; + memory[320*80+319:320*80] = INIT_50; + memory[320*81+319:320*81] = INIT_51; + memory[320*82+319:320*82] = INIT_52; + memory[320*83+319:320*83] = INIT_53; + memory[320*84+319:320*84] = INIT_54; + memory[320*85+319:320*85] = INIT_55; + memory[320*86+319:320*86] = INIT_56; + memory[320*87+319:320*87] = INIT_57; + memory[320*88+319:320*88] = INIT_58; + memory[320*89+319:320*89] = INIT_59; + memory[320*90+319:320*90] = INIT_5A; + memory[320*91+319:320*91] = INIT_5B; + memory[320*92+319:320*92] = INIT_5C; + memory[320*93+319:320*93] = INIT_5D; + memory[320*94+319:320*94] = INIT_5E; + memory[320*95+319:320*95] = INIT_5F; + memory[320*96+319:320*96] = INIT_60; + memory[320*97+319:320*97] = INIT_61; + memory[320*98+319:320*98] = INIT_62; + memory[320*99+319:320*99] = INIT_63; + memory[320*100+319:320*100] = INIT_64; + memory[320*101+319:320*101] = INIT_65; + memory[320*102+319:320*102] = INIT_66; + memory[320*103+319:320*103] = INIT_67; + memory[320*104+319:320*104] = INIT_68; + memory[320*105+319:320*105] = INIT_69; + memory[320*106+319:320*106] = INIT_6A; + memory[320*107+319:320*107] = INIT_6B; + memory[320*108+319:320*108] = INIT_6C; + memory[320*109+319:320*109] = INIT_6D; + memory[320*110+319:320*110] = INIT_6E; + memory[320*111+319:320*111] = INIT_6F; + memory[320*112+319:320*112] = INIT_70; + memory[320*113+319:320*113] = INIT_71; + memory[320*114+319:320*114] = INIT_72; + memory[320*115+319:320*115] = INIT_73; + memory[320*116+319:320*116] = INIT_74; + memory[320*117+319:320*117] = INIT_75; + memory[320*118+319:320*118] = INIT_76; + memory[320*119+319:320*119] = INIT_77; + memory[320*120+319:320*120] = INIT_78; + memory[320*121+319:320*121] = INIT_79; + memory[320*122+319:320*122] = INIT_7A; + memory[320*123+319:320*123] = INIT_7B; + memory[320*124+319:320*124] = INIT_7C; + memory[320*125+319:320*125] = INIT_7D; + memory[320*126+319:320*126] = INIT_7E; + memory[320*127+319:320*127] = INIT_7F; + end + + // Signal inversion + wire clka = A_CLK_INV ^ A_CLK; + wire clkb = B_CLK_INV ^ B_CLK; + wire ena = A_EN_INV ^ A_EN; + wire enb = B_EN_INV ^ B_EN; + wire wea = A_WE_INV ^ A_WE; + wire web = B_WE_INV ^ B_WE; + + // Internal signals + wire [15:0] addra; + wire [15:0] addrb; + reg [39:0] A_DO_out = 0, A_DO_reg = 0; + reg [39:0] B_DO_out = 0, B_DO_reg = 0; + + generate + if (RAM_MODE == "SDP") begin + // Port A (write) + if (A_WR_WIDTH == 80) begin + assign addra = A_ADDR[15:7]*80; + end + // Port B (read) + if (B_RD_WIDTH == 80) begin + assign addrb = B_ADDR[15:7]*80; + end + end + else if (RAM_MODE == "TDP") begin + // Port A + if (WIDTH_MODE_A <= 1) begin + wire [15:0] tmpa = {1'b0, A_ADDR[15:1]}; + assign addra = tmpa + (tmpa/4); + end + else if (WIDTH_MODE_A <= 2) begin + wire [15:0] tmpa = {2'b0, A_ADDR[15:2]}; + assign addra = tmpa*2 + (tmpa/2); + end + else if (WIDTH_MODE_A <= 5) begin + assign addra = {3'b0, A_ADDR[15:3]}*5; + end + else if (WIDTH_MODE_A <= 10) begin + assign addra = {4'b0, A_ADDR[15:4]}*10; + end + else if (WIDTH_MODE_A <= 20) begin + assign addra = {5'b0, A_ADDR[15:5]}*20; + end + else if (WIDTH_MODE_A <= 40) begin + assign addra = {6'b0, A_ADDR[15:6]}*40; + end + // Port B + if (WIDTH_MODE_B <= 1) begin + wire [15:0] tmpb = {1'b0, B_ADDR[15:1]}; + assign addrb = tmpb + (tmpb/4); + end + else if (WIDTH_MODE_B <= 2) begin + wire [15:0] tmpb = {2'b0, B_ADDR[15:2]}; + assign addrb = tmpb*2 + (tmpb/2); + end + else if (WIDTH_MODE_B <= 5) begin + assign addrb = {3'b0, B_ADDR[15:3]}*5; + end + else if (WIDTH_MODE_B <= 10) begin + assign addrb = {4'b0, B_ADDR[15:4]}*10; + end + else if (WIDTH_MODE_B <= 20) begin + assign addrb = {5'b0, B_ADDR[15:5]}*20; + end + else if (WIDTH_MODE_B <= 40) begin + assign addrb = {6'b0, B_ADDR[15:6]}*40; + end + end + endgenerate + + generate + if (RAM_MODE == "SDP") begin + // SDP write port + always @(posedge clka) + begin + for (k=0; k < A_WR_WIDTH; k=k+1) begin + if (k < 40) begin + if (ena && wea && A_BM[k]) memory[addra+k] <= A_DI[k]; + end + else begin // use both ports + if (ena && wea && B_BM[k-40]) memory[addra+k] <= B_DI[k-40]; + end + end + end + // SDP read port + always @(posedge clkb) + begin + for (k=0; k < B_RD_WIDTH; k=k+1) begin + if (k < 40) begin + if (enb) A_DO_out[k] <= memory[addrb+k]; + end + else begin // use both ports + if (enb) B_DO_out[k-40] <= memory[addrb+k]; + end + end + end + end + else if (RAM_MODE == "TDP") begin + // {A,B}_ADDR[0]=0 selects lower, {A,B}_ADDR[0]=1 selects upper cascade memory + wire upper_sel_a = ((CAS == "UPPER") && (A_ADDR[0] == 1)); + wire lower_sel_a = ((CAS == "LOWER") && (A_ADDR[0] == 0)); + wire upper_sel_b = ((CAS == "UPPER") && (B_ADDR[0] == 1)); + wire lower_sel_b = ((CAS == "LOWER") && (B_ADDR[0] == 0)); + + reg dumm; + + // Cascade output port A + always @(*) + begin + if ((A_WR_MODE == "NO_CHANGE") && lower_sel_a) begin + A_CO = memory[addra]; + end + else if ((A_WR_MODE == "WRITE_THROUGH") && lower_sel_a) begin + A_CO = ((wea && A_BM[0]) ? (A_DI[0]) : (memory[addra])); + end + end + + // Cascade output port B + always @(*) + begin + if ((B_WR_MODE == "NO_CHANGE") && lower_sel_b) begin + B_CO = memory[addrb]; + end + else if ((B_WR_MODE == "WRITE_THROUGH") && lower_sel_b) begin + B_CO = ((web && B_BM[0]) ? (B_DI[0]) : (memory[addrb])); + end + end + + // TDP port A + always @(posedge clka) + begin + for (i=0; i < WIDTH_MODE_A; i=i+1) begin + if (upper_sel_a || lower_sel_a || (CAS == "NONE")) begin + if (ena && wea && A_BM[i]) + memory[addra+i] <= A_DI[i]; + end + + if (A_WR_MODE == "NO_CHANGE") begin + if (ena && !wea) begin + if (CAS == "UPPER") begin + A_DO_out[i] <= ((A_ADDR[0] == 1) ? (memory[addra+i]) : (A_CI)); + end + else if (CAS == "NONE") begin + A_DO_out[i] <= memory[addra+i]; + end + end + end + else if (A_WR_MODE == "WRITE_THROUGH") begin + if (ena) begin + if (CAS == "UPPER") begin + if (A_ADDR[0] == 1) begin + A_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i])); + end else begin + A_DO_out[i] <= A_CI; + end + end + else if (CAS == "NONE") begin + A_DO_out[i] <= ((wea && A_BM[i]) ? (A_DI[i]) : (memory[addra+i])); + end + end + end + end + end + // TDP port B + always @(posedge clkb) + begin + for (i=0; i < WIDTH_MODE_B; i=i+1) begin + if (upper_sel_b || lower_sel_b || (CAS == "NONE")) begin + if (enb && web && B_BM[i]) + memory[addrb+i] <= B_DI[i]; + end + + if (B_WR_MODE == "NO_CHANGE") begin + if (enb && !web) begin + if (CAS == "UPPER") begin + B_DO_out[i] <= ((B_ADDR[0] == 1) ? (memory[addrb+i]) : (B_CI)); + end + else if (CAS == "NONE") begin + B_DO_out[i] <= memory[addrb+i]; + end + end + end + else if (B_WR_MODE == "WRITE_THROUGH") begin + if (enb) begin + if (CAS == "UPPER") begin + if (B_ADDR[0] == 1) begin + B_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i])); + end else begin + B_DO_out[i] <= B_CI; + end + end + else if (CAS == "NONE") begin + B_DO_out[i] <= ((web && B_BM[i]) ? (B_DI[i]) : (memory[addrb+i])); + end + end + end + end + end + end + endgenerate + + // Optional output register + generate + if (A_DO_REG) begin + always @(posedge clka) begin + A_DO_reg <= A_DO_out; + end + assign A_DO = A_DO_reg; + end + else begin + assign A_DO = A_DO_out; + end + if (B_DO_REG) begin + always @(posedge clkb) begin + B_DO_reg <= B_DO_out; + end + assign B_DO = B_DO_reg; + end + else begin + assign B_DO = B_DO_out; + end + endgenerate +endmodule + +module CC_FIFO_40K ( + output A_ECC_1B_ERR, + output B_ECC_1B_ERR, + output A_ECC_2B_ERR, + output B_ECC_2B_ERR, + // FIFO pop port + output [39:0] A_DO, + output [39:0] B_DO, + (* clkbuf_sink *) + input A_CLK, + input A_EN, + // FIFO push port + input [39:0] A_DI, + input [39:0] B_DI, + input [39:0] A_BM, + input [39:0] B_BM, + (* clkbuf_sink *) + input B_CLK, + input B_EN, + input B_WE, + // FIFO control + input F_RST_N, + input [14:0] F_ALMOST_FULL_OFFSET, + input [14:0] F_ALMOST_EMPTY_OFFSET, + // FIFO status signals + output F_FULL, + output F_EMPTY, + output F_ALMOST_FULL, + output F_ALMOST_EMPTY, + output F_RD_ERROR, + output F_WR_ERROR, + output [15:0] F_RD_PTR, + output [15:0] F_WR_PTR +); + // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED + parameter LOC = "UNPLACED"; + + // Offset configuration + parameter DYN_STAT_SELECT = 1'b0; + parameter [14:0] ALMOST_FULL_OFFSET = 15'b0; + parameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0; + + // Port Widths + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + + // RAM and Write Modes + parameter RAM_MODE = "TDP"; // "TDP" or "SDP" + parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC" + + // Inverting Control Pins + parameter A_CLK_INV = 1'b0; + parameter B_CLK_INV = 1'b0; + parameter A_EN_INV = 1'b0; + parameter B_EN_INV = 1'b0; + parameter A_WE_INV = 1'b0; + parameter B_WE_INV = 1'b0; + + // Output Register + parameter A_DO_REG = 1'b0; + parameter B_DO_REG = 1'b0; + + // Error Checking and Correction + parameter A_ECC_EN = 1'b0; + parameter B_ECC_EN = 1'b0; + + integer i, k; + + // 512 x 80 bit + reg [40959:0] memory = 40960'b0; + + reg [15:0] counter_max; + reg [15:0] sram_depth; + localparam tp = (A_WIDTH == 1) ? 15 : + (A_WIDTH == 2) ? 14 : + (A_WIDTH == 5) ? 13 : + (A_WIDTH == 10) ? 12 : + (A_WIDTH == 20) ? 11 : + (A_WIDTH == 40) ? 10 : 9; + + initial begin + // Check parameters + if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin + $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); + $finish(); + end + if ((FIFO_MODE != "ASYNC") && (FIFO_MODE != "SYNC")) begin + $display("ERROR: Illegal FIFO MODE %d.", FIFO_MODE); + $finish(); + end + if ((RAM_MODE == "SDP") && (DYN_STAT_SELECT == 1)) begin + $display("ERROR: Dynamic offset configuration is not supported in %s mode.", RAM_MODE); + $finish(); + end + if ((RAM_MODE == "SDP") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin + $display("ERROR: SDP is ony supported in 80 bit mode."); + $finish(); + end + if ((A_WIDTH == 80) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port A width of 80 bits is only supported in SDP mode."); + $finish(); + end + if ((B_WIDTH == 80) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port B width of 80 bits is only supported in SDP mode."); + $finish(); + end + if ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) && + (A_WIDTH != 5) && (A_WIDTH != 2) && (A_WIDTH != 1) && (A_WIDTH != 0)) begin + $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, A_WIDTH); + $finish(); + end + if ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) && + (B_WIDTH != 5) && (B_WIDTH != 2) && (B_WIDTH != 1) && (B_WIDTH != 0)) begin + $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, B_WIDTH); + $finish(); + end + if (A_WIDTH != B_WIDTH) begin + $display("ERROR: The values of A_WIDTH and B_WIDTH must be equal."); + end + if ((A_ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (A_WIDTH != 40)) begin + $display("ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.", RAM_MODE, A_WIDTH); + $finish(); + end + // Set local parameters + if (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH + counter_max = 2 * 32*1024 - 1; + sram_depth = 32*1024; + end + else if (A_WIDTH == 2) begin + counter_max = 2 * 16*1024 - 1; + sram_depth = 16*1024; + end + else if (A_WIDTH == 5) begin + counter_max = 2 * 8*1024 - 1; + sram_depth = 8*1024; + end + else if (A_WIDTH == 10) begin + counter_max = 2 * 4*1024 - 1; + sram_depth = 4*1024; + end + else if (A_WIDTH == 20) begin + counter_max = 2 * 2*1024 - 1; + sram_depth = 2*1024; + end + else if (A_WIDTH == 40) begin + counter_max = 2 * 1*1024 - 1; + sram_depth = 1*1024; + end + else begin // 80 bit SDP + counter_max = 2 * 512 - 1; + sram_depth = 512; + end + end + + // Internal signals + wire fifo_rdclk = A_CLK ^ A_CLK_INV; + wire fifo_wrclk = (FIFO_MODE == "ASYNC") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV); + wire [15:0] almost_full_offset = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET : ALMOST_FULL_OFFSET; + wire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET; + reg [39:0] A_DO_out = 0, A_DO_reg = 0; + reg [39:0] B_DO_out = 0, B_DO_reg = 0; + + // Status signals + reg fifo_full; + reg fifo_empty; + reg fifo_almost_full; + reg fifo_almost_empty; + assign F_FULL = fifo_full; + assign F_EMPTY = fifo_empty; + assign F_ALMOST_FULL = fifo_almost_full; + assign F_ALMOST_EMPTY = fifo_almost_empty; + assign F_WR_ERROR = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV)); + assign F_RD_ERROR = (F_EMPTY && (A_EN ^ A_EN_INV)); + wire ram_we = (~F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV)); + wire ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV)); + + // Reset synchronizers + reg [1:0] aclk_reset_q, bclk_reset_q; + wire fifo_sync_rstn = aclk_reset_q; + wire fifo_async_wrrstn = bclk_reset_q; + wire fifo_async_rdrstn = aclk_reset_q; + + always @(posedge fifo_rdclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + aclk_reset_q <= 2'b0; + end + else begin + aclk_reset_q[1] <= aclk_reset_q[0]; + aclk_reset_q[0] <= 1'b1; + end + end + + always @(posedge fifo_wrclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + bclk_reset_q <= 2'b0; + end + else begin + bclk_reset_q[1] <= bclk_reset_q[0]; + bclk_reset_q[0] <= 1'b1; + end + end + + // Push/pop pointers + reg [15:0] rd_pointer, rd_pointer_int; + reg [15:0] wr_pointer, wr_pointer_int; + reg [15:0] rd_pointer_cmp, wr_pointer_cmp; + wire [15:0] rd_pointer_nxt; + wire [15:0] wr_pointer_nxt; + reg [15:0] fifo_rdaddr, rdaddr; + reg [15:0] fifo_wraddr, wraddr; + assign F_RD_PTR = fifo_rdaddr; + assign F_WR_PTR = fifo_wraddr; + + always @(posedge fifo_rdclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + rd_pointer <= 0; + rd_pointer_int <= 0; + end + else if (ram_en) begin + rd_pointer <= rd_pointer_nxt; + rd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0]; + end + end + + assign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1); + + always @(posedge fifo_wrclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + wr_pointer <= 0; + wr_pointer_int <= 0; + end + else if (ram_we) begin + wr_pointer <= wr_pointer_nxt; + wr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0]; + end + end + + assign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1); + + // Address synchronizers + reg [15:0] rd_pointer_sync, wr_pointer_sync; + reg [15:0] rd_pointer_sync_0, rd_pointer_sync_1; + reg [15:0] wr_pointer_sync_0, wr_pointer_sync_1; + + always @(posedge fifo_rdclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + wr_pointer_sync_0 <= 0; + wr_pointer_sync_1 <= 0; + end + else begin + wr_pointer_sync_0 <= wraddr; + wr_pointer_sync_1 <= wr_pointer_sync_0; + end + end + + always @(posedge fifo_wrclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + rd_pointer_sync_0 <= 0; + rd_pointer_sync_1 <= 0; + end + else begin + rd_pointer_sync_0 <= rdaddr; + rd_pointer_sync_1 <= rd_pointer_sync_0; + end + end + + always @(*) begin + fifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}}; + fifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}}; + + rdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]}; + wraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]}; + + if (FIFO_MODE == "ASYNC") + fifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] ); + else + fifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]); + + if (FIFO_MODE == "ASYNC") + fifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]); + else + fifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]); + + rd_pointer_cmp = (FIFO_MODE == "ASYNC") ? rd_pointer_sync : rd_pointer; + if (wr_pointer[tp] == rd_pointer_cmp[tp]) + fifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset)); + else + fifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset); + + wr_pointer_cmp = (FIFO_MODE == "ASYNC") ? wr_pointer_sync : wr_pointer; + if (wr_pointer_cmp[tp] == rd_pointer[tp]) + fifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset); + else + fifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset)); + end + + generate + always @(*) begin + wr_pointer_sync = 0; + rd_pointer_sync = 0; + for (i=tp; i >= 0; i=i-1) begin + if (i == tp) begin + wr_pointer_sync[i] = wr_pointer_sync_1[i]; + rd_pointer_sync[i] = rd_pointer_sync_1[i]; + end + else begin + wr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1]; + rd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1]; + end + end + end + if (RAM_MODE == "SDP") begin + // SDP push ports A+B + always @(posedge fifo_wrclk) + begin + for (k=0; k < A_WIDTH; k=k+1) begin + if (k < 40) begin + if (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k]; + end + else begin // use both ports + if (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40]; + end + end + end + // SDP pop ports A+B + always @(posedge fifo_rdclk) + begin + for (k=0; k < B_WIDTH; k=k+1) begin + if (k < 40) begin + if (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k]; + end + else begin // use both ports + if (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k]; + end + end + end + end + else if (RAM_MODE == "TDP") begin + // TDP pop port A + always @(posedge fifo_rdclk) + begin + for (i=0; i < A_WIDTH; i=i+1) begin + if (ram_en) begin + A_DO_out[i] <= memory[fifo_rdaddr+i]; + end + end + end + // TDP push port B + always @(posedge fifo_wrclk) + begin + for (i=0; i < B_WIDTH; i=i+1) begin + if (ram_we && B_BM[i]) + memory[fifo_wraddr+i] <= B_DI[i]; + end + end + end + endgenerate + + // Optional output register + generate + if (A_DO_REG) begin + always @(posedge fifo_rdclk) begin + A_DO_reg <= A_DO_out; + end + assign A_DO = A_DO_reg; + end + else begin + assign A_DO = A_DO_out; + end + if (B_DO_REG) begin + always @(posedge fifo_rdclk) begin + B_DO_reg <= B_DO_out; + end + assign B_DO = B_DO_reg; + end + else begin + assign B_DO = B_DO_out; + end + endgenerate +endmodule + +// Models of the LUT2 tree primitives +module CC_L2T4( + output O, + input I0, I1, I2, I3 +); + parameter [3:0] INIT_L00 = 4'b0000; + parameter [3:0] INIT_L01 = 4'b0000; + parameter [3:0] INIT_L10 = 4'b0000; + + wire [1:0] l00_s1 = I1 ? INIT_L00[3:2] : INIT_L00[1:0]; + wire l00 = I0 ? l00_s1[1] : l00_s1[0]; + + wire [1:0] l01_s1 = I3 ? INIT_L01[3:2] : INIT_L01[1:0]; + wire l01 = I2 ? l01_s1[1] : l01_s1[0]; + + wire [1:0] l10_s1 = l01 ? INIT_L10[3:2] : INIT_L10[1:0]; + assign O = l00 ? l10_s1[1] : l10_s1[0]; + +endmodule + + +module CC_L2T5( + output O, + input I0, I1, I2, I3, I4 +); + parameter [3:0] INIT_L02 = 4'b0000; + parameter [3:0] INIT_L03 = 4'b0000; + parameter [3:0] INIT_L11 = 4'b0000; + parameter [3:0] INIT_L20 = 4'b0000; + + wire [1:0] l02_s1 = I1 ? INIT_L02[3:2] : INIT_L02[1:0]; + wire l02 = I0 ? l02_s1[1] : l02_s1[0]; + + wire [1:0] l03_s1 = I3 ? INIT_L03[3:2] : INIT_L03[1:0]; + wire l03 = I2 ? l03_s1[1] : l03_s1[0]; + + wire [1:0] l11_s1 = l03 ? INIT_L11[3:2] : INIT_L11[1:0]; + wire l11 = l02 ? l11_s1[1] : l11_s1[0]; + + wire [1:0] l20_s1 = l11 ? INIT_L20[3:2] : INIT_L20[1:0]; + assign O = I4 ? l20_s1[1] : l20_s1[0]; + +endmodule diff --git a/techlibs/gatemate/lut_map.v b/techlibs/gatemate/lut_map.v index 1e5d49725..c522e4c85 100644 --- a/techlibs/gatemate/lut_map.v +++ b/techlibs/gatemate/lut_map.v @@ -1,45 +1,45 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -module \$lut (A, Y); - parameter WIDTH = 0; - parameter LUT = 0; - - (* force_downto *) - input [WIDTH-1:0] A; - output Y; - - generate - if (WIDTH == 1) begin - CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0])); - end - else if (WIDTH == 2) begin - CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1])); - end - else if (WIDTH == 3) begin - CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); - end - else if (WIDTH == 4) begin - CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); - end - else begin - wire _TECHMAP_FAIL_ = 1; - end - endgenerate -endmodule +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + (* force_downto *) + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0])); + end + else if (WIDTH == 2) begin + CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1])); + end + else if (WIDTH == 3) begin + CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); + end + else if (WIDTH == 4) begin + CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end + else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule diff --git a/techlibs/gatemate/mux_map.v b/techlibs/gatemate/mux_map.v index 13c1972e3..bcc8480d9 100644 --- a/techlibs/gatemate/mux_map.v +++ b/techlibs/gatemate/mux_map.v @@ -1,56 +1,56 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); - input A, B, C, D, E, F, G, H, S, T, U; - output Y; - - CC_MX8 _TECHMAP_REPLACE_ ( - .D0(A), .D1(B), .D2(C), .D3(D), - .D4(E), .D5(F), .D6(G), .D7(H), - .S0(S), .S1(T), .S2(U), - .Y(Y) - ); - -endmodule - -module \$_MUX4_ (A, B, C, D, S, T, Y); - input A, B, C, D, S, T; - output Y; - - CC_MX4 _TECHMAP_REPLACE_ ( - .D0(A), .D1(B), .D2(C), .D3(D), - .S0(S), .S1(T), - .Y(Y) - ); - -endmodule - -/* -module \$_MUX_ (A, B, S, Y); - input A, B, S; - output Y; - - CC_MX2 _TECHMAP_REPLACE_ ( - .D0(A), .D1(B), .S0(S), - .Y(Y) - ); - -endmodule -*/ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); + input A, B, C, D, E, F, G, H, S, T, U; + output Y; + + CC_MX8 _TECHMAP_REPLACE_ ( + .D0(A), .D1(B), .D2(C), .D3(D), + .D4(E), .D5(F), .D6(G), .D7(H), + .S0(S), .S1(T), .S2(U), + .Y(Y) + ); + +endmodule + +module \$_MUX4_ (A, B, C, D, S, T, Y); + input A, B, C, D, S, T; + output Y; + + CC_MX4 _TECHMAP_REPLACE_ ( + .D0(A), .D1(B), .D2(C), .D3(D), + .S0(S), .S1(T), + .Y(Y) + ); + +endmodule + +/* +module \$_MUX_ (A, B, S, Y); + input A, B, S; + output Y; + + CC_MX2 _TECHMAP_REPLACE_ ( + .D0(A), .D1(B), .S0(S), + .Y(Y) + ); + +endmodule +*/ diff --git a/techlibs/gatemate/reg_map.v b/techlibs/gatemate/reg_map.v index 6ec170a9d..8debc64c3 100644 --- a/techlibs/gatemate/reg_map.v +++ b/techlibs/gatemate/reg_map.v @@ -1,51 +1,51 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *) -module \$_DFFE_xxxx_ (input D, C, R, E, output Q); - - parameter _TECHMAP_CELLTYPE_ = ""; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - - CC_DFF #( - .CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"), - .EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"), - .SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"), - .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"), - .INIT(_TECHMAP_WIREINIT_Q_) - ) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q)); - - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule - -(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *) -module \$_DLATCH_xxx_ (input E, R, D, output Q); - - parameter _TECHMAP_CELLTYPE_ = ""; - parameter _TECHMAP_WIREINIT_Q_ = 1'bx; - - CC_DLT #( - .G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"), - .SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"), - .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"), - .INIT(_TECHMAP_WIREINIT_Q_) - ) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q)); - - wire _TECHMAP_REMOVEINIT_Q_ = 1; -endmodule +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *) +module \$_DFFE_xxxx_ (input D, C, R, E, output Q); + + parameter _TECHMAP_CELLTYPE_ = ""; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + + CC_DFF #( + .CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"), + .EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"), + .SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"), + .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"), + .INIT(_TECHMAP_WIREINIT_Q_) + ) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q)); + + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule + +(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *) +module \$_DLATCH_xxx_ (input E, R, D, output Q); + + parameter _TECHMAP_CELLTYPE_ = ""; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + + CC_DLT #( + .G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"), + .SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"), + .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"), + .INIT(_TECHMAP_WIREINIT_Q_) + ) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q)); + + wire _TECHMAP_REMOVEINIT_Q_ = 1; +endmodule diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc index 6861b6780..aa002c272 100644 --- a/techlibs/gatemate/synth_gatemate.cc +++ b/techlibs/gatemate/synth_gatemate.cc @@ -1,390 +1,390 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2021 Cologne Chip AG - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/register.h" -#include "kernel/celltypes.h" -#include "kernel/rtlil.h" -#include "kernel/log.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct SynthGateMatePass : public ScriptPass -{ - SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { } - - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_gatemate [options]\n"); - log("\n"); - log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module.\n"); - log("\n"); - log(" -vlog \n"); - log(" write the design to the specified verilog file. Writing of an output\n"); - log(" file is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -json \n"); - log(" write the design to the specified JSON file. Writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). An empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis.\n"); - log("\n"); - log(" -scopename\n"); - log(" create 'scopename' attributes when flattening the netlist.\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n"); - log("\n"); - log(" -noaddf\n"); - log(" do not use CC_ADDF full adder cells in output netlist.\n"); - log("\n"); - log(" -nomult\n"); - log(" do not use CC_MULT multiplier cells in output netlist.\n"); - log("\n"); - log(" -nomx8, -nomx4\n"); - log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n"); - log("\n"); - log(" -luttree\n"); - log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n"); - log(" legacy p_r.\n"); - log("\n"); - log(" -dff\n"); - log(" run 'abc' with -dff option\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with '-dff -D 1' options\n"); - log("\n"); - log(" -abc_new\n"); - log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n"); - log("\n"); - log(" -noiopad\n"); - log(" disable I/O buffer insertion (useful for hierarchical or \n"); - log(" out-of-context flows).\n"); - log("\n"); - log(" -noclkbuf\n"); - log(" disable automatic clock buffer insertion.\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); - help_script(); - log("\n"); - } - - string top_opt, vlog_file, json_file; - bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new; - - void clear_flags() override - { - top_opt = "-auto-top"; - vlog_file = ""; - json_file = ""; - noflatten = false; - scopename = false; - nobram = false; - noaddf = false; - nomult = false; - nomx4 = false; - nomx8 = false; - luttree = false; - dff = false; - retime = false; - noiopad = false; - noclkbuf = false; - abc_new = false; - } - - void execute(std::vector args, RTLIL::Design *design) override - { - string run_from, run_to; - clear_flags(); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { - top_opt = "-top " + args[++argidx]; - continue; - } - if (args[argidx] == "-vlog" && argidx+1 < args.size()) { - vlog_file = args[++argidx]; - continue; - } - if (args[argidx] == "-json" && argidx+1 < args.size()) { - json_file = args[++argidx]; - continue; - } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); - if (pos == std::string::npos) - break; - run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); - continue; - } - if (args[argidx] == "-noflatten") { - noflatten = true; - continue; - } - if (args[argidx] == "-scopename") { - scopename = true; - continue; - } - if (args[argidx] == "-nobram") { - nobram = true; - continue; - } - if (args[argidx] == "-noaddf") { - noaddf = true; - continue; - } - if (args[argidx] == "-nomult") { - nomult = true; - continue; - } - if (args[argidx] == "-nomx4") { - nomx4 = true; - continue; - } - if (args[argidx] == "-nomx8") { - nomx8 = true; - continue; - } - if (args[argidx] == "-luttree") { - luttree = true; - continue; - } - if (args[argidx] == "-dff") { - dff = true; - continue; - } - if (args[argidx] == "-retime") { - retime = true; - continue; - } - if (args[argidx] == "-noiopad") { - noiopad = true; - continue; - } - if (args[argidx] == "-noclkbuf") { - noclkbuf = true; - continue; - } - if (args[argidx] == "-abc_new") { - abc_new = true; - continue; - } - break; - } - extra_args(args, argidx, design); - - if (!design->full_selection()) { - log_cmd_error("This command only operates on fully selected designs!\n"); - } - - log_header(design, "Executing SYNTH_GATEMATE pass.\n"); - log_push(); - - run_script(design, run_from, run_to); - - log_pop(); - } - - void script() override - { - if (check_label("begin")) - { - run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v"); - run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); - } - - if (check_label("prepare")) - { - run("proc"); - if (!noflatten) { - run("check"); - std::string flatten_args = scopename ? " -scopename" : ""; - run("flatten" + flatten_args); - } - run("tribuf -logic"); - run("deminout"); - run("opt_expr"); - run("opt_clean"); - run("check"); - run("opt -nodffe -nosdff"); - run("fsm"); - run("opt"); - run("wreduce"); - run("peepopt"); - run("opt_clean"); - run("muxpack"); - run("share"); - run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); - run("opt_expr"); - run("opt_clean"); - } - - if (check_label("map_mult", "(skip if '-nomult')") && !nomult) - { - run("techmap -map +/gatemate/mul_map.v"); - } - - if (check_label("coarse")) - { - run("alumacc"); - run("opt"); - run("memory -nomap"); - run("opt_clean"); - } - - if (check_label("map_bram", "(skip if '-nobram')") && !nobram) - { - run("memory_libmap -lib +/gatemate/brams.txt"); - run("techmap -map +/gatemate/brams_map.v"); - } - - if (check_label("map_ffram")) - { - run("opt -fast -mux_undef -undriven -fine"); - run("memory_map"); - run("opt -undriven -fine"); - } - - if (check_label("map_gates")) - { - std::string techmap_args = ""; - if (!noaddf) { - techmap_args += " -map +/gatemate/arith_map.v"; - } - run("techmap -map +/techmap.v " + techmap_args); - run("opt -fast"); - if (retime) { - run("abc -dff -D 1", "(only if -retime)"); - } - } - - if (check_label("map_io", "(skip if '-noiopad')") && !noiopad) - { - run("iopadmap -bits " - "-inpad CC_IBUF Y:I " - "-outpad CC_OBUF A:O " - "-toutpad CC_TOBUF ~T:A:O " - "-tinoutpad CC_IOBUF ~T:Y:A:IO" - ); - run("clean"); - } - - if (check_label("map_regs")) - { - run("opt_clean"); - run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01"); - run("techmap -map +/gatemate/reg_map.v"); - run("opt_expr -mux_undef"); - run("simplemap"); - run("opt_clean"); - } - - if (check_label("map_muxs")) - { - std::string muxcover_args; - if (!nomx4) { - muxcover_args += stringf(" -mux4"); - } - if (!nomx8) { - muxcover_args += stringf(" -mux8"); - } - run("muxcover " + muxcover_args); - run("opt -full"); - run("simplemap"); - run("techmap -map +/gatemate/mux_map.v"); - } - - if (check_label("map_luts")) - { - if (luttree || help_mode) { - std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib"; - if (dff) { - abc_args += " -dff"; - } - if (abc_new) { - run("abc_new " + abc_args, "(with -luttree and -abc_new)"); - } else { - run("abc " + abc_args, "(with -luttree, without -abc_new)"); - } - run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)"); - run("gatemate_foldinv", "(with -luttree)"); - run("techmap -map +/gatemate/inv_map.v", "(with -luttree)"); - } - if (!luttree || help_mode) { - std::string abc_args = " -dress -lut 4"; - if (dff) { - abc_args += " -dff"; - } - run("abc " + abc_args, "(without -luttree)"); - } - run("clean"); - } - - if (check_label("map_cells")) - { - run("techmap -map +/gatemate/lut_map.v"); - run("clean"); - } - - if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf) - { - run("clkbufmap -buf CC_BUFG O:I"); - run("clean"); - } - - if (check_label("check")) - { - run("hierarchy -check"); - run("stat -width"); - run("check -noinit"); - run("blackbox =A:whitebox"); - } - - if (check_label("vlog")) - { - run("opt_clean -purge"); - if (!vlog_file.empty() || help_mode) { - run(stringf("write_verilog -noattr %s", help_mode ? "" : vlog_file)); - } - } - - if (check_label("json")) - { - if (!json_file.empty() || help_mode) { - run(stringf("write_json %s", help_mode ? "" : json_file)); - } - } - } -} SynthGateMatePass; - -PRIVATE_NAMESPACE_END +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 Cologne Chip AG + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthGateMatePass : public ScriptPass +{ + SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_gatemate [options]\n"); + log("\n"); + log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module.\n"); + log("\n"); + log(" -vlog \n"); + log(" write the design to the specified verilog file. Writing of an output\n"); + log(" file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. Writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). An empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis.\n"); + log("\n"); + log(" -scopename\n"); + log(" create 'scopename' attributes when flattening the netlist.\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n"); + log("\n"); + log(" -noaddf\n"); + log(" do not use CC_ADDF full adder cells in output netlist.\n"); + log("\n"); + log(" -nomult\n"); + log(" do not use CC_MULT multiplier cells in output netlist.\n"); + log("\n"); + log(" -nomx8, -nomx4\n"); + log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n"); + log("\n"); + log(" -luttree\n"); + log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n"); + log(" legacy p_r.\n"); + log("\n"); + log(" -dff\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with '-dff -D 1' options\n"); + log("\n"); + log(" -abc_new\n"); + log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n"); + log("\n"); + log(" -noiopad\n"); + log(" disable I/O buffer insertion (useful for hierarchical or \n"); + log(" out-of-context flows).\n"); + log("\n"); + log(" -noclkbuf\n"); + log(" disable automatic clock buffer insertion.\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, vlog_file, json_file; + bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new; + + void clear_flags() override + { + top_opt = "-auto-top"; + vlog_file = ""; + json_file = ""; + noflatten = false; + scopename = false; + nobram = false; + noaddf = false; + nomult = false; + nomx4 = false; + nomx8 = false; + luttree = false; + dff = false; + retime = false; + noiopad = false; + noclkbuf = false; + abc_new = false; + } + + void execute(std::vector args, RTLIL::Design *design) override + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-vlog" && argidx+1 < args.size()) { + vlog_file = args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-noflatten") { + noflatten = true; + continue; + } + if (args[argidx] == "-scopename") { + scopename = true; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-noaddf") { + noaddf = true; + continue; + } + if (args[argidx] == "-nomult") { + nomult = true; + continue; + } + if (args[argidx] == "-nomx4") { + nomx4 = true; + continue; + } + if (args[argidx] == "-nomx8") { + nomx8 = true; + continue; + } + if (args[argidx] == "-luttree") { + luttree = true; + continue; + } + if (args[argidx] == "-dff") { + dff = true; + continue; + } + if (args[argidx] == "-retime") { + retime = true; + continue; + } + if (args[argidx] == "-noiopad") { + noiopad = true; + continue; + } + if (args[argidx] == "-noclkbuf") { + noclkbuf = true; + continue; + } + if (args[argidx] == "-abc_new") { + abc_new = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) { + log_cmd_error("This command only operates on fully selected designs!\n"); + } + + log_header(design, "Executing SYNTH_GATEMATE pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + if (check_label("begin")) + { + run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); + } + + if (check_label("prepare")) + { + run("proc"); + if (!noflatten) { + run("check"); + std::string flatten_args = scopename ? " -scopename" : ""; + run("flatten" + flatten_args); + } + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("muxpack"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + } + + if (check_label("map_mult", "(skip if '-nomult')") && !nomult) + { + run("techmap -map +/gatemate/mul_map.v"); + } + + if (check_label("coarse")) + { + run("alumacc"); + run("opt"); + run("memory -nomap"); + run("opt_clean"); + } + + if (check_label("map_bram", "(skip if '-nobram')") && !nobram) + { + run("memory_libmap -lib +/gatemate/brams.txt"); + run("techmap -map +/gatemate/brams_map.v"); + } + + if (check_label("map_ffram")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { + std::string techmap_args = ""; + if (!noaddf) { + techmap_args += " -map +/gatemate/arith_map.v"; + } + run("techmap -map +/techmap.v " + techmap_args); + run("opt -fast"); + if (retime) { + run("abc -dff -D 1", "(only if -retime)"); + } + } + + if (check_label("map_io", "(skip if '-noiopad')") && !noiopad) + { + run("iopadmap -bits " + "-inpad CC_IBUF Y:I " + "-outpad CC_OBUF A:O " + "-toutpad CC_TOBUF ~T:A:O " + "-tinoutpad CC_IOBUF ~T:Y:A:IO" + ); + run("clean"); + } + + if (check_label("map_regs")) + { + run("opt_clean"); + run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01"); + run("techmap -map +/gatemate/reg_map.v"); + run("opt_expr -mux_undef"); + run("simplemap"); + run("opt_clean"); + } + + if (check_label("map_muxs")) + { + std::string muxcover_args; + if (!nomx4) { + muxcover_args += stringf(" -mux4"); + } + if (!nomx8) { + muxcover_args += stringf(" -mux8"); + } + run("muxcover " + muxcover_args); + run("opt -full"); + run("simplemap"); + run("techmap -map +/gatemate/mux_map.v"); + } + + if (check_label("map_luts")) + { + if (luttree || help_mode) { + std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib"; + if (dff) { + abc_args += " -dff"; + } + if (abc_new) { + run("abc_new " + abc_args, "(with -luttree and -abc_new)"); + } else { + run("abc " + abc_args, "(with -luttree, without -abc_new)"); + } + run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)"); + run("gatemate_foldinv", "(with -luttree)"); + run("techmap -map +/gatemate/inv_map.v", "(with -luttree)"); + } + if (!luttree || help_mode) { + std::string abc_args = " -dress -lut 4"; + if (dff) { + abc_args += " -dff"; + } + run("abc " + abc_args, "(without -luttree)"); + } + run("clean"); + } + + if (check_label("map_cells")) + { + run("techmap -map +/gatemate/lut_map.v"); + run("clean"); + } + + if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf) + { + run("clkbufmap -buf CC_BUFG O:I"); + run("clean"); + } + + if (check_label("check")) + { + run("hierarchy -check"); + run("stat -width"); + run("check -noinit"); + run("blackbox =A:whitebox"); + } + + if (check_label("vlog")) + { + run("opt_clean -purge"); + if (!vlog_file.empty() || help_mode) { + run(stringf("write_verilog -noattr %s", help_mode ? "" : vlog_file)); + } + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) { + run(stringf("write_json %s", help_mode ? "" : json_file)); + } + } + } +} SynthGateMatePass; + +PRIVATE_NAMESPACE_END diff --git a/tests/arch/ecp5/bug1836.mem b/tests/arch/ecp5/bug1836.mem index 1e904d87c..4f9184443 100644 --- a/tests/arch/ecp5/bug1836.mem +++ b/tests/arch/ecp5/bug1836.mem @@ -1,32 +1,32 @@ -0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1, -0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10, -0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a, -0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842, -0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6, -0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504, -0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3, -0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5, -0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d, -0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b, -0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23, -0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3, -0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3, -0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de, -0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b, -0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324, -0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e, -0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef, -0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85, -0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd, -0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759, -0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb, -0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c, -0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa, -0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2, -0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894, -0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc, -0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c, -0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c, -0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21, -0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4, -0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb, \ No newline at end of file +0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1, +0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10, +0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a, +0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842, +0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6, +0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504, +0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3, +0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5, +0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d, +0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b, +0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23, +0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3, +0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3, +0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de, +0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b, +0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324, +0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e, +0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef, +0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85, +0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd, +0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759, +0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb, +0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c, +0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa, +0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2, +0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894, +0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc, +0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c, +0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c, +0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21, +0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4, +0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb, From 48a3dcc02a3836ab4a39289910c1aaa9390dc76e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:23:41 +0200 Subject: [PATCH 048/101] End of file fix --- .github/ISSUE_TEMPLATE/config.yml | 1 - .github/ISSUE_TEMPLATE/feature_request.yml | 1 - .github/PULL_REQUEST_TEMPLATE.md | 2 +- .github/workflows/test-sanitizers.yml | 2 +- CHANGELOG | 1 - README.md | 1 - backends/btor/test_cells.sh | 1 - backends/cxxrtl/runtime/README.txt | 2 +- backends/edif/runtest.py | 1 - backends/simplec/test00_uut.v | 1 - backends/smt2/test_cells.sh | 1 - backends/smv/test_cells.sh | 1 - docs/source/appendix/env_vars.rst | 1 - docs/source/cell/word_logic.rst | 2 +- docs/source/code_examples/intro/mycells.v | 1 - docs/source/code_examples/macc/Makefile | 1 - docs/source/code_examples/macc/macc_xilinx_test.ys | 1 - docs/source/code_examples/macro_commands/synth_ice40.ys | 2 +- docs/source/code_examples/opt/opt_merge.ys | 1 - docs/source/code_examples/opt/opt_muxtree.ys | 1 - docs/source/code_examples/scrambler/scrambler.ys | 1 - docs/source/code_examples/synth_flow/Makefile | 1 - docs/source/using_yosys/more_scripting/data_flow_tracking.rst | 2 +- docs/source/using_yosys/synthesis/abc.rst | 1 - docs/source/using_yosys/synthesis/extract.rst | 2 +- docs/source/using_yosys/synthesis/index.rst | 1 - docs/source/using_yosys/synthesis/memory.rst | 1 - docs/source/yosys_internals/extending_yosys/index.rst | 1 - docs/source/yosys_internals/extending_yosys/test_suites.rst | 1 - docs/source/yosys_internals/flow/index.rst | 1 - docs/source/yosys_internals/formats/index.rst | 1 - examples/basys3/README | 1 - examples/basys3/example.xdc | 1 - examples/cmos/README | 1 - examples/cmos/cmos_cells.sp | 1 - examples/cmos/cmos_cells.v | 1 - examples/cmos/cmos_cells_digital.sp | 1 - examples/cmos/counter_digital.ys | 1 - examples/cmos/testbench.sh | 1 - examples/cmos/testbench_digital.sh | 1 - examples/cxx-api/demomain.cc | 1 - examples/gowin/README | 1 - examples/gowin/demo.cst | 2 +- examples/intel/DE2i-150/quartus_compile/de2i.qsf | 2 +- examples/intel/MAX10/runme_postsynth | 1 - examples/intel/asicworld_lfsr/runme_postsynth | 1 - examples/intel/asicworld_lfsr/runme_presynth | 2 +- examples/osu035/Makefile | 1 - examples/smtbmc/Makefile | 1 - examples/smtbmc/demo9.v | 1 - frontends/ast/dpicall.cc | 1 - frontends/blif/blifparse.cc | 1 - frontends/liberty/liberty.cc | 2 -- frontends/verific/README | 1 - frontends/verilog/verilog_lexer.l | 1 - kernel/calc.cc | 1 - kernel/cellhelp.py | 1 - kernel/compressor_tree.h | 2 +- kernel/json.cc | 1 - kernel/mem.cc | 2 +- passes/cmds/design.cc | 1 - passes/opt/opt_lut_ins.cc | 1 - passes/opt/opt_mem_feedback.cc | 1 - passes/opt/opt_mem_priority.cc | 1 - passes/opt/wreduce.cc | 1 - passes/proc/proc_memwr.cc | 1 - passes/sat/example.v | 1 - passes/sat/example.ys | 1 - passes/techmap/arith_tree.cc | 2 +- passes/techmap/filterlib.cc | 1 - passes/techmap/liberty_cache.h | 2 +- passes/techmap/libparse.cc | 1 - passes/tests/test_autotb.cc | 1 - techlibs/achronix/speedster22i/cells_map.v | 1 - techlibs/achronix/speedster22i/cells_sim.v | 3 --- techlibs/analogdevices/arith_map.v | 1 - techlibs/analogdevices/ff_map.v | 1 - techlibs/analogdevices/lut_map.v | 1 - techlibs/fabulous/arith_map.v | 1 - techlibs/fabulous/io_map.v | 1 - techlibs/gatemate/gatemate_foldinv.cc | 1 - techlibs/gowin/adc.v | 1 - techlibs/gowin/arith_map.v | 1 - techlibs/gowin/cells_sim.v | 2 -- techlibs/gowin/cells_xtra.py | 1 - techlibs/gowin/cells_xtra_gw5a.v | 1 - techlibs/ice40/arith_map.v | 1 - techlibs/ice40/tests/test_bram.sh | 1 - techlibs/intel/common/brams_map_m9k.v | 1 - techlibs/intel/cyclone10lp/cells_map.v | 2 -- techlibs/intel/cycloneiv/cells_map.v | 2 -- techlibs/intel/cycloneiv/cells_sim.v | 2 -- techlibs/intel/cycloneive/cells_map.v | 2 -- techlibs/intel/max10/cells_map.v | 2 -- techlibs/intel/max10/dsp_map.v | 1 - techlibs/intel_alm/common/lutram_mlab.txt | 2 +- techlibs/intel_alm/common/misc_sim.v | 2 +- techlibs/lattice/cells_bb_ecp5.v | 1 - techlibs/lattice/cells_bb_nexus.v | 1 - techlibs/lattice/cells_bb_xo2.v | 1 - techlibs/lattice/cells_bb_xo3.v | 1 - techlibs/lattice/cells_bb_xo3d.v | 1 - techlibs/lattice/lattice_dsp_nexus.cc | 2 +- techlibs/lattice/lattice_dsp_nexus.pmg | 2 +- techlibs/microchip/arith_map.v | 1 - techlibs/microchip/brams_defs.vh | 2 +- techlibs/microchip/cells_map.v | 1 - techlibs/microchip/cells_sim.v | 2 +- techlibs/microchip/microchip_dsp_cascade.pmg | 2 +- techlibs/microchip/uSRAM_map.v | 1 - techlibs/nanoxplore/brams.txt | 2 +- techlibs/nanoxplore/cells_bb_l.v | 1 - techlibs/nanoxplore/cells_bb_m.v | 1 - techlibs/nanoxplore/cells_wrap.v | 1 - techlibs/nanoxplore/rf_rams_map_u.v | 2 +- techlibs/quicklogic/ql_bram_types.cc | 2 +- techlibs/quicklogic/qlf_k6n10f/arith_map.v | 1 - techlibs/quicklogic/qlf_k6n10f/brams_map.v | 2 +- techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 2 +- techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 1 - techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v | 1 - techlibs/quicklogic/qlf_k6n10f/ffs_map.v | 1 - techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v | 2 +- techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v | 1 - techlibs/sf2/arith_map.v | 1 - techlibs/xilinx/arith_map.v | 1 - techlibs/xilinx/brams_xcu_map.v | 1 - techlibs/xilinx/cells_xtra.v | 1 - techlibs/xilinx/ff_map.v | 1 - techlibs/xilinx/lut_map.v | 1 - techlibs/xilinx/tests/bram1.sh | 1 - techlibs/xilinx/tests/bram2.sh | 1 - techlibs/xilinx/xc3s_mult_map.v | 1 - techlibs/xilinx/xc3sda_dsp_map.v | 1 - techlibs/xilinx/xc5v_dsp_map.v | 1 - techlibs/xilinx/xc6s_dsp_map.v | 2 -- techlibs/xilinx/xcu_dsp_map.v | 1 - techlibs/xilinx/xilinx_dffopt.cc | 1 - tests/arch/analogdevices/asym_ram_sdp.ys | 1 - tests/arch/analogdevices/dffs.ys | 1 - tests/arch/analogdevices/dsp_abc9.ys | 1 - tests/arch/common/blockram.v | 1 - tests/arch/common/memory_attributes/attributes_test.v | 1 - tests/arch/ecp5/add_sub.ys | 1 - tests/arch/ecp5/dffs.ys | 2 +- tests/arch/efinix/add_sub.ys | 1 - tests/arch/gowin/add_sub.ys | 1 - tests/arch/gowin/compare.ys | 2 -- tests/arch/gowin/tribuf.ys | 2 +- tests/arch/ice40/add_sub.ys | 1 - tests/arch/ice40/dffs.ys | 2 +- tests/arch/intel_alm/add_sub.ys | 1 - tests/arch/intel_alm/adffs.ys | 1 - tests/arch/intel_alm/blockram.ys | 1 - tests/arch/intel_alm/counter.ys | 1 - tests/arch/intel_alm/dffs.ys | 1 - tests/arch/intel_alm/fsm.ys | 1 - tests/arch/intel_alm/logic.ys | 1 - tests/arch/intel_alm/lutram.ys | 1 - tests/arch/intel_alm/mul.ys | 1 - tests/arch/intel_alm/mux.ys | 1 - tests/arch/intel_alm/shifter.ys | 1 - tests/arch/intel_alm/tribuf.ys | 1 - tests/arch/microchip/.gitignore | 1 - tests/arch/microchip/dff.ys | 2 +- tests/arch/microchip/dff_opt.ys | 2 +- tests/arch/microchip/ram_SDP.ys | 2 +- tests/arch/microchip/ram_TDP.ys | 2 +- tests/arch/microchip/reduce.ys | 1 - tests/arch/microchip/simple_ram.ys | 2 +- tests/arch/microchip/widemux.ys | 2 +- tests/arch/xilinx/asym_ram_sdp.ys | 1 - tests/arch/xilinx/asym_ram_sdp_read_wider.v | 2 +- tests/arch/xilinx/asym_ram_sdp_write_wider.v | 2 +- tests/arch/xilinx/dffs.ys | 1 - tests/arch/xilinx/dsp_cascade.ys | 1 - tests/arith_tree/arith_tree_alu_macc_equiv.ys | 2 +- tests/arith_tree/arith_tree_final_adder.ys | 1 - tests/asicworld/code_hdl_models_up_counter.v | 1 - tests/asicworld/code_verilog_tutorial_counter_tb.v | 1 - tests/bram/generate_mk.py | 1 - tests/errors/syntax_err01.v | 1 - tests/errors/syntax_err02.v | 1 - tests/errors/syntax_err03.v | 1 - tests/errors/syntax_err04.v | 1 - tests/errors/syntax_err05.v | 1 - tests/errors/syntax_err06.v | 1 - tests/errors/syntax_err07.v | 1 - tests/errors/syntax_err08.v | 1 - tests/errors/syntax_err09.v | 1 - tests/errors/syntax_err13.v | 1 - tests/functional/rtlil_cells.py | 2 +- tests/functional/smt_vcd.py | 2 +- tests/hana/README | 1 - tests/hana/hana_vlib.v | 1 - tests/hana/test_simulation_decoder.v | 1 - tests/hana/test_simulation_vlib.v | 1 - tests/liberty/XNOR2X1.lib | 2 +- tests/liberty/idranges.lib | 1 - tests/liberty/non-ascii.lib | 2 +- tests/liberty/retention.lib | 2 +- tests/liberty/semicolmissing.lib | 2 -- tests/memlib/generate_mk.py | 1 - tests/memlib/memlib_lut.txt | 1 - tests/memlib/memlib_wide_write.v | 1 - tests/memories/amber23_sram_byte_en.v | 1 - tests/memories/read_arst.v | 1 - tests/memories/wide_read_async.v | 1 - tests/memories/wide_read_mixed.v | 1 - tests/memories/wide_read_sync.v | 1 - tests/memories/wide_read_trans.v | 1 - tests/opt/opt_dff_qd.ys | 1 - tests/opt/opt_dff_srst.ys | 1 - tests/opt/opt_expr.ys | 2 +- tests/opt/opt_expr_mux_undef.ys | 1 - tests/opt/opt_merge_properties.ys | 1 - tests/opt/opt_share_bug2538.ys | 1 - tests/pyosys/test_sigspec_it.py | 1 - tests/rtlil/.gitignore | 2 +- tests/sat/alu.v | 1 - tests/sat/asserts_seq.v | 1 - tests/sat/asserts_seq.ys | 1 - tests/sat/counters-repeat.v | 1 - tests/sat/counters-repeat.ys | 1 - tests/sat/counters.v | 1 - tests/sat/counters.ys | 1 - tests/sat/expose_dff.v | 1 - tests/sat/expose_dff.ys | 1 - tests/sat/share.v | 1 - tests/sdc/alu_sub.v | 1 - tests/sdc/side-effects.sdc | 2 +- tests/sim/assume_x_first_step.ys | 2 +- tests/sim/simple_assign.vcd | 2 +- tests/sim/vcd_var_reference_whitespace.ys | 2 +- tests/simple/aes_kexp128.v | 1 - tests/simple/arraycells.v | 1 - tests/simple/attrib01_module.v | 1 - tests/simple/attrib02_port_decl.v | 1 - tests/simple/attrib03_parameter.v | 1 - tests/simple/attrib04_net_var.v | 1 - tests/simple/attrib05_port_conn.v.DISABLED | 1 - tests/simple/attrib06_operator_suffix.v | 1 - tests/simple/attrib07_func_call.v.DISABLED | 1 - tests/simple/attrib08_mod_inst.v | 1 - tests/simple/attrib09_case.v | 1 - tests/simple/dff_different_styles.v | 2 -- tests/simple/fsm.v | 1 - tests/simple/hierarchy.v | 1 - tests/simple/i2c_master_tests.v | 1 - tests/simple/loops.v | 1 - tests/simple/mem_arst.v | 1 - tests/simple/memory.v | 1 - tests/simple/muxtree.v | 1 - tests/simple/omsp_dbg_uart.v | 1 - tests/simple/paramods.v | 1 - tests/simple/process.v | 1 - tests/simple/rotate.v | 1 - tests/simple/specify.v | 1 - tests/simple/usb_phy_tests.v | 1 - tests/simple/values.v | 1 - tests/simple/vloghammer.v | 1 - tests/smv/run-single.sh | 1 - tests/smv/run-test.sh | 1 - tests/sva/Makefile | 1 - tests/sva/runtest.sh | 1 - tests/svtypes/enum_simple.ys | 1 - tests/svtypes/typedef_scopes.sv | 1 - tests/techmap/bmuxmap_pmux.ys | 2 -- tests/techmap/bug5495.sh | 1 - tests/techmap/clockgate.lib | 2 +- tests/techmap/clockgate.v | 2 +- tests/techmap/clockgate_bad.il | 2 +- tests/techmap/clockgate_neg.lib | 2 +- tests/techmap/clockgate_pos.lib | 2 +- tests/techmap/clockgate_wide.v | 2 +- tests/techmap/dfflibmap_dffsr_not_next.lib | 2 +- tests/techmap/dfflibmap_formal.ys | 2 +- tests/techmap/mem_simple_4x1_map.v | 1 - tests/tools/cmp_tbdata.c | 1 - tests/tools/profiler.pl | 1 - tests/tools/txt2tikztiming.py | 1 - tests/tools/vcd2txt.pl | 1 - tests/various/attrib05_port_conn.v | 1 - tests/various/attrib07_func_call.v | 1 - tests/various/bug3515.ys | 1 - tests/various/bug4909.ys | 1 - tests/various/deminout_unused.ys | 1 - tests/various/dynamic_part_select/latch_1990_gate.v | 1 - tests/various/dynamic_part_select/reversed.v | 1 - tests/various/reg_wire_error.sv | 1 - tests/various/scopeinfo.ys | 2 +- tests/various/sim_const.ys | 1 - tests/various/stat_area_by_width.lib | 2 +- tests/various/stat_hierarchy.ys | 2 -- tests/various/stat_high_level.ys | 2 -- tests/various/stat_high_level2.ys | 2 -- tests/verific/case.sv | 1 - tests/verific/rom_case.ys | 2 +- tests/verilog/for_loop_signed_index.ys | 2 +- tests/verilog/issue4402.ys | 2 +- tests/verilog/issue5745.ys | 2 +- tests/verilog/unreachable_case_sign.ys | 1 - tests/vloghtb/run-test.sh | 1 - tests/vloghtb/test_makefile | 1 - 304 files changed, 64 insertions(+), 321 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml index c758bf1f6..ce2780d6f 100644 --- a/.github/ISSUE_TEMPLATE/config.yml +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -5,4 +5,3 @@ contact_links: - name: IRC Channel url: https://web.libera.chat/#yosys about: "#yosys on irc.libera.chat" - diff --git a/.github/ISSUE_TEMPLATE/feature_request.yml b/.github/ISSUE_TEMPLATE/feature_request.yml index 49d86f341..19785d22a 100644 --- a/.github/ISSUE_TEMPLATE/feature_request.yml +++ b/.github/ISSUE_TEMPLATE/feature_request.yml @@ -22,4 +22,3 @@ body: description: "A clear and detailed description of the feature." validations: required: true - diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index d8d929f3f..428735733 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -6,4 +6,4 @@ _Explain how this is achieved._ _Make sure your change comes with tests. If not possible, share how a reviewer might evaluate it._ -_These template prompts can be deleted when you're done responding to them._ \ No newline at end of file +_These template prompts can be deleted when you're done responding to them._ diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index a1229d164..d6c77fcf1 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -98,4 +98,4 @@ jobs: echo "Some jobs failed or were cancelled" exit 1 fi - - run: echo "All good" \ No newline at end of file + - run: echo "All good" diff --git a/CHANGELOG b/CHANGELOG index 61b221bc9..543209a83 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1802,4 +1802,3 @@ Yosys 0.1.0 .. Yosys 0.2.0 - Added "design -stash/-copy-from/-copy-to" - Added "copy" command - Added "splice" command - diff --git a/README.md b/README.md index e27486a84..61062243b 100644 --- a/README.md +++ b/README.md @@ -303,4 +303,3 @@ DOCS (e.g.) This will build/rebuild yosys as necessary before generating the website documentation from the yosys help commands. To build for pdf instead of html, use the `docs-latexpdf` target. - diff --git a/backends/btor/test_cells.sh b/backends/btor/test_cells.sh index fc7f5b75c..dc044ec29 100755 --- a/backends/btor/test_cells.sh +++ b/backends/btor/test_cells.sh @@ -27,4 +27,3 @@ for fn in test_*.il; do done echo "OK." - diff --git a/backends/cxxrtl/runtime/README.txt b/backends/cxxrtl/runtime/README.txt index 9ae7051cd..f6e2d6c92 100644 --- a/backends/cxxrtl/runtime/README.txt +++ b/backends/cxxrtl/runtime/README.txt @@ -15,4 +15,4 @@ file of the simulation toplevel). The interfaces declared in `cxxrtl*.h` (without `capi`) are unstable and may change without notice. For clarity, all of the files in this directory and its subdirectories have unique names regardless -of the directory where they are placed. \ No newline at end of file +of the directory where they are placed. diff --git a/backends/edif/runtest.py b/backends/edif/runtest.py index 826876a86..7af6433c1 100644 --- a/backends/edif/runtest.py +++ b/backends/edif/runtest.py @@ -118,4 +118,3 @@ os.system("set -x; ./test_gold > test_gold.out") os.system("set -x; ./test_gate > test_gate.out") os.system("set -x; md5sum test_gold.out test_gate.out") - diff --git a/backends/simplec/test00_uut.v b/backends/simplec/test00_uut.v index 92329a6f9..15ff4391d 100644 --- a/backends/simplec/test00_uut.v +++ b/backends/simplec/test00_uut.v @@ -11,4 +11,3 @@ endmodule module unit_y(input [31:0] a, b, c, output [31:0] y); assign y = a & (b | c); endmodule - diff --git a/backends/smt2/test_cells.sh b/backends/smt2/test_cells.sh index 33c1b9989..bf13b5fb3 100644 --- a/backends/smt2/test_cells.sh +++ b/backends/smt2/test_cells.sh @@ -52,4 +52,3 @@ echo "" echo " All tests passed." echo "" exit 0 - diff --git a/backends/smv/test_cells.sh b/backends/smv/test_cells.sh index f2c5ff09d..2497edc6b 100644 --- a/backends/smv/test_cells.sh +++ b/backends/smv/test_cells.sh @@ -30,4 +30,3 @@ for fn in test_*.il; do done grep '^-- invariant .* is false' *.out || echo 'All OK.' - diff --git a/docs/source/appendix/env_vars.rst b/docs/source/appendix/env_vars.rst index 7e10fad86..1be00288e 100644 --- a/docs/source/appendix/env_vars.rst +++ b/docs/source/appendix/env_vars.rst @@ -29,4 +29,3 @@ Yosys environment variables ``YOSYS_ABORT_ON_LOG_ERROR`` Can be used for debugging Yosys internals. Setting it to 1 causes abort() to be called when Yosys terminates with an error message. - diff --git a/docs/source/cell/word_logic.rst b/docs/source/cell/word_logic.rst index 32945d560..9f04e9b99 100644 --- a/docs/source/cell/word_logic.rst +++ b/docs/source/cell/word_logic.rst @@ -43,4 +43,4 @@ values. .. autocellgroup:: logic :members: :source: - :linenos: \ No newline at end of file + :linenos: diff --git a/docs/source/code_examples/intro/mycells.v b/docs/source/code_examples/intro/mycells.v index 802f58718..87eed4ada 100644 --- a/docs/source/code_examples/intro/mycells.v +++ b/docs/source/code_examples/intro/mycells.v @@ -20,4 +20,3 @@ output reg Q; always @(posedge C) Q <= D; endmodule - diff --git a/docs/source/code_examples/macc/Makefile b/docs/source/code_examples/macc/Makefile index 6bd7dd116..a49083fd3 100644 --- a/docs/source/code_examples/macc/Makefile +++ b/docs/source/code_examples/macc/Makefile @@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys .PHONY: clean clean: @rm -f *.dot - diff --git a/docs/source/code_examples/macc/macc_xilinx_test.ys b/docs/source/code_examples/macc/macc_xilinx_test.ys index 47bf399b2..aab4eb811 100644 --- a/docs/source/code_examples/macc/macc_xilinx_test.ys +++ b/docs/source/code_examples/macc/macc_xilinx_test.ys @@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2 design -load __macc_xilinx_xmap show -prefix macc_xilinx_xmap -format dot -notitle - diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index 07d960a64..e9b36bb35 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -88,4 +88,4 @@ check: stat check -noinit blackbox =A:whitebox - \ No newline at end of file + diff --git a/docs/source/code_examples/opt/opt_merge.ys b/docs/source/code_examples/opt/opt_merge.ys index 38434ca3a..2cb43a860 100644 --- a/docs/source/code_examples/opt/opt_merge.ys +++ b/docs/source/code_examples/opt/opt_merge.ys @@ -15,4 +15,3 @@ opt_merge after clean show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut - diff --git a/docs/source/code_examples/opt/opt_muxtree.ys b/docs/source/code_examples/opt/opt_muxtree.ys index b9d394c08..b5e4396d4 100644 --- a/docs/source/code_examples/opt/opt_muxtree.ys +++ b/docs/source/code_examples/opt/opt_muxtree.ys @@ -14,4 +14,3 @@ opt_muxtree after clean show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut - diff --git a/docs/source/code_examples/scrambler/scrambler.ys b/docs/source/code_examples/scrambler/scrambler.ys index f14caa6f7..c340f4b76 100644 --- a/docs/source/code_examples/scrambler/scrambler.ys +++ b/docs/source/code_examples/scrambler/scrambler.ys @@ -19,4 +19,3 @@ eval -set in 1 -show out eval -set in 270369 -show out sat -set out 632435482 - diff --git a/docs/source/code_examples/synth_flow/Makefile b/docs/source/code_examples/synth_flow/Makefile index 583c6a421..83a5f5b97 100644 --- a/docs/source/code_examples/synth_flow/Makefile +++ b/docs/source/code_examples/synth_flow/Makefile @@ -17,4 +17,3 @@ examples: .PHONY: clean clean: @rm -f *.dot - diff --git a/docs/source/using_yosys/more_scripting/data_flow_tracking.rst b/docs/source/using_yosys/more_scripting/data_flow_tracking.rst index aa13a2e69..fa8d1be00 100644 --- a/docs/source/using_yosys/more_scripting/data_flow_tracking.rst +++ b/docs/source/using_yosys/more_scripting/data_flow_tracking.rst @@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other input is either 1 or carries a tag of the same group. So if one input is ``0, "key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a", "key:b"``, rather than simply ``0``. Note that if we add an unrelated -``"overflow"`` tag to the first input, it would still not be propagated. \ No newline at end of file +``"overflow"`` tag to the first input, it would still not be propagated. diff --git a/docs/source/using_yosys/synthesis/abc.rst b/docs/source/using_yosys/synthesis/abc.rst index ba12cabc1..086205f63 100644 --- a/docs/source/using_yosys/synthesis/abc.rst +++ b/docs/source/using_yosys/synthesis/abc.rst @@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual critical path, while the generally-longer paths result in ABC9 being able to reduce design area by mapping other logic to slower cells with greater logic density. - diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst index 73957bb55..8c346412a 100644 --- a/docs/source/using_yosys/synthesis/extract.rst +++ b/docs/source/using_yosys/synthesis/extract.rst @@ -228,4 +228,4 @@ Unwrap in ``test2``: :end-before: end part e .. figure:: /_images/code_examples/macc/macc_xilinx_test2e.* - :class: width-helper invert-helper \ No newline at end of file + :class: width-helper invert-helper diff --git a/docs/source/using_yosys/synthesis/index.rst b/docs/source/using_yosys/synthesis/index.rst index 60581668f..6ca8b02d5 100644 --- a/docs/source/using_yosys/synthesis/index.rst +++ b/docs/source/using_yosys/synthesis/index.rst @@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and extract abc cell_libs - diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst index 9b81fb6dc..b498bcb1d 100644 --- a/docs/source/using_yosys/synthesis/memory.rst +++ b/docs/source/using_yosys/synthesis/memory.rst @@ -787,4 +787,3 @@ Asynchronous writes end assign read_data = mem[read_addr]; - diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst index 72843ecd6..d7ef48b08 100644 --- a/docs/source/yosys_internals/extending_yosys/index.rst +++ b/docs/source/yosys_internals/extending_yosys/index.rst @@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds. advanced_bugpoint contributing test_suites - diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 58274c864..f506f5c87 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -194,4 +194,3 @@ compiler versions. For up to date information, including OS versions, refer to .. code-block:: console cmake --build build --target test-unit - diff --git a/docs/source/yosys_internals/flow/index.rst b/docs/source/yosys_internals/flow/index.rst index c7ab0ebcc..e5afa2540 100644 --- a/docs/source/yosys_internals/flow/index.rst +++ b/docs/source/yosys_internals/flow/index.rst @@ -16,4 +16,3 @@ These scripts contain three types of commands: overview control_and_data verilog_frontend - diff --git a/docs/source/yosys_internals/formats/index.rst b/docs/source/yosys_internals/formats/index.rst index 611370ebc..22d9e964a 100644 --- a/docs/source/yosys_internals/formats/index.rst +++ b/docs/source/yosys_internals/formats/index.rst @@ -56,4 +56,3 @@ constructs must be called from the synthesis script first. .. [1] In Yosys the term pass is only used to refer to commands that operate on the RTLIL data structure. - diff --git a/examples/basys3/README b/examples/basys3/README index 0ce717294..77fbef15c 100644 --- a/examples/basys3/README +++ b/examples/basys3/README @@ -16,4 +16,3 @@ Programming board: All of the above: bash run.sh - diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc index 8cdaa1996..7b6736588 100644 --- a/examples/basys3/example.xdc +++ b/examples/basys3/example.xdc @@ -21,4 +21,3 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] - diff --git a/examples/cmos/README b/examples/cmos/README index c459b4b54..7033c9b82 100644 --- a/examples/cmos/README +++ b/examples/cmos/README @@ -10,4 +10,3 @@ Each test bench can be run separately by either running: The later case also includes pure verilog simulation using the iverilog and gtkwave for comparison. - diff --git a/examples/cmos/cmos_cells.sp b/examples/cmos/cmos_cells.sp index 673b20d08..f23d978cb 100644 --- a/examples/cmos/cmos_cells.sp +++ b/examples/cmos/cmos_cells.sp @@ -36,4 +36,3 @@ X1 nC D t DLATCH X2 C t Q DLATCH X3 C nC NOT .ENDS DFF - diff --git a/examples/cmos/cmos_cells.v b/examples/cmos/cmos_cells.v index 27278facb..9a855ab8c 100644 --- a/examples/cmos/cmos_cells.v +++ b/examples/cmos/cmos_cells.v @@ -41,4 +41,3 @@ always @(posedge C, posedge S, posedge R) else Q <= D; endmodule - diff --git a/examples/cmos/cmos_cells_digital.sp b/examples/cmos/cmos_cells_digital.sp index e1cb82a2f..89f844094 100644 --- a/examples/cmos/cmos_cells_digital.sp +++ b/examples/cmos/cmos_cells_digital.sp @@ -28,4 +28,3 @@ Alatch D E null null Q nQ latch1 .model dff1 d_dff Adff D C null null Q nQ dff1 .ENDS DFF - diff --git a/examples/cmos/counter_digital.ys b/examples/cmos/counter_digital.ys index a5e728e02..eef353e98 100644 --- a/examples/cmos/counter_digital.ys +++ b/examples/cmos/counter_digital.ys @@ -13,4 +13,3 @@ abc -liberty cmos_cells.lib;; write_verilog synth.v write_spice -neg 0s -pos 1s synth.sp - diff --git a/examples/cmos/testbench.sh b/examples/cmos/testbench.sh index 856169ab9..6928b71a2 100644 --- a/examples/cmos/testbench.sh +++ b/examples/cmos/testbench.sh @@ -4,4 +4,3 @@ set -ex ../../yosys counter.ys ngspice testbench.sp - diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh index 2e70e874c..1a27925b1 100644 --- a/examples/cmos/testbench_digital.sh +++ b/examples/cmos/testbench_digital.sh @@ -12,4 +12,3 @@ iverilog -o counter_tb counter.v counter_tb.v # requires ngspice with xspice support enabled: ngspice testbench_digital.sp - diff --git a/examples/cxx-api/demomain.cc b/examples/cxx-api/demomain.cc index c63edbdf0..7ab9324fa 100644 --- a/examples/cxx-api/demomain.cc +++ b/examples/cxx-api/demomain.cc @@ -19,4 +19,3 @@ int main() Yosys::yosys_shutdown(); return 0; } - diff --git a/examples/gowin/README b/examples/gowin/README index 0194e9f09..75076fde5 100644 --- a/examples/gowin/README +++ b/examples/gowin/README @@ -14,4 +14,3 @@ gowinTool_linux directory 3.) edit gowinTool_linux/bin/gwlicense.ini. Set lic="..." to the full path to the license file. - diff --git a/examples/gowin/demo.cst b/examples/gowin/demo.cst index c8f89dcf8..2be79f694 100644 --- a/examples/gowin/demo.cst +++ b/examples/gowin/demo.cst @@ -7,4 +7,4 @@ IO_LOC "leds[3]" 82; IO_LOC "leds[4]" 83; IO_LOC "leds[5]" 84; IO_LOC "leds[6]" 85; -IO_LOC "leds[7]" 86; \ No newline at end of file +IO_LOC "leds[7]" 86; diff --git a/examples/intel/DE2i-150/quartus_compile/de2i.qsf b/examples/intel/DE2i-150/quartus_compile/de2i.qsf index 5a230155f..99245b607 100644 --- a/examples/intel/DE2i-150/quartus_compile/de2i.qsf +++ b/examples/intel/DE2i-150/quartus_compile/de2i.qsf @@ -1096,4 +1096,4 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/examples/intel/MAX10/runme_postsynth b/examples/intel/MAX10/runme_postsynth index 657c05fa8..70bad061d 100644 --- a/examples/intel/MAX10/runme_postsynth +++ b/examples/intel/MAX10/runme_postsynth @@ -2,4 +2,3 @@ iverilog -D POST_IMPL -o verif_post -s tb_top tb_top.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) vvp -N verif_post - diff --git a/examples/intel/asicworld_lfsr/runme_postsynth b/examples/intel/asicworld_lfsr/runme_postsynth index ad5ca39d4..56a232eb3 100755 --- a/examples/intel/asicworld_lfsr/runme_postsynth +++ b/examples/intel/asicworld_lfsr/runme_postsynth @@ -2,4 +2,3 @@ iverilog -D POST_IMPL -o verif_post -s tb lfsr_updown_tb.v top.vqm $(yosys-config --datdir/altera_intel/max10/cells_comb_max10.v) vvp -N verif_post - diff --git a/examples/intel/asicworld_lfsr/runme_presynth b/examples/intel/asicworld_lfsr/runme_presynth index 3ed6618d3..9a83b1bbd 100755 --- a/examples/intel/asicworld_lfsr/runme_presynth +++ b/examples/intel/asicworld_lfsr/runme_presynth @@ -2,4 +2,4 @@ iverilog -o presynth lfsr_updown_tb.v lfsr_updown.v &&\ -vvp -N presynth \ No newline at end of file +vvp -N presynth diff --git a/examples/osu035/Makefile b/examples/osu035/Makefile index 2bb8162b3..ce3c36269 100644 --- a/examples/osu035/Makefile +++ b/examples/osu035/Makefile @@ -10,4 +10,3 @@ osu035_stdcells.lib: clean: rm -f osu035_stdcells.lib rm -f example.yslog example.edif - diff --git a/examples/smtbmc/Makefile b/examples/smtbmc/Makefile index af937ea74..54dd2dac4 100644 --- a/examples/smtbmc/Makefile +++ b/examples/smtbmc/Makefile @@ -74,4 +74,3 @@ clean: rm -f glift_mux.ys .PHONY: demo1 demo2 demo3 demo4 demo5 demo6 demo7 demo8 demo9 clean - diff --git a/examples/smtbmc/demo9.v b/examples/smtbmc/demo9.v index f0b91e2ca..bbfbf11b8 100644 --- a/examples/smtbmc/demo9.v +++ b/examples/smtbmc/demo9.v @@ -10,4 +10,3 @@ module demo9; cover(1); end endmodule - diff --git a/frontends/ast/dpicall.cc b/frontends/ast/dpicall.cc index b4e4c6f15..3b1d13b09 100644 --- a/frontends/ast/dpicall.cc +++ b/frontends/ast/dpicall.cc @@ -161,4 +161,3 @@ std::unique_ptr AST::dpi_call(AstSrcLocType, const std::string&, c YOSYS_NAMESPACE_END #endif /* YOSYS_ENABLE_LIBFFI */ - diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 2eae64fa1..220c317ec 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -691,4 +691,3 @@ struct BlifFrontend : public Frontend { } BlifFrontend; YOSYS_NAMESPACE_END - diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 447f438a8..96db2f640 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -836,5 +836,3 @@ skip_cell:; } LibertyFrontend; YOSYS_NAMESPACE_END - - diff --git a/frontends/verific/README b/frontends/verific/README index 921873af3..0e8b76f35 100644 --- a/frontends/verific/README +++ b/frontends/verific/README @@ -34,4 +34,3 @@ should be something like this: SBY [example] summary: engine_0 (smtbmc yices) returned PASS for induction SBY [example] summary: successful proof by k-induction. SBY [example] DONE (PASS, rc=0) - diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 62a7f7bbb..7b45370ae 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -713,4 +713,3 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { <*>. { BEGIN(0); return char_tok(*YYText(), out_loc); } %% - diff --git a/kernel/calc.cc b/kernel/calc.cc index 84ac100ab..685326f82 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -712,4 +712,3 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar } YOSYS_NAMESPACE_END - diff --git a/kernel/cellhelp.py b/kernel/cellhelp.py index 741558730..f834ead83 100644 --- a/kernel/cellhelp.py +++ b/kernel/cellhelp.py @@ -97,4 +97,3 @@ for line in fileinput.input(): print(simHelper) # new simHelper = SimHelper() - diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h index 5ac9d1c3e..d5ca316b1 100644 --- a/kernel/compressor_tree.h +++ b/kernel/compressor_tree.h @@ -114,4 +114,4 @@ FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode); YOSYS_NAMESPACE_END -#endif // COMPRESSOR_TREE_H \ No newline at end of file +#endif // COMPRESSOR_TREE_H diff --git a/kernel/json.cc b/kernel/json.cc index 738746267..dc3a110cf 100644 --- a/kernel/json.cc +++ b/kernel/json.cc @@ -169,4 +169,3 @@ void PrettyJson::entry_json(const char *name, const Json &value) this->name(name); this->value(value); } - diff --git a/kernel/mem.cc b/kernel/mem.cc index 2f7f16c7a..63f07aad0 100644 --- a/kernel/mem.cc +++ b/kernel/mem.cc @@ -1915,4 +1915,4 @@ RTLIL::Const::iterator MemContents::_range_write(RTLIL::Const::iterator it, RTLI auto it_next = std::next(it, _data_width); std::fill(to_end, it_next, State::S0); return it_next; -} \ No newline at end of file +} diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index cfd5d8af8..9dff6fa45 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -401,4 +401,3 @@ struct DesignPass : public Pass { } DesignPass; YOSYS_NAMESPACE_END - diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index c1355da25..d96c269ce 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -282,4 +282,3 @@ struct OptLutInsPass : public Pass { } OptLutInsPass; PRIVATE_NAMESPACE_END - diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index fe5157934..f25eb8a8c 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -347,4 +347,3 @@ struct OptMemFeedbackPass : public Pass { } OptMemFeedbackPass; PRIVATE_NAMESPACE_END - diff --git a/passes/opt/opt_mem_priority.cc b/passes/opt/opt_mem_priority.cc index a9b145bea..352a3f919 100644 --- a/passes/opt/opt_mem_priority.cc +++ b/passes/opt/opt_mem_priority.cc @@ -106,4 +106,3 @@ struct OptMemPriorityPass : public Pass { } OptMemPriorityPass; PRIVATE_NAMESPACE_END - diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index d70299ab8..2ba01d26b 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -650,4 +650,3 @@ struct WreducePass : public Pass { } WreducePass; PRIVATE_NAMESPACE_END - diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index e79d24e96..2535d716b 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -117,4 +117,3 @@ struct ProcMemWrPass : public Pass { } ProcMemWrPass; PRIVATE_NAMESPACE_END - diff --git a/passes/sat/example.v b/passes/sat/example.v index aa0ddb6e3..ee6545fab 100644 --- a/passes/sat/example.v +++ b/passes/sat/example.v @@ -82,4 +82,3 @@ always @(posedge clk) assign y = counter == 12; endmodule - diff --git a/passes/sat/example.ys b/passes/sat/example.ys index cc72faac0..b6615eee9 100644 --- a/passes/sat/example.ys +++ b/passes/sat/example.ys @@ -11,4 +11,3 @@ sat -show rst,counter -set-at 3 y 1'b1 -seq 4 example004 sat -prove y 1'b0 -show rst,counter,y -ignore_unknown_cells example004 sat -prove y 1'b0 -tempinduct -show rst,counter,y -set-at 1 rst 1'b1 -seq 1 example004 - diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc index 39217f817..2c5d51386 100644 --- a/passes/techmap/arith_tree.cc +++ b/passes/techmap/arith_tree.cc @@ -487,4 +487,4 @@ struct ArithTreePass : public Pass { } } ArithTreePass; -PRIVATE_NAMESPACE_END \ No newline at end of file +PRIVATE_NAMESPACE_END diff --git a/passes/techmap/filterlib.cc b/passes/techmap/filterlib.cc index 05cfa6d24..f553527d3 100644 --- a/passes/techmap/filterlib.cc +++ b/passes/techmap/filterlib.cc @@ -1,4 +1,3 @@ #define FILTERLIB #include "libparse.cc" - diff --git a/passes/techmap/liberty_cache.h b/passes/techmap/liberty_cache.h index 8ae89947f..01a7bf395 100644 --- a/passes/techmap/liberty_cache.h +++ b/passes/techmap/liberty_cache.h @@ -142,4 +142,4 @@ inline std::string convert_liberty_files_to_merged_scl(const std::vector DSP48E1.PCIN # (see above for explanation) select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i - diff --git a/tests/arith_tree/arith_tree_alu_macc_equiv.ys b/tests/arith_tree/arith_tree_alu_macc_equiv.ys index 165bf5975..da2552107 100644 --- a/tests/arith_tree/arith_tree_alu_macc_equiv.ys +++ b/tests/arith_tree/arith_tree_alu_macc_equiv.ys @@ -104,4 +104,4 @@ equiv_opt -assert arith_tree design -load postopt select -assert-min 1 t:$fa select -assert-count 1 t:$add -design -reset \ No newline at end of file +design -reset diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys index 6bb960ae4..a657d4338 100644 --- a/tests/arith_tree/arith_tree_final_adder.ys +++ b/tests/arith_tree/arith_tree_final_adder.ys @@ -67,4 +67,3 @@ select -assert-none t:$add select -assert-min 1 t:$_AND_ select -assert-min 1 t:$_XOR_ design -reset - diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index e05302182..45dd08f16 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -26,4 +26,3 @@ end endmodule - diff --git a/tests/asicworld/code_verilog_tutorial_counter_tb.v b/tests/asicworld/code_verilog_tutorial_counter_tb.v index 33d540509..e2902d1e5 100644 --- a/tests/asicworld/code_verilog_tutorial_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_counter_tb.v @@ -98,4 +98,3 @@ if (count_compare != count) begin end endmodule - diff --git a/tests/bram/generate_mk.py b/tests/bram/generate_mk.py index 09f5c650b..5b320543b 100644 --- a/tests/bram/generate_mk.py +++ b/tests/bram/generate_mk.py @@ -324,4 +324,3 @@ def create_tests(): ) gen_tests_makefile.generate_custom(create_tests) - diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v index 68e9b1d50..44e23dc13 100644 --- a/tests/errors/syntax_err01.v +++ b/tests/errors/syntax_err01.v @@ -1,4 +1,3 @@ module a; integer [31:0]w; endmodule - diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v index c72e976a8..78b076d2d 100644 --- a/tests/errors/syntax_err02.v +++ b/tests/errors/syntax_err02.v @@ -4,4 +4,3 @@ task to ( ); endtask endmodule - diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v index 6eec44ade..ec43bcc09 100644 --- a/tests/errors/syntax_err03.v +++ b/tests/errors/syntax_err03.v @@ -4,4 +4,3 @@ task to ( ); endtask endmodule - diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v index d488e5dbb..dce45a49b 100644 --- a/tests/errors/syntax_err04.v +++ b/tests/errors/syntax_err04.v @@ -1,4 +1,3 @@ module a; wire [3]x; endmodule - diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v index 8a1f11532..0d134b692 100644 --- a/tests/errors/syntax_err05.v +++ b/tests/errors/syntax_err05.v @@ -1,4 +1,3 @@ module a; input x[2:0]; endmodule - diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v index b35a1dea2..ca1dc5ba7 100644 --- a/tests/errors/syntax_err06.v +++ b/tests/errors/syntax_err06.v @@ -3,4 +3,3 @@ initial begin : label1 end: label2 endmodule - diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v index 62bcc6b3e..207fd8a93 100644 --- a/tests/errors/syntax_err07.v +++ b/tests/errors/syntax_err07.v @@ -3,4 +3,3 @@ wire [5:0]x; wire [3:0]y; assign y = (4)55; endmodule - diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v index d41bfd6c9..28617ab75 100644 --- a/tests/errors/syntax_err08.v +++ b/tests/errors/syntax_err08.v @@ -3,4 +3,3 @@ wire [5:0]x; wire [3:0]y; assign y = x 55; endmodule - diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v index 1e472eb94..9db022768 100644 --- a/tests/errors/syntax_err09.v +++ b/tests/errors/syntax_err09.v @@ -1,3 +1,2 @@ module a(input wire x = 1'b0); endmodule - diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v index b5c942fca..35843df58 100644 --- a/tests/errors/syntax_err13.v +++ b/tests/errors/syntax_err13.v @@ -1,4 +1,3 @@ module a #(p = 0) (); endmodule - diff --git a/tests/functional/rtlil_cells.py b/tests/functional/rtlil_cells.py index 9a44821d3..40bc9188f 100644 --- a/tests/functional/rtlil_cells.py +++ b/tests/functional/rtlil_cells.py @@ -378,4 +378,4 @@ def generate_test_cases(per_cell, rnd): names.append(f'{cell.name}-{name}' if name != '' else cell.name) if per_cell is not None and len(seen_names) >= per_cell: break - return (names, tests) \ No newline at end of file + return (names, tests) diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py index c23be440e..73e28b2b2 100644 --- a/tests/functional/smt_vcd.py +++ b/tests/functional/smt_vcd.py @@ -185,4 +185,4 @@ def simulate_smt(smt_file_path, vcd_path, num_steps, rnd): try: simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd) finally: - smt_io.p_close() \ No newline at end of file + smt_io.p_close() diff --git a/tests/hana/README b/tests/hana/README index 2081fb10f..0ff6855cf 100644 --- a/tests/hana/README +++ b/tests/hana/README @@ -1,4 +1,3 @@ These test cases are copied from the hana project: https://sourceforge.net/projects/sim-sim/ - diff --git a/tests/hana/hana_vlib.v b/tests/hana/hana_vlib.v index fc82f1389..a8921bcfd 100644 --- a/tests/hana/hana_vlib.v +++ b/tests/hana/hana_vlib.v @@ -1136,4 +1136,3 @@ module INC64 #(parameter SIZE = 64) (input [SIZE-1:0] in, output [SIZE:0] out); assign out = in + 1; endmodule - diff --git a/tests/hana/test_simulation_decoder.v b/tests/hana/test_simulation_decoder.v index ef9045aad..2a102a903 100644 --- a/tests/hana/test_simulation_decoder.v +++ b/tests/hana/test_simulation_decoder.v @@ -216,4 +216,3 @@ always @(in or enable) endcase end endmodule - diff --git a/tests/hana/test_simulation_vlib.v b/tests/hana/test_simulation_vlib.v index 7d3af09c2..cdf3c56db 100644 --- a/tests/hana/test_simulation_vlib.v +++ b/tests/hana/test_simulation_vlib.v @@ -62,4 +62,3 @@ VCC synth_VCC_1(.out( synth_net_4)); VCC synth_VCC_2(.out(synth_net_10)); endmodule - diff --git a/tests/liberty/XNOR2X1.lib b/tests/liberty/XNOR2X1.lib index 0bb285ef7..67ae8b706 100644 --- a/tests/liberty/XNOR2X1.lib +++ b/tests/liberty/XNOR2X1.lib @@ -334,4 +334,4 @@ library (ls05_stdcells) { } } } -} \ No newline at end of file +} diff --git a/tests/liberty/idranges.lib b/tests/liberty/idranges.lib index 7149f19ee..890161403 100644 --- a/tests/liberty/idranges.lib +++ b/tests/liberty/idranges.lib @@ -3,4 +3,3 @@ library("foobar") { bar : baz[0] ; } } - diff --git a/tests/liberty/non-ascii.lib b/tests/liberty/non-ascii.lib index 1ac636e34..92e9f7b77 100644 --- a/tests/liberty/non-ascii.lib +++ b/tests/liberty/non-ascii.lib @@ -11,4 +11,4 @@ library(dummy) { function : "A" ; } } -} \ No newline at end of file +} diff --git a/tests/liberty/retention.lib b/tests/liberty/retention.lib index d2f1aa325..5a38b6623 100644 --- a/tests/liberty/retention.lib +++ b/tests/liberty/retention.lib @@ -54,4 +54,4 @@ library (retention) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib index f7c20750a..a58bb7fe1 100644 --- a/tests/liberty/semicolmissing.lib +++ b/tests/liberty/semicolmissing.lib @@ -68,5 +68,3 @@ library(supergate) { } } /* end */ - - diff --git a/tests/memlib/generate_mk.py b/tests/memlib/generate_mk.py index 13b62b1d8..230d2ebd6 100644 --- a/tests/memlib/generate_mk.py +++ b/tests/memlib/generate_mk.py @@ -1588,4 +1588,3 @@ extra = [ "endif", ] gen_tests_makefile.generate_custom(create_tests, extra) - diff --git a/tests/memlib/memlib_lut.txt b/tests/memlib/memlib_lut.txt index 9f6d84123..7b99dcd61 100644 --- a/tests/memlib/memlib_lut.txt +++ b/tests/memlib/memlib_lut.txt @@ -25,4 +25,3 @@ ram distributed \RAM_LUT { clock anyedge; } } - diff --git a/tests/memlib/memlib_wide_write.v b/tests/memlib/memlib_wide_write.v index afed6d00c..25502b61d 100644 --- a/tests/memlib/memlib_wide_write.v +++ b/tests/memlib/memlib_wide_write.v @@ -26,4 +26,3 @@ always @(posedge PORT_A_CLK) begin end endmodule - diff --git a/tests/memories/amber23_sram_byte_en.v b/tests/memories/amber23_sram_byte_en.v index 3554af887..317994d9a 100644 --- a/tests/memories/amber23_sram_byte_en.v +++ b/tests/memories/amber23_sram_byte_en.v @@ -81,4 +81,3 @@ always @(posedge i_clk) end endmodule - diff --git a/tests/memories/read_arst.v b/tests/memories/read_arst.v index 6100cc4a7..72b584e0c 100644 --- a/tests/memories/read_arst.v +++ b/tests/memories/read_arst.v @@ -24,4 +24,3 @@ always @(posedge clk, posedge reset) begin end endmodule - diff --git a/tests/memories/wide_read_async.v b/tests/memories/wide_read_async.v index aecdb1938..dd6f25dcb 100644 --- a/tests/memories/wide_read_async.v +++ b/tests/memories/wide_read_async.v @@ -24,4 +24,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/memories/wide_read_mixed.v b/tests/memories/wide_read_mixed.v index c36db3d31..64a32c2a2 100644 --- a/tests/memories/wide_read_mixed.v +++ b/tests/memories/wide_read_mixed.v @@ -43,4 +43,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/memories/wide_read_sync.v b/tests/memories/wide_read_sync.v index 54ba3f256..447161186 100644 --- a/tests/memories/wide_read_sync.v +++ b/tests/memories/wide_read_sync.v @@ -29,4 +29,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/memories/wide_read_trans.v b/tests/memories/wide_read_trans.v index fe3293500..f7d827f79 100644 --- a/tests/memories/wide_read_trans.v +++ b/tests/memories/wide_read_trans.v @@ -37,4 +37,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/opt/opt_dff_qd.ys b/tests/opt/opt_dff_qd.ys index c6232643f..bf4be9749 100644 --- a/tests/opt/opt_dff_qd.ys +++ b/tests/opt/opt_dff_qd.ys @@ -47,4 +47,3 @@ select -assert-count 6 t:$_DFFE_??_ select -assert-count 4 t:$_DLATCH_?_ select -assert-count 4 t:$_SR_??_ select -assert-none t:$_AND_ t:$_DFFE_??_ t:$_DLATCH_?_ t:$_SR_??_ %% %n t:* %i - diff --git a/tests/opt/opt_dff_srst.ys b/tests/opt/opt_dff_srst.ys index 4a77de0b8..2b660bfc7 100644 --- a/tests/opt/opt_dff_srst.ys +++ b/tests/opt/opt_dff_srst.ys @@ -110,4 +110,3 @@ select -assert-count 2 t:$_DFF_P_ select -assert-count 4 t:$_DFFE_PP_ design -reset - diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 61b54a92f..72288591e 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -374,4 +374,4 @@ EOF scratchpad -set opt.did_something false opt_expr -scratchpad -assert opt.did_something false \ No newline at end of file +scratchpad -assert opt.did_something false diff --git a/tests/opt/opt_expr_mux_undef.ys b/tests/opt/opt_expr_mux_undef.ys index 83c29e07b..499ceeca8 100644 --- a/tests/opt/opt_expr_mux_undef.ys +++ b/tests/opt/opt_expr_mux_undef.ys @@ -287,4 +287,3 @@ select -assert-none t:$_MUX16_ select -assert-count 1 o:out %ci* ########## - diff --git a/tests/opt/opt_merge_properties.ys b/tests/opt/opt_merge_properties.ys index dddc13bfb..bbe70900b 100644 --- a/tests/opt/opt_merge_properties.ys +++ b/tests/opt/opt_merge_properties.ys @@ -13,4 +13,3 @@ chformal -lower clean opt_merge select -assert-count 2 t:$cover - diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys index 7261c6695..dfecc3b35 100644 --- a/tests/opt/opt_share_bug2538.ys +++ b/tests/opt/opt_share_bug2538.ys @@ -17,4 +17,3 @@ EOT proc alumacc equiv_opt -assert opt_share - diff --git a/tests/pyosys/test_sigspec_it.py b/tests/pyosys/test_sigspec_it.py index 2876e7725..c875b1928 100644 --- a/tests/pyosys/test_sigspec_it.py +++ b/tests/pyosys/test_sigspec_it.py @@ -25,4 +25,3 @@ module = d.module(r"\spm") for conn_from, conn_to in module.connections_: for bit_from, bit_to in zip(conn_from, conn_to): print(f"assign {_dump_sigbit(bit_from)} = {_dump_sigbit(bit_to)};") - diff --git a/tests/rtlil/.gitignore b/tests/rtlil/.gitignore index abe251a76..36445e53c 100644 --- a/tests/rtlil/.gitignore +++ b/tests/rtlil/.gitignore @@ -1 +1 @@ -/temp \ No newline at end of file +/temp diff --git a/tests/sat/alu.v b/tests/sat/alu.v index 9826fe05d..820740b7d 100644 --- a/tests/sat/alu.v +++ b/tests/sat/alu.v @@ -76,4 +76,3 @@ module alu( result <= tmp[7:0]; end endmodule - diff --git a/tests/sat/asserts_seq.v b/tests/sat/asserts_seq.v index 9715104f3..3fcf2d659 100644 --- a/tests/sat/asserts_seq.v +++ b/tests/sat/asserts_seq.v @@ -84,4 +84,3 @@ module test_005(clk, a, a_old, b); assert(a_old != b); end endmodule - diff --git a/tests/sat/asserts_seq.ys b/tests/sat/asserts_seq.ys index db94f94ea..f73fdee90 100644 --- a/tests/sat/asserts_seq.ys +++ b/tests/sat/asserts_seq.ys @@ -12,4 +12,3 @@ sat -falsify -prove-asserts -seq 2 test_002 sat -falsify -prove-asserts -seq 2 test_003 sat -falsify -prove-asserts -seq 2 test_004 sat -verify -prove-asserts -seq 2 test_005 - diff --git a/tests/sat/counters-repeat.v b/tests/sat/counters-repeat.v index 2ea45499a..340fc8d94 100644 --- a/tests/sat/counters-repeat.v +++ b/tests/sat/counters-repeat.v @@ -35,4 +35,3 @@ module counter2(clk, rst, ping); assign ping = &count; endmodule - diff --git a/tests/sat/counters-repeat.ys b/tests/sat/counters-repeat.ys index b3dcfe08a..f9b096300 100644 --- a/tests/sat/counters-repeat.ys +++ b/tests/sat/counters-repeat.ys @@ -7,4 +7,3 @@ miter -equiv -make_assert -make_outputs counter1 counter2 miter cd miter; flatten; opt sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs - diff --git a/tests/sat/counters.v b/tests/sat/counters.v index 09e273044..fd4451495 100644 --- a/tests/sat/counters.v +++ b/tests/sat/counters.v @@ -32,4 +32,3 @@ module counter2(clk, rst, ping); assign ping = &count; endmodule - diff --git a/tests/sat/counters.ys b/tests/sat/counters.ys index 330895f82..89f03d214 100644 --- a/tests/sat/counters.ys +++ b/tests/sat/counters.ys @@ -7,4 +7,3 @@ miter -equiv -make_assert -make_outputs counter1 counter2 miter cd miter; flatten; opt sat -verify -prove-asserts -tempinduct -set-at 1 in_rst 1 -seq 1 -show-inputs -show-outputs - diff --git a/tests/sat/expose_dff.v b/tests/sat/expose_dff.v index 708e2da3a..28db5d103 100644 --- a/tests/sat/expose_dff.v +++ b/tests/sat/expose_dff.v @@ -30,4 +30,3 @@ always @(posedge clk, negedge rst_n) else y <= a != 0; endmodule - diff --git a/tests/sat/expose_dff.ys b/tests/sat/expose_dff.ys index 95556840a..aa5d9f352 100644 --- a/tests/sat/expose_dff.ys +++ b/tests/sat/expose_dff.ys @@ -12,4 +12,3 @@ flatten miter34; opt miter34 sat -verify -prove trigger 0 miter12 sat -verify -prove trigger 0 miter34 - diff --git a/tests/sat/share.v b/tests/sat/share.v index 29e423137..0aed31be3 100644 --- a/tests/sat/share.v +++ b/tests/sat/share.v @@ -52,4 +52,3 @@ module test_3( if (9 <= s && s < 12) y3 <= b / a; end endmodule - diff --git a/tests/sdc/alu_sub.v b/tests/sdc/alu_sub.v index d66cad18e..3f971417a 100644 --- a/tests/sdc/alu_sub.v +++ b/tests/sdc/alu_sub.v @@ -59,4 +59,3 @@ module alu( result <= tmp[7:0]; end endmodule - diff --git a/tests/sdc/side-effects.sdc b/tests/sdc/side-effects.sdc index 2c2126f84..890f5652f 100644 --- a/tests/sdc/side-effects.sdc +++ b/tests/sdc/side-effects.sdc @@ -1,2 +1,2 @@ puts "This should print something:" -puts [get_ports {A[0]}] \ No newline at end of file +puts [get_ports {A[0]}] diff --git a/tests/sim/assume_x_first_step.ys b/tests/sim/assume_x_first_step.ys index 3922e06f6..20c759950 100644 --- a/tests/sim/assume_x_first_step.ys +++ b/tests/sim/assume_x_first_step.ys @@ -1,2 +1,2 @@ read_verilog simple_assign.v -sim -r simple_assign.vcd -scope simple_assign \ No newline at end of file +sim -r simple_assign.vcd -scope simple_assign diff --git a/tests/sim/simple_assign.vcd b/tests/sim/simple_assign.vcd index c4494fadf..b84cd54a9 100644 --- a/tests/sim/simple_assign.vcd +++ b/tests/sim/simple_assign.vcd @@ -10,4 +10,4 @@ b1 n1 b1 n2 #10 b0 n1 -b0 n2 \ No newline at end of file +b0 n2 diff --git a/tests/sim/vcd_var_reference_whitespace.ys b/tests/sim/vcd_var_reference_whitespace.ys index 8e17821d2..26e3f5dec 100644 --- a/tests/sim/vcd_var_reference_whitespace.ys +++ b/tests/sim/vcd_var_reference_whitespace.ys @@ -1,3 +1,3 @@ read_rtlil vector_assign.il sim -r var_reference_without_whitespace.vcd -scope tb.uut -sim -r var_reference_with_whitespace.vcd -scope tb.uut \ No newline at end of file +sim -r var_reference_with_whitespace.vcd -scope tb.uut diff --git a/tests/simple/aes_kexp128.v b/tests/simple/aes_kexp128.v index 3ee034789..90efcc251 100644 --- a/tests/simple/aes_kexp128.v +++ b/tests/simple/aes_kexp128.v @@ -21,4 +21,3 @@ always @(posedge clk) begin end endmodule - diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v index fd85a1195..e54870f90 100644 --- a/tests/simple/arraycells.v +++ b/tests/simple/arraycells.v @@ -12,4 +12,3 @@ module aoi12(a, b, c, y); output y; assign y = ~((a & b) | c); endmodule - diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v index d6e36fb80..38bda4c0d 100644 --- a/tests/simple/attrib01_module.v +++ b/tests/simple/attrib01_module.v @@ -18,4 +18,3 @@ module attrib01_foo(clk, rst, inp, out); attrib01_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v index 989213b77..0c6b1545f 100644 --- a/tests/simple/attrib02_port_decl.v +++ b/tests/simple/attrib02_port_decl.v @@ -22,4 +22,3 @@ module attrib02_foo(clk, rst, inp, out); attrib02_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v index d2ae98978..4a84b25df 100644 --- a/tests/simple/attrib03_parameter.v +++ b/tests/simple/attrib03_parameter.v @@ -25,4 +25,3 @@ module attrib03_foo(clk, rst, inp, out); attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v index 98826e971..76118d56d 100644 --- a/tests/simple/attrib04_net_var.v +++ b/tests/simple/attrib04_net_var.v @@ -29,4 +29,3 @@ module attrib04_foo(clk, rst, inp, out); attrib04_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED index 8cc471f4e..3e256e912 100644 --- a/tests/simple/attrib05_port_conn.v.DISABLED +++ b/tests/simple/attrib05_port_conn.v.DISABLED @@ -18,4 +18,3 @@ module attrib05_foo(clk, rst, inp, out); attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); endmodule - diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v index 2bc136f9a..8331172b6 100644 --- a/tests/simple/attrib06_operator_suffix.v +++ b/tests/simple/attrib06_operator_suffix.v @@ -20,4 +20,3 @@ module attrib06_foo(clk, rst, inp_a, inp_b, out); attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out); endmodule - diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED index 282fc5da7..5b76aefc1 100644 --- a/tests/simple/attrib07_func_call.v.DISABLED +++ b/tests/simple/attrib07_func_call.v.DISABLED @@ -18,4 +18,3 @@ module attri07_foo(clk, rst, inp_a, inp_b, out); else out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b); endmodule - diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v index 759e67c7b..582f3876d 100644 --- a/tests/simple/attrib08_mod_inst.v +++ b/tests/simple/attrib08_mod_inst.v @@ -19,4 +19,3 @@ module attrib08_foo(clk, rst, inp, out); (* my_module_instance = 99 *) attrib08_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v index a72b81dda..d569749ca 100644 --- a/tests/simple/attrib09_case.v +++ b/tests/simple/attrib09_case.v @@ -23,4 +23,3 @@ module attrib09_foo(clk, rst, inp, out); attrib09_bar bar_instance (clk, rst, inp, out); endmodule - diff --git a/tests/simple/dff_different_styles.v b/tests/simple/dff_different_styles.v index 7765d6e2a..528513b9f 100644 --- a/tests/simple/dff_different_styles.v +++ b/tests/simple/dff_different_styles.v @@ -101,5 +101,3 @@ always @(posedge clk, posedge preset, posedge clear) begin q <= d; end endmodule - - diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v index 2dba14bb0..26dbd7624 100644 --- a/tests/simple/fsm.v +++ b/tests/simple/fsm.v @@ -66,4 +66,3 @@ begin end endmodule - diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v index b03044fde..b76543372 100644 --- a/tests/simple/hierarchy.v +++ b/tests/simple/hierarchy.v @@ -24,4 +24,3 @@ assign y2 = b; assign y3 = c; assign y4 = d; endmodule - diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v index 3aa596632..958c5b0e9 100644 --- a/tests/simple/i2c_master_tests.v +++ b/tests/simple/i2c_master_tests.v @@ -59,4 +59,3 @@ module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt); cmd_stop <= #1 cmd; endmodule - diff --git a/tests/simple/loops.v b/tests/simple/loops.v index d7743a422..ffd6245b2 100644 --- a/tests/simple/loops.v +++ b/tests/simple/loops.v @@ -76,4 +76,3 @@ begin end endmodule - diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 88d0553b9..11ba27015 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -38,4 +38,3 @@ module MyMem #( end endmodule - diff --git a/tests/simple/memory.v b/tests/simple/memory.v index a6a280992..4f720a484 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -317,4 +317,3 @@ module memtest13 ( end end endmodule - diff --git a/tests/simple/muxtree.v b/tests/simple/muxtree.v index 1fb1cea5e..b02bbb06d 100644 --- a/tests/simple/muxtree.v +++ b/tests/simple/muxtree.v @@ -80,4 +80,3 @@ module select_leaves(input R, C, D, output reg Q); else Q <= Q ? Q : D ? D : Q; endmodule - diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v index 569a28adb..2b0d144c2 100644 --- a/tests/simple/omsp_dbg_uart.v +++ b/tests/simple/omsp_dbg_uart.v @@ -31,4 +31,3 @@ assign cmd_valid = (uart_state==RX_CMD) & xfer_done; assign xfer_done = uart_state!=RX_SYNC; endmodule - diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v index 23cb276f2..a404c07da 100644 --- a/tests/simple/paramods.v +++ b/tests/simple/paramods.v @@ -50,4 +50,3 @@ output [width-1:0] out; assign out = in + step; endmodule - diff --git a/tests/simple/process.v b/tests/simple/process.v index 8cb4c870e..3be002bbb 100644 --- a/tests/simple/process.v +++ b/tests/simple/process.v @@ -81,4 +81,3 @@ end else begin end endmodule - diff --git a/tests/simple/rotate.v b/tests/simple/rotate.v index a2fe00055..e1fd2e408 100644 --- a/tests/simple/rotate.v +++ b/tests/simple/rotate.v @@ -45,4 +45,3 @@ end endfunction endmodule - diff --git a/tests/simple/specify.v b/tests/simple/specify.v index 2c784ef6d..a8b87f53b 100644 --- a/tests/simple/specify.v +++ b/tests/simple/specify.v @@ -28,4 +28,3 @@ specparam c=1:2:3; endspecify endmodule - diff --git a/tests/simple/usb_phy_tests.v b/tests/simple/usb_phy_tests.v index bc45e71a5..dcc5ace4f 100644 --- a/tests/simple/usb_phy_tests.v +++ b/tests/simple/usb_phy_tests.v @@ -33,4 +33,3 @@ always @* end endmodule - diff --git a/tests/simple/values.v b/tests/simple/values.v index afcd251fc..c69b57176 100644 --- a/tests/simple/values.v +++ b/tests/simple/values.v @@ -41,4 +41,3 @@ always @* endcase endmodule - diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v index 5fcedbff1..e36c971f7 100644 --- a/tests/simple/vloghammer.v +++ b/tests/simple/vloghammer.v @@ -79,4 +79,3 @@ endmodule // output signed [5:0] y; // assign y = -(5'd27); // endmodule - diff --git a/tests/smv/run-single.sh b/tests/smv/run-single.sh index 62ed2cee3..452187425 100644 --- a/tests/smv/run-single.sh +++ b/tests/smv/run-single.sh @@ -30,4 +30,3 @@ set -ex ../../yosys -l $1.log -q $1.ys NuSMV -bmc $1.smv >> $1.log grep "^-- invariant .* is true" $1.log - diff --git a/tests/smv/run-test.sh b/tests/smv/run-test.sh index c8264ac8a..7df3b65f1 100755 --- a/tests/smv/run-test.sh +++ b/tests/smv/run-test.sh @@ -16,4 +16,3 @@ all: $(addsuffix .ok,$(basename $(wildcard temp/test_*.il))) EOT ${MAKE:-make} -f temp/makefile - diff --git a/tests/sva/Makefile b/tests/sva/Makefile index d8c206664..a562012db 100644 --- a/tests/sva/Makefile +++ b/tests/sva/Makefile @@ -13,4 +13,3 @@ clean: rm -rf $(addsuffix _pass.sby,$(TESTS)) $(addsuffix _pass,$(TESTS)) rm -rf $(addsuffix _fail.sby,$(TESTS)) $(addsuffix _fail,$(TESTS)) rm -rf $(addsuffix .fst,$(TESTS)) - diff --git a/tests/sva/runtest.sh b/tests/sva/runtest.sh index 6a855188f..ee97e2d47 100644 --- a/tests/sva/runtest.sh +++ b/tests/sva/runtest.sh @@ -87,4 +87,3 @@ fi { set +x; } &>/dev/null touch $prefix.ok - diff --git a/tests/svtypes/enum_simple.ys b/tests/svtypes/enum_simple.ys index 36922f5e0..26a39943b 100644 --- a/tests/svtypes/enum_simple.ys +++ b/tests/svtypes/enum_simple.ys @@ -2,4 +2,3 @@ read_verilog -sv enum_simple.sv hierarchy; proc; opt; async2sync sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts -show-all - diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv index cd7b7953e..93af0040f 100644 --- a/tests/svtypes/typedef_scopes.sv +++ b/tests/svtypes/typedef_scopes.sv @@ -69,4 +69,3 @@ module other; between_t a = 8'h42; always @(*) assert(a == 8'h42); endmodule - diff --git a/tests/techmap/bmuxmap_pmux.ys b/tests/techmap/bmuxmap_pmux.ys index dd6a80131..89452813e 100644 --- a/tests/techmap/bmuxmap_pmux.ys +++ b/tests/techmap/bmuxmap_pmux.ys @@ -41,5 +41,3 @@ EOT hierarchy -auto-top equiv_opt -assert bmuxmap -pmux - - diff --git a/tests/techmap/bug5495.sh b/tests/techmap/bug5495.sh index d1ade0fb2..f8244efbe 100755 --- a/tests/techmap/bug5495.sh +++ b/tests/techmap/bug5495.sh @@ -9,4 +9,3 @@ if ! timeout 10 ${YOSYS} bug5495.v -p 'hierarchy; techmap; abc -script bug5495.a echo "Yosys failed to complete" exit 1 fi - diff --git a/tests/techmap/clockgate.lib b/tests/techmap/clockgate.lib index 584325108..5ec5b1e4a 100644 --- a/tests/techmap/clockgate.lib +++ b/tests/techmap/clockgate.lib @@ -110,4 +110,4 @@ library(test) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/techmap/clockgate.v b/tests/techmap/clockgate.v index 3b4936852..8b5637103 100644 --- a/tests/techmap/clockgate.v +++ b/tests/techmap/clockgate.v @@ -41,4 +41,4 @@ module dffe_wide_11( input clk, en, if ( en ) q1 <= d1; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/techmap/clockgate_bad.il b/tests/techmap/clockgate_bad.il index c967b04e6..ec4f7789a 100644 --- a/tests/techmap/clockgate_bad.il +++ b/tests/techmap/clockgate_bad.il @@ -28,4 +28,4 @@ module \bad2 connect \EN \en connect \Q \q1 end -end \ No newline at end of file +end diff --git a/tests/techmap/clockgate_neg.lib b/tests/techmap/clockgate_neg.lib index 5068f9c9a..e964adb5b 100644 --- a/tests/techmap/clockgate_neg.lib +++ b/tests/techmap/clockgate_neg.lib @@ -52,4 +52,4 @@ library(test) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/techmap/clockgate_pos.lib b/tests/techmap/clockgate_pos.lib index bab9e7cc7..02f5c251b 100644 --- a/tests/techmap/clockgate_pos.lib +++ b/tests/techmap/clockgate_pos.lib @@ -52,4 +52,4 @@ library(test) { direction : input; } } -} \ No newline at end of file +} diff --git a/tests/techmap/clockgate_wide.v b/tests/techmap/clockgate_wide.v index 687fd7104..4e1f600c4 100644 --- a/tests/techmap/clockgate_wide.v +++ b/tests/techmap/clockgate_wide.v @@ -5,4 +5,4 @@ module dffe_wide_11( input clk, input [1:0] en, if ( en[0] ) q1 <= d1; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/techmap/dfflibmap_dffsr_not_next.lib b/tests/techmap/dfflibmap_dffsr_not_next.lib index 579dedb10..f95096bc5 100644 --- a/tests/techmap/dfflibmap_dffsr_not_next.lib +++ b/tests/techmap/dfflibmap_dffsr_not_next.lib @@ -25,4 +25,4 @@ library (test_not_next) { preset : "!RN"; } } -} \ No newline at end of file +} diff --git a/tests/techmap/dfflibmap_formal.ys b/tests/techmap/dfflibmap_formal.ys index e5e61cd62..afa2c4d9d 100644 --- a/tests/techmap/dfflibmap_formal.ys +++ b/tests/techmap/dfflibmap_formal.ys @@ -265,4 +265,4 @@ flatten opt_clean -purge equiv_make top top_unmapped equiv equiv_induct -set-assumes equiv -equiv_status -assert equiv \ No newline at end of file +equiv_status -assert equiv diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v index 762e2938e..4cf706a97 100644 --- a/tests/techmap/mem_simple_4x1_map.v +++ b/tests/techmap/mem_simple_4x1_map.v @@ -149,4 +149,3 @@ module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); end endgenerate endmodule - diff --git a/tests/tools/cmp_tbdata.c b/tests/tools/cmp_tbdata.c index c0b12cd9b..a6bc9dae7 100644 --- a/tests/tools/cmp_tbdata.c +++ b/tests/tools/cmp_tbdata.c @@ -66,4 +66,3 @@ int main(int argc, char **argv) fclose(f2); return 0; } - diff --git a/tests/tools/profiler.pl b/tests/tools/profiler.pl index 456f634bc..99155eec7 100755 --- a/tests/tools/profiler.pl +++ b/tests/tools/profiler.pl @@ -52,4 +52,3 @@ printf "\nFull journal of headers:\n"; for (my $i = 0; $i <= $#lines_text; $i++) { printf "%3d %08.2f %s\n", $lines_depth[$i], $lines_time[$i], $lines_text[$i]; } - diff --git a/tests/tools/txt2tikztiming.py b/tests/tools/txt2tikztiming.py index 9c6cd3a19..e608ece99 100755 --- a/tests/tools/txt2tikztiming.py +++ b/tests/tools/txt2tikztiming.py @@ -103,4 +103,3 @@ for t in sorted(time_val.keys()): if last_time < stop_time: print("%f%s" % ((stop_time - last_time)*args.s, last_value), end='') print('') - diff --git a/tests/tools/vcd2txt.pl b/tests/tools/vcd2txt.pl index 92d3d1652..34758f290 100755 --- a/tests/tools/vcd2txt.pl +++ b/tests/tools/vcd2txt.pl @@ -58,4 +58,3 @@ for my $node (keys $vcd) { } } } - diff --git a/tests/various/attrib05_port_conn.v b/tests/various/attrib05_port_conn.v index e20e66319..75e2ebcb7 100644 --- a/tests/various/attrib05_port_conn.v +++ b/tests/various/attrib05_port_conn.v @@ -18,4 +18,3 @@ module foo(clk, rst, inp, out); bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); endmodule - diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v index 8c9fb2926..a91bcec1d 100644 --- a/tests/various/attrib07_func_call.v +++ b/tests/various/attrib07_func_call.v @@ -18,4 +18,3 @@ module foo(clk, rst, inp_a, inp_b, out); else out <= do_add (* combinational_adder *) (inp_a, inp_b); endmodule - diff --git a/tests/various/bug3515.ys b/tests/various/bug3515.ys index 783a75bb4..d086ad4e0 100644 --- a/tests/various/bug3515.ys +++ b/tests/various/bug3515.ys @@ -28,4 +28,3 @@ hierarchy -top mod_and_or opt extract -map ./bug3515.v select -assert-count 2 t:$and - diff --git a/tests/various/bug4909.ys b/tests/various/bug4909.ys index bf8cfb45b..f0cb33097 100644 --- a/tests/various/bug4909.ys +++ b/tests/various/bug4909.ys @@ -41,4 +41,3 @@ EOF prep splitcells - diff --git a/tests/various/deminout_unused.ys b/tests/various/deminout_unused.ys index 5ed00509d..67f322b47 100644 --- a/tests/various/deminout_unused.ys +++ b/tests/various/deminout_unused.ys @@ -11,4 +11,3 @@ proc tribuf deminout select -assert-count 1 i:x o:x %i - diff --git a/tests/various/dynamic_part_select/latch_1990_gate.v b/tests/various/dynamic_part_select/latch_1990_gate.v index a46183f23..36402a0ad 100644 --- a/tests/various/dynamic_part_select/latch_1990_gate.v +++ b/tests/various/dynamic_part_select/latch_1990_gate.v @@ -3,4 +3,3 @@ module latch_1990_gate (output wire [1:0] x); assign x = 2'b10; endmodule // latch_1990_gate - diff --git a/tests/various/dynamic_part_select/reversed.v b/tests/various/dynamic_part_select/reversed.v index 0268fa6bb..ff5808afb 100644 --- a/tests/various/dynamic_part_select/reversed.v +++ b/tests/various/dynamic_part_select/reversed.v @@ -11,4 +11,3 @@ module reversed #(parameter WIDTH=32, SELW=4, CTRLW=$clog2(WIDTH), DINW=2**SELW) dout[(WIDTH-ctrl*sel)-:SLICE] <= din; end endmodule - diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv index fe5ff3abd..6d90fda32 100644 --- a/tests/various/reg_wire_error.sv +++ b/tests/various/reg_wire_error.sv @@ -71,4 +71,3 @@ begin end endmodule - diff --git a/tests/various/scopeinfo.ys b/tests/various/scopeinfo.ys index f8d4ca31b..a261ddb45 100644 --- a/tests/various/scopeinfo.ys +++ b/tests/various/scopeinfo.ys @@ -107,4 +107,4 @@ select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/r:TYPE=module select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_inst_attr=inst_attr_deep %i select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_module_attr=module_attr_deep %i select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:cell_src %i -select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i \ No newline at end of file +select -assert-count 1 top/a:hdlname=some_inst?some_inst_deep top/a:module_src %i diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys index d778b92cd..69502cf09 100644 --- a/tests/various/sim_const.ys +++ b/tests/various/sim_const.ys @@ -10,4 +10,3 @@ EOT proc sim -clock clk -n 1 -w top select -assert-count 1 a:init=2'b10 top/q %i - diff --git a/tests/various/stat_area_by_width.lib b/tests/various/stat_area_by_width.lib index 1e98aa488..9dff055c9 100644 --- a/tests/various/stat_area_by_width.lib +++ b/tests/various/stat_area_by_width.lib @@ -22,4 +22,4 @@ cell ( "$bmux" ) { double_area_parameterised ( " 3.0, 6.0, 9.0, 12.0, 15.0, 18.0, 21.0, 24.0, 27.0, 30.0, 33.0, 36.0, 39.0, 42.0, 45.0, 48.0, 51.0, 54.0, 57.0, 60.0, 63.0, 66.0, 69.0, 72.0, 75.0, 78.0, 81.0, 84.0, 87.0, 90.0, 93.0, 96.0, 99.0, 102.0, 105.0, 108.0, 111.0, 114.0, 117.0, 120.0, 123.0, 126.0, 129.0, 132.0, 135.0, 138.0, 141.0, 144.0, 147.0, 150.0, 153.0, 156.0, 159.0, 162.0, 165.0, 168.0, 171.0, 174.0, 177.0, 180.0, 183.0, 186.0, 189.0, 192.0, 195.0, 198.0, 201.0, 204.0, 207.0, 210.0, 213.0, 216.0, 219.0, 222.0, 225.0, 228.0, 231.0, 234.0, 237.0, 240.0, 243.0, 246.0, 249.0, 252.0, 255.0, 258.0, 261.0, 264.0, 267.0, 270.0, 273.0, 276.0, 279.0, 282.0, 285.0, 288.0, 291.0, 294.0, 297.0, 300.0, 303.0, 306.0, 309.0, 312.0, 315.0, 318.0, 321.0, 324.0, 327.0, 330.0, 333.0, 336.0, 339.0, 342.0, 345.0, 348.0, 351.0, 354.0, 357.0, 360.0, 363.0, 366.0, 369.0, 372.0, 375.0, 378.0, 381.0, 384.0,", " 6.0, 12.0, 18.0, 24.0, 30.0, 36.0, 42.0, 48.0, 54.0, 60.0, 66.0, 72.0, 78.0, 84.0, 90.0, 96.0, 102.0, 108.0, 114.0, 120.0, 126.0, 132.0, 138.0, 144.0, 150.0, 156.0, 162.0, 168.0, 174.0, 180.0, 186.0, 192.0, 198.0, 204.0, 210.0, 216.0, 222.0, 228.0, 234.0, 240.0, 246.0, 252.0, 258.0, 264.0, 270.0, 276.0, 282.0, 288.0, 294.0, 300.0, 306.0, 312.0, 318.0, 324.0, 330.0, 336.0, 342.0, 348.0, 354.0, 360.0, 366.0, 372.0, 378.0, 384.0, 390.0, 396.0, 402.0, 408.0, 414.0, 420.0, 426.0, 432.0, 438.0, 444.0, 450.0, 456.0, 462.0, 468.0, 474.0, 480.0, 486.0, 492.0, 498.0, 504.0, 510.0, 516.0, 522.0, 528.0, 534.0, 540.0, 546.0, 552.0, 558.0, 564.0, 570.0, 576.0, 582.0, 588.0, 594.0, 600.0, 606.0, 612.0, 618.0, 624.0, 630.0, 636.0, 642.0, 648.0, 654.0, 660.0, 666.0, 672.0, 678.0, 684.0, 690.0, 696.0, 702.0, 708.0, 714.0, 720.0, 726.0, 732.0, 738.0, 744.0, 750.0, 756.0, 762.0, 768.0,", " 9.0, 18.0, 27.0, 36.0, 45.0, 54.0, 63.0, 72.0, 81.0, 90.0, 99.0, 108.0, 117.0, 126.0, 135.0, 144.0, 153.0, 162.0, 171.0, 180.0, 189.0, 198.0, 207.0, 216.0, 225.0, 234.0, 243.0, 252.0, 261.0, 270.0, 279.0, 288.0, 297.0, 306.0, 315.0, 324.0, 333.0, 342.0, 351.0, 360.0, 369.0, 378.0, 387.0, 396.0, 405.0, 414.0, 423.0, 432.0, 441.0, 450.0, 459.0, 468.0, 477.0, 486.0, 495.0, 504.0, 513.0, 522.0, 531.0, 540.0, 549.0, 558.0, 567.0, 576.0, 585.0, 594.0, 603.0, 612.0, 621.0, 630.0, 639.0, 648.0, 657.0, 666.0, 675.0, 684.0, 693.0, 702.0, 711.0, 720.0, 729.0, 738.0, 747.0, 756.0, 765.0, 774.0, 783.0, 792.0, 801.0, 810.0, 819.0, 828.0, 837.0, 846.0, 855.0, 864.0, 873.0, 882.0, 891.0, 900.0, 909.0, 918.0, 927.0, 936.0, 945.0, 954.0, 963.0, 972.0, 981.0, 990.0, 999.0, 1008.0, 1017.0, 1026.0, 1035.0, 1044.0, 1053.0, 1062.0, 1071.0, 1080.0, 1089.0, 1098.0, 1107.0, 1116.0, 1125.0, 1134.0, 1143.0, 1152.0,", " 12.0, 24.0, 36.0, 48.0, 60.0, 72.0, 84.0, 96.0, 108.0, 120.0, 132.0, 144.0, 156.0, 168.0, 180.0, 192.0, 204.0, 216.0, 228.0, 240.0, 252.0, 264.0, 276.0, 288.0, 300.0, 312.0, 324.0, 336.0, 348.0, 360.0, 372.0, 384.0, 396.0, 408.0, 420.0, 432.0, 444.0, 456.0, 468.0, 480.0, 492.0, 504.0, 516.0, 528.0, 540.0, 552.0, 564.0, 576.0, 588.0, 600.0, 612.0, 624.0, 636.0, 648.0, 660.0, 672.0, 684.0, 696.0, 708.0, 720.0, 732.0, 744.0, 756.0, 768.0, 780.0, 792.0, 804.0, 816.0, 828.0, 840.0, 852.0, 864.0, 876.0, 888.0, 900.0, 912.0, 924.0, 936.0, 948.0, 960.0, 972.0, 984.0, 996.0, 1008.0, 1020.0, 1032.0, 1044.0, 1056.0, 1068.0, 1080.0, 1092.0, 1104.0, 1116.0, 1128.0, 1140.0, 1152.0, 1164.0, 1176.0, 1188.0, 1200.0, 1212.0, 1224.0, 1236.0, 1248.0, 1260.0, 1272.0, 1284.0, 1296.0, 1308.0, 1320.0, 1332.0, 1344.0, 1356.0, 1368.0, 1380.0, 1392.0, 1404.0, 1416.0, 1428.0, 1440.0, 1452.0, 1464.0, 1476.0, 1488.0, 1500.0, 1512.0, 1524.0, 1536.0,", " 15.0, 30.0, 45.0, 60.0, 75.0, 90.0, 105.0, 120.0, 135.0, 150.0, 165.0, 180.0, 195.0, 210.0, 225.0, 240.0, 255.0, 270.0, 285.0, 300.0, 315.0, 330.0, 345.0, 360.0, 375.0, 390.0, 405.0, 420.0, 435.0, 450.0, 465.0, 480.0, 495.0, 510.0, 525.0, 540.0, 555.0, 570.0, 585.0, 600.0, 615.0, 630.0, 645.0, 660.0, 675.0, 690.0, 705.0, 720.0, 735.0, 750.0, 765.0, 780.0, 795.0, 810.0, 825.0, 840.0, 855.0, 870.0, 885.0, 900.0, 915.0, 930.0, 945.0, 960.0, 975.0, 990.0, 1005.0, 1020.0, 1035.0, 1050.0, 1065.0, 1080.0, 1095.0, 1110.0, 1125.0, 1140.0, 1155.0, 1170.0, 1185.0, 1200.0, 1215.0, 1230.0, 1245.0, 1260.0, 1275.0, 1290.0, 1305.0, 1320.0, 1335.0, 1350.0, 1365.0, 1380.0, 1395.0, 1410.0, 1425.0, 1440.0, 1455.0, 1470.0, 1485.0, 1500.0, 1515.0, 1530.0, 1545.0, 1560.0, 1575.0, 1590.0, 1605.0, 1620.0, 1635.0, 1650.0, 1665.0, 1680.0, 1695.0, 1710.0, 1725.0, 1740.0, 1755.0, 1770.0, 1785.0, 1800.0, 1815.0, 1830.0, 1845.0, 1860.0, 1875.0, 1890.0, 1905.0, 1920.0,", " 18.0, 36.0, 54.0, 72.0, 90.0, 108.0, 126.0, 144.0, 162.0, 180.0, 198.0, 216.0, 234.0, 252.0, 270.0, 288.0, 306.0, 324.0, 342.0, 360.0, 378.0, 396.0, 414.0, 432.0, 450.0, 468.0, 486.0, 504.0, 522.0, 540.0, 558.0, 576.0, 594.0, 612.0, 630.0, 648.0, 666.0, 684.0, 702.0, 720.0, 738.0, 756.0, 774.0, 792.0, 810.0, 828.0, 846.0, 864.0, 882.0, 900.0, 918.0, 936.0, 954.0, 972.0, 990.0, 1008.0, 1026.0, 1044.0, 1062.0, 1080.0, 1098.0, 1116.0, 1134.0, 1152.0, 1170.0, 1188.0, 1206.0, 1224.0, 1242.0, 1260.0, 1278.0, 1296.0, 1314.0, 1332.0, 1350.0, 1368.0, 1386.0, 1404.0, 1422.0, 1440.0, 1458.0, 1476.0, 1494.0, 1512.0, 1530.0, 1548.0, 1566.0, 1584.0, 1602.0, 1620.0, 1638.0, 1656.0, 1674.0, 1692.0, 1710.0, 1728.0, 1746.0, 1764.0, 1782.0, 1800.0, 1818.0, 1836.0, 1854.0, 1872.0, 1890.0, 1908.0, 1926.0, 1944.0, 1962.0, 1980.0, 1998.0, 2016.0, 2034.0, 2052.0, 2070.0, 2088.0, 2106.0, 2124.0, 2142.0, 2160.0, 2178.0, 2196.0, 2214.0, 2232.0, 2250.0, 2268.0, 2286.0, 2304.0,", " 21.0, 42.0, 63.0, 84.0, 105.0, 126.0, 147.0, 168.0, 189.0, 210.0, 231.0, 252.0, 273.0, 294.0, 315.0, 336.0, 357.0, 378.0, 399.0, 420.0, 441.0, 462.0, 483.0, 504.0, 525.0, 546.0, 567.0, 588.0, 609.0, 630.0, 651.0, 672.0, 693.0, 714.0, 735.0, 756.0, 777.0, 798.0, 819.0, 840.0, 861.0, 882.0, 903.0, 924.0, 945.0, 966.0, 987.0, 1008.0, 1029.0, 1050.0, 1071.0, 1092.0, 1113.0, 1134.0, 1155.0, 1176.0, 1197.0, 1218.0, 1239.0, 1260.0, 1281.0, 1302.0, 1323.0, 1344.0, 1365.0, 1386.0, 1407.0, 1428.0, 1449.0, 1470.0, 1491.0, 1512.0, 1533.0, 1554.0, 1575.0, 1596.0, 1617.0, 1638.0, 1659.0, 1680.0, 1701.0, 1722.0, 1743.0, 1764.0, 1785.0, 1806.0, 1827.0, 1848.0, 1869.0, 1890.0, 1911.0, 1932.0, 1953.0, 1974.0, 1995.0, 2016.0, 2037.0, 2058.0, 2079.0, 2100.0, 2121.0, 2142.0, 2163.0, 2184.0, 2205.0, 2226.0, 2247.0, 2268.0, 2289.0, 2310.0, 2331.0, 2352.0, 2373.0, 2394.0, 2415.0, 2436.0, 2457.0, 2478.0, 2499.0, 2520.0, 2541.0, 2562.0, 2583.0, 2604.0, 2625.0, 2646.0, 2667.0, 2688.0,", " 24.0, 48.0, 72.0, 96.0, 120.0, 144.0, 168.0, 192.0, 216.0, 240.0, 264.0, 288.0, 312.0, 336.0, 360.0, 384.0, 408.0, 432.0, 456.0, 480.0, 504.0, 528.0, 552.0, 576.0, 600.0, 624.0, 648.0, 672.0, 696.0, 720.0, 744.0, 768.0, 792.0, 816.0, 840.0, 864.0, 888.0, 912.0, 936.0, 960.0, 984.0, 1008.0, 1032.0, 1056.0, 1080.0, 1104.0, 1128.0, 1152.0, 1176.0, 1200.0, 1224.0, 1248.0, 1272.0, 1296.0, 1320.0, 1344.0, 1368.0, 1392.0, 1416.0, 1440.0, 1464.0, 1488.0, 1512.0, 1536.0, 1560.0, 1584.0, 1608.0, 1632.0, 1656.0, 1680.0, 1704.0, 1728.0, 1752.0, 1776.0, 1800.0, 1824.0, 1848.0, 1872.0, 1896.0, 1920.0, 1944.0, 1968.0, 1992.0, 2016.0, 2040.0, 2064.0, 2088.0, 2112.0, 2136.0, 2160.0, 2184.0, 2208.0, 2232.0, 2256.0, 2280.0, 2304.0, 2328.0, 2352.0, 2376.0, 2400.0, 2424.0, 2448.0, 2472.0, 2496.0, 2520.0, 2544.0, 2568.0, 2592.0, 2616.0, 2640.0, 2664.0, 2688.0, 2712.0, 2736.0, 2760.0, 2784.0, 2808.0, 2832.0, 2856.0, 2880.0, 2904.0, 2928.0, 2952.0, 2976.0, 3000.0, 3024.0, 3048.0, 3072.0,", " 27.0, 54.0, 81.0, 108.0, 135.0, 162.0, 189.0, 216.0, 243.0, 270.0, 297.0, 324.0, 351.0, 378.0, 405.0, 432.0, 459.0, 486.0, 513.0, 540.0, 567.0, 594.0, 621.0, 648.0, 675.0, 702.0, 729.0, 756.0, 783.0, 810.0, 837.0, 864.0, 891.0, 918.0, 945.0, 972.0, 999.0, 1026.0, 1053.0, 1080.0, 1107.0, 1134.0, 1161.0, 1188.0, 1215.0, 1242.0, 1269.0, 1296.0, 1323.0, 1350.0, 1377.0, 1404.0, 1431.0, 1458.0, 1485.0, 1512.0, 1539.0, 1566.0, 1593.0, 1620.0, 1647.0, 1674.0, 1701.0, 1728.0, 1755.0, 1782.0, 1809.0, 1836.0, 1863.0, 1890.0, 1917.0, 1944.0, 1971.0, 1998.0, 2025.0, 2052.0, 2079.0, 2106.0, 2133.0, 2160.0, 2187.0, 2214.0, 2241.0, 2268.0, 2295.0, 2322.0, 2349.0, 2376.0, 2403.0, 2430.0, 2457.0, 2484.0, 2511.0, 2538.0, 2565.0, 2592.0, 2619.0, 2646.0, 2673.0, 2700.0, 2727.0, 2754.0, 2781.0, 2808.0, 2835.0, 2862.0, 2889.0, 2916.0, 2943.0, 2970.0, 2997.0, 3024.0, 3051.0, 3078.0, 3105.0, 3132.0, 3159.0, 3186.0, 3213.0, 3240.0, 3267.0, 3294.0, 3321.0, 3348.0, 3375.0, 3402.0, 3429.0, 3456.0,", " 30.0, 60.0, 90.0, 120.0, 150.0, 180.0, 210.0, 240.0, 270.0, 300.0, 330.0, 360.0, 390.0, 420.0, 450.0, 480.0, 510.0, 540.0, 570.0, 600.0, 630.0, 660.0, 690.0, 720.0, 750.0, 780.0, 810.0, 840.0, 870.0, 900.0, 930.0, 960.0, 990.0, 1020.0, 1050.0, 1080.0, 1110.0, 1140.0, 1170.0, 1200.0, 1230.0, 1260.0, 1290.0, 1320.0, 1350.0, 1380.0, 1410.0, 1440.0, 1470.0, 1500.0, 1530.0, 1560.0, 1590.0, 1620.0, 1650.0, 1680.0, 1710.0, 1740.0, 1770.0, 1800.0, 1830.0, 1860.0, 1890.0, 1920.0, 1950.0, 1980.0, 2010.0, 2040.0, 2070.0, 2100.0, 2130.0, 2160.0, 2190.0, 2220.0, 2250.0, 2280.0, 2310.0, 2340.0, 2370.0, 2400.0, 2430.0, 2460.0, 2490.0, 2520.0, 2550.0, 2580.0, 2610.0, 2640.0, 2670.0, 2700.0, 2730.0, 2760.0, 2790.0, 2820.0, 2850.0, 2880.0, 2910.0, 2940.0, 2970.0, 3000.0, 3030.0, 3060.0, 3090.0, 3120.0, 3150.0, 3180.0, 3210.0, 3240.0, 3270.0, 3300.0, 3330.0, 3360.0, 3390.0, 3420.0, 3450.0, 3480.0, 3510.0, 3540.0, 3570.0, 3600.0, 3630.0, 3660.0, 3690.0, 3720.0, 3750.0, 3780.0, 3810.0, 3840.0,", " 33.0, 66.0, 99.0, 132.0, 165.0, 198.0, 231.0, 264.0, 297.0, 330.0, 363.0, 396.0, 429.0, 462.0, 495.0, 528.0, 561.0, 594.0, 627.0, 660.0, 693.0, 726.0, 759.0, 792.0, 825.0, 858.0, 891.0, 924.0, 957.0, 990.0, 1023.0, 1056.0, 1089.0, 1122.0, 1155.0, 1188.0, 1221.0, 1254.0, 1287.0, 1320.0, 1353.0, 1386.0, 1419.0, 1452.0, 1485.0, 1518.0, 1551.0, 1584.0, 1617.0, 1650.0, 1683.0, 1716.0, 1749.0, 1782.0, 1815.0, 1848.0, 1881.0, 1914.0, 1947.0, 1980.0, 2013.0, 2046.0, 2079.0, 2112.0, 2145.0, 2178.0, 2211.0, 2244.0, 2277.0, 2310.0, 2343.0, 2376.0, 2409.0, 2442.0, 2475.0, 2508.0, 2541.0, 2574.0, 2607.0, 2640.0, 2673.0, 2706.0, 2739.0, 2772.0, 2805.0, 2838.0, 2871.0, 2904.0, 2937.0, 2970.0, 3003.0, 3036.0, 3069.0, 3102.0, 3135.0, 3168.0, 3201.0, 3234.0, 3267.0, 3300.0, 3333.0, 3366.0, 3399.0, 3432.0, 3465.0, 3498.0, 3531.0, 3564.0, 3597.0, 3630.0, 3663.0, 3696.0, 3729.0, 3762.0, 3795.0, 3828.0, 3861.0, 3894.0, 3927.0, 3960.0, 3993.0, 4026.0, 4059.0, 4092.0, 4125.0, 4158.0, 4191.0, 4224.0,", " 36.0, 72.0, 108.0, 144.0, 180.0, 216.0, 252.0, 288.0, 324.0, 360.0, 396.0, 432.0, 468.0, 504.0, 540.0, 576.0, 612.0, 648.0, 684.0, 720.0, 756.0, 792.0, 828.0, 864.0, 900.0, 936.0, 972.0, 1008.0, 1044.0, 1080.0, 1116.0, 1152.0, 1188.0, 1224.0, 1260.0, 1296.0, 1332.0, 1368.0, 1404.0, 1440.0, 1476.0, 1512.0, 1548.0, 1584.0, 1620.0, 1656.0, 1692.0, 1728.0, 1764.0, 1800.0, 1836.0, 1872.0, 1908.0, 1944.0, 1980.0, 2016.0, 2052.0, 2088.0, 2124.0, 2160.0, 2196.0, 2232.0, 2268.0, 2304.0, 2340.0, 2376.0, 2412.0, 2448.0, 2484.0, 2520.0, 2556.0, 2592.0, 2628.0, 2664.0, 2700.0, 2736.0, 2772.0, 2808.0, 2844.0, 2880.0, 2916.0, 2952.0, 2988.0, 3024.0, 3060.0, 3096.0, 3132.0, 3168.0, 3204.0, 3240.0, 3276.0, 3312.0, 3348.0, 3384.0, 3420.0, 3456.0, 3492.0, 3528.0, 3564.0, 3600.0, 3636.0, 3672.0, 3708.0, 3744.0, 3780.0, 3816.0, 3852.0, 3888.0, 3924.0, 3960.0, 3996.0, 4032.0, 4068.0, 4104.0, 4140.0, 4176.0, 4212.0, 4248.0, 4284.0, 4320.0, 4356.0, 4392.0, 4428.0, 4464.0, 4500.0, 4536.0, 4572.0, 4608.0,", " 39.0, 78.0, 117.0, 156.0, 195.0, 234.0, 273.0, 312.0, 351.0, 390.0, 429.0, 468.0, 507.0, 546.0, 585.0, 624.0, 663.0, 702.0, 741.0, 780.0, 819.0, 858.0, 897.0, 936.0, 975.0, 1014.0, 1053.0, 1092.0, 1131.0, 1170.0, 1209.0, 1248.0, 1287.0, 1326.0, 1365.0, 1404.0, 1443.0, 1482.0, 1521.0, 1560.0, 1599.0, 1638.0, 1677.0, 1716.0, 1755.0, 1794.0, 1833.0, 1872.0, 1911.0, 1950.0, 1989.0, 2028.0, 2067.0, 2106.0, 2145.0, 2184.0, 2223.0, 2262.0, 2301.0, 2340.0, 2379.0, 2418.0, 2457.0, 2496.0, 2535.0, 2574.0, 2613.0, 2652.0, 2691.0, 2730.0, 2769.0, 2808.0, 2847.0, 2886.0, 2925.0, 2964.0, 3003.0, 3042.0, 3081.0, 3120.0, 3159.0, 3198.0, 3237.0, 3276.0, 3315.0, 3354.0, 3393.0, 3432.0, 3471.0, 3510.0, 3549.0, 3588.0, 3627.0, 3666.0, 3705.0, 3744.0, 3783.0, 3822.0, 3861.0, 3900.0, 3939.0, 3978.0, 4017.0, 4056.0, 4095.0, 4134.0, 4173.0, 4212.0, 4251.0, 4290.0, 4329.0, 4368.0, 4407.0, 4446.0, 4485.0, 4524.0, 4563.0, 4602.0, 4641.0, 4680.0, 4719.0, 4758.0, 4797.0, 4836.0, 4875.0, 4914.0, 4953.0, 4992.0,", ) ; } -} \ No newline at end of file +} diff --git a/tests/various/stat_hierarchy.ys b/tests/various/stat_hierarchy.ys index f41165629..93cd5e8e1 100644 --- a/tests/various/stat_hierarchy.ys +++ b/tests/various/stat_hierarchy.ys @@ -58,5 +58,3 @@ logger -expect log "2 94.349 - - sg13g2_dfrbp_1" 2 logger -expect log "2 94.349 2 - submodules" 2 logger -expect-no-warnings stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top -hierarchy - - diff --git a/tests/various/stat_high_level.ys b/tests/various/stat_high_level.ys index 03e5e957e..9f94bf764 100644 --- a/tests/various/stat_high_level.ys +++ b/tests/various/stat_high_level.ys @@ -88,5 +88,3 @@ logger -expect log "2 51 - - \$reduce_xor" 2 logger -expect log "8 66 2 5 cells" 2 logger -expect-no-warnings stat -liberty ./stat_area_by_width.lib -top \top -hierarchy - - diff --git a/tests/various/stat_high_level2.ys b/tests/various/stat_high_level2.ys index 63d59da95..3493c1239 100644 --- a/tests/various/stat_high_level2.ys +++ b/tests/various/stat_high_level2.ys @@ -87,5 +87,3 @@ logger -expect log "3 37.5 3 37.5 cells" 1 logger -expect log "8 80 2 5 cells" 2 logger -expect-no-warnings stat -liberty ./stat_area_by_width.lib -top \top -hierarchy - - diff --git a/tests/verific/case.sv b/tests/verific/case.sv index ed8529b91..a03a9d1f8 100644 --- a/tests/verific/case.sv +++ b/tests/verific/case.sv @@ -25,4 +25,3 @@ module top ( endcase end endmodule - diff --git a/tests/verific/rom_case.ys b/tests/verific/rom_case.ys index 253cc0766..49719d2db 100644 --- a/tests/verific/rom_case.ys +++ b/tests/verific/rom_case.ys @@ -75,4 +75,4 @@ dump memory_libmap -lib ../memlib/memlib_block_sdp.txt memory_map stat -select -assert-count 1 t:RAM_BLOCK_SDP \ No newline at end of file +select -assert-count 1 t:RAM_BLOCK_SDP diff --git a/tests/verilog/for_loop_signed_index.ys b/tests/verilog/for_loop_signed_index.ys index a2bde3395..87e6b14cb 100644 --- a/tests/verilog/for_loop_signed_index.ys +++ b/tests/verilog/for_loop_signed_index.ys @@ -53,4 +53,4 @@ EOT hierarchy -top unsigned_index proc -sat -set a 1 -prove y 0 -verify \ No newline at end of file +sat -set a 1 -prove y 0 -verify diff --git a/tests/verilog/issue4402.ys b/tests/verilog/issue4402.ys index 4fcf816a3..f5ddca7d2 100644 --- a/tests/verilog/issue4402.ys +++ b/tests/verilog/issue4402.ys @@ -29,4 +29,4 @@ proc write_verilog temp/issue4402_syn.v # Port declaration must include the signed keyword. -! grep -q "input signed wire0" temp/issue4402_syn.v \ No newline at end of file +! grep -q "input signed wire0" temp/issue4402_syn.v diff --git a/tests/verilog/issue5745.ys b/tests/verilog/issue5745.ys index 938ead63a..1e16b8373 100644 --- a/tests/verilog/issue5745.ys +++ b/tests/verilog/issue5745.ys @@ -15,4 +15,4 @@ endmodule EOT chparam -set p2 11 hierarchy -top mod -sat -prove k 1 -verify \ No newline at end of file +sat -prove k 1 -verify diff --git a/tests/verilog/unreachable_case_sign.ys b/tests/verilog/unreachable_case_sign.ys index 569c8a313..48f7993f7 100644 --- a/tests/verilog/unreachable_case_sign.ys +++ b/tests/verilog/unreachable_case_sign.ys @@ -32,4 +32,3 @@ EOT prep -top top async2sync sim -n 3 -clock clk - diff --git a/tests/vloghtb/run-test.sh b/tests/vloghtb/run-test.sh index 29f7c2680..11b93f890 100755 --- a/tests/vloghtb/run-test.sh +++ b/tests/vloghtb/run-test.sh @@ -12,4 +12,3 @@ rm -rf log_test_* ${MAKE:-make} EXIT_ON_ERROR=1 YOSYS_BIN=$PWD/../../yosys YOSYS_SCRIPT="proc;;" check_yosys ${MAKE:-make} -f test_makefile MODE=share ${MAKE:-make} -f test_makefile MODE=mapopt - diff --git a/tests/vloghtb/test_makefile b/tests/vloghtb/test_makefile index 174dbbc2c..0d87d5045 100644 --- a/tests/vloghtb/test_makefile +++ b/tests/vloghtb/test_makefile @@ -6,4 +6,3 @@ run: $(addprefix log_test_$(MODE)/,$(addsuffix .txt,$(TESTS))) log_test_$(MODE)/%.txt: rtl/%.v @bash test_$(MODE).sh $< - From a6893422070da115bc19b0ff1c9efe5367f29088 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:24:59 +0200 Subject: [PATCH 049/101] Remove trailing whitespaces --- CHANGELOG | 44 +- backends/aiger/xaiger.cc | 2 +- backends/functional/smtlib.cc | 6 +- backends/functional/smtlib_rosette.cc | 2 +- backends/functional/test_generic.cc | 2 +- backends/smt2/ywio.py | 4 +- cmake/YosysAbc.cmake | 6 +- .../appendix/APPNOTE_010_Verilog_to_BLIF.rst | 6 +- .../appendix/APPNOTE_012_Verilog_to_BTOR.rst | 2 +- docs/source/appendix/primer.rst | 4 +- docs/source/appendix/rtlil_text.rst | 32 +- docs/source/cell/word_logic.rst | 2 +- docs/source/cmd/index_internal.rst | 6 +- docs/source/code_examples/fifo/Makefile | 2 +- docs/source/code_examples/fifo/fifo.v | 4 +- docs/source/code_examples/fifo/fifo.ys | 2 +- .../macro_commands/synth_ice40.ys | 4 +- docs/source/code_examples/opt/opt_expr.ys | 2 +- docs/source/code_examples/opt/opt_muxtree.ys | 2 +- docs/source/code_examples/show/cmos.ys | 4 +- docs/source/getting_started/example_synth.rst | 12 +- docs/source/getting_started/installation.rst | 2 +- .../getting_started/scripting_intro.rst | 4 +- docs/source/introduction.rst | 22 +- docs/source/literature.bib | 66 +- .../interactive_investigation.rst | 32 +- .../more_scripting/load_design.rst | 2 +- .../using_yosys/more_scripting/selections.rst | 20 +- .../using_yosys/synthesis/cell_libs.rst | 4 +- docs/source/using_yosys/synthesis/extract.rst | 4 +- docs/source/using_yosys/synthesis/fsm.rst | 2 +- docs/source/using_yosys/synthesis/memory.rst | 12 +- .../using_yosys/synthesis/techmap_synth.rst | 2 +- .../extending_yosys/advanced_bugpoint.rst | 2 +- .../extending_yosys/extensions.rst | 2 +- docs/source/yosys_internals/flow/index.rst | 2 +- .../yosys_internals/flow/verilog_frontend.rst | 10 +- docs/source/yosys_internals/formats/index.rst | 2 +- docs/tests/macro_commands.py | 2 +- docs/util/RtlilLexer.py | 2 +- docs/util/cell_documenter.py | 28 +- docs/util/cmd_documenter.py | 18 +- docs/util/custom_directives.py | 30 +- examples/intel/asicworld_lfsr/lfsr_updown.v | 6 +- .../intel/asicworld_lfsr/lfsr_updown_tb.v | 2 +- examples/smtbmc/glift/C7552.v | 838 ++++---- examples/smtbmc/glift/C7552.ys | 2 +- examples/smtbmc/glift/C880.v | 98 +- examples/smtbmc/glift/C880.ys | 2 +- examples/smtbmc/glift/alu2.v | 66 +- examples/smtbmc/glift/alu2.ys | 2 +- examples/smtbmc/glift/alu4.v | 142 +- examples/smtbmc/glift/alu4.ys | 2 +- examples/smtbmc/glift/t481.v | 12 +- examples/smtbmc/glift/t481.ys | 2 +- examples/smtbmc/glift/too_large.v | 68 +- examples/smtbmc/glift/too_large.ys | 2 +- examples/smtbmc/glift/ttt2.v | 44 +- examples/smtbmc/glift/ttt2.ys | 2 +- examples/smtbmc/glift/x1.v | 86 +- examples/smtbmc/glift/x1.ys | 2 +- frontends/verific/verific.cc | 34 +- kernel/cellhelp.py | 4 +- kernel/compressor_tree.cc | 2 +- kernel/functional.h | 8 +- kernel/io.h | 6 +- kernel/tclapi.cc | 2 +- kernel/topo_scc.h | 2 +- passes/cmds/check.cc | 6 +- passes/cmds/linecoverage.cc | 4 +- passes/cmds/linux_perf.cc | 2 +- passes/cmds/logger.cc | 6 +- passes/cmds/select.cc | 2 +- passes/cmds/setenv.cc | 4 +- passes/cmds/timeest.cc | 6 +- passes/memory/memory_libmap.cc | 4 +- passes/opt/muxpack.cc | 2 +- passes/opt/opt_balance_tree.cc | 32 +- passes/opt/opt_hier.cc | 4 +- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_share.cc | 2 +- passes/opt/peepopt_muldiv_c.pmg | 8 +- passes/opt/peepopt_shiftadd.pmg | 4 +- passes/sat/cutpoint.cc | 2 +- passes/sat/qbfsat.h | 2 +- passes/sat/sim.cc | 48 +- passes/sat/synthprop.cc | 2 +- passes/techmap/abc9.cc | 2 +- passes/techmap/abc_new.cc | 2 +- passes/techmap/booth.cc | 4 +- passes/techmap/dfflegalize.cc | 2 +- passes/techmap/extract_counter.cc | 4 +- passes/techmap/libparse.cc | 4 +- passes/techmap/lut2mux.cc | 6 +- passes/techmap/techmap.cc | 2 +- techlibs/analogdevices/cells_sim.v | 4 +- techlibs/anlogic/anlogic_fixcarry.cc | 16 +- techlibs/anlogic/arith_map.v | 4 +- techlibs/anlogic/cells_sim.v | 10 +- techlibs/anlogic/eagle_bb.v | 24 +- techlibs/common/mul2dsp.v | 4 +- techlibs/common/simlib.v | 16 +- techlibs/efinix/arith_map.v | 6 +- techlibs/efinix/brams_map.v | 4 +- techlibs/efinix/cells_sim.v | 28 +- techlibs/efinix/efinix_fixcarry.cc | 14 +- techlibs/fabulous/prims.v | 26 +- techlibs/fix_mod.py | 2 +- techlibs/gatemate/gatemate_foldinv.cc | 2 +- techlibs/gowin/cells_sim.v | 24 +- techlibs/gowin/cells_xtra_gw1n.v | 228 +- techlibs/gowin/cells_xtra_gw2a.v | 266 +-- techlibs/gowin/cells_xtra_gw5a.v | 1836 ++++++++--------- techlibs/ice40/ice40_dsp.pmg | 4 +- techlibs/intel_alm/common/abc9_map.v | 4 +- techlibs/intel_alm/common/megafunction_bb.v | 82 +- techlibs/lattice/cells_sim_nexus.v | 4 +- techlibs/lattice/dsp_map_nexus.v | 6 +- techlibs/lattice/lattice_dsp_nexus.cc | 4 +- techlibs/lattice/lattice_dsp_nexus.pmg | 8 +- techlibs/lattice/lattice_gsr.cc | 4 +- techlibs/microchip/LSRAM.txt | 36 +- techlibs/microchip/LSRAM_map.v | 16 +- techlibs/microchip/arith_map.v | 2 +- techlibs/microchip/cells_sim.v | 14 +- techlibs/microchip/microchip_dsp.pmg | 24 +- techlibs/microchip/microchip_dsp_CREG.pmg | 6 +- techlibs/microchip/microchip_dsp_cascade.pmg | 18 +- techlibs/microchip/polarfire_dsp_map.v | 10 +- techlibs/microchip/uSRAM.txt | 12 +- techlibs/microchip/uSRAM_map.v | 4 +- techlibs/nanoxplore/brams_init.vh | 2 +- techlibs/nanoxplore/cells_sim_u.v | 8 +- techlibs/nanoxplore/nx_carry.cc | 8 +- techlibs/nanoxplore/rf_rams_map_l.v | 2 +- techlibs/nanoxplore/rf_rams_map_m.v | 2 +- techlibs/nanoxplore/synth_nanoxplore.cc | 6 +- techlibs/quicklogic/pp3/abc9_map.v | 4 +- techlibs/quicklogic/ql_bram_merge.cc | 2 +- techlibs/quicklogic/ql_bram_types.cc | 6 +- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 2 +- techlibs/quicklogic/synth_quicklogic.cc | 2 +- techlibs/sf2/NOTES.txt | 4 +- techlibs/xilinx/tests/test_dsp_model.v | 2 +- .../analogdevices/asym_ram_sdp_read_wider.v | 2 +- tests/arch/analogdevices/attributes_test.ys | 8 +- tests/arch/analogdevices/blockram.ys | 4 +- tests/arch/analogdevices/bug1598.ys | 6 +- tests/arch/analogdevices/dsp_abc9.ys | 4 +- tests/arch/common/blockram.v | 2 +- tests/arch/common/fsm.v | 2 +- tests/arch/common/shifter.v | 2 +- tests/arch/ecp5/bug1598.ys | 4 +- tests/arch/ecp5/memories.ys | 2 +- tests/arch/ecp5/shifter.ys | 2 +- tests/arch/ice40/bug1598.ys | 4 +- tests/arch/ice40/bug1626.ys | 8 +- tests/arch/ice40/ice40_dsp_const.ys | 6 +- tests/arch/ice40/spram.v | 2 +- tests/arch/microchip/dff.ys | 6 +- tests/arch/microchip/dff_opt.ys | 6 +- tests/arch/microchip/dsp.ys | 8 +- tests/arch/microchip/mult.ys | 6 +- tests/arch/microchip/ram_SDP.ys | 8 +- tests/arch/microchip/ram_TDP.ys | 8 +- tests/arch/microchip/reduce.ys | 6 +- tests/arch/microchip/simple_ram.ys | 6 +- tests/arch/microchip/uram_ar.ys | 8 +- tests/arch/microchip/uram_sr.ys | 8 +- tests/arch/microchip/widemux.ys | 6 +- tests/arch/nanoxplore/meminit.v | 2 +- tests/arch/nanoxplore/meminit.ys | 6 +- tests/arch/quicklogic/qlf_k6n10f/dffs.ys | 4 +- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 4 +- tests/arch/quicklogic/qlf_k6n10f/meminit.v | 2 +- tests/arch/xilinx/asym_ram_sdp_read_wider.v | 2 +- tests/arch/xilinx/attributes_test.ys | 8 +- tests/arch/xilinx/blockram.ys | 4 +- tests/arch/xilinx/bug1598.ys | 4 +- tests/arch/xilinx/xilinx_srl.v | 2 +- tests/asicworld/code_hdl_models_GrayCounter.v | 10 +- tests/asicworld/code_hdl_models_arbiter.v | 60 +- tests/asicworld/code_hdl_models_arbiter_tb.v | 30 +- tests/asicworld/code_hdl_models_cam.v | 16 +- tests/asicworld/code_hdl_models_clk_div.v | 12 +- tests/asicworld/code_hdl_models_clk_div_45.v | 4 +- .../code_hdl_models_decoder_using_assign.v | 10 +- .../code_hdl_models_dff_async_reset.v | 4 +- .../code_hdl_models_dff_sync_reset.v | 2 +- .../code_hdl_models_encoder_using_case.v | 34 +- .../code_hdl_models_encoder_using_if.v | 66 +- .../asicworld/code_hdl_models_gray_counter.v | 26 +- tests/asicworld/code_hdl_models_lfsr.v | 2 +- tests/asicworld/code_hdl_models_lfsr_updown.v | 8 +- .../code_hdl_models_mux_using_case.v | 4 +- tests/asicworld/code_hdl_models_one_hot_cnt.v | 4 +- .../asicworld/code_hdl_models_parallel_crc.v | 4 +- .../code_hdl_models_parity_using_assign.v | 14 +- .../code_hdl_models_parity_using_bitwise.v | 6 +- .../code_hdl_models_parity_using_function.v | 22 +- ...code_hdl_models_pri_encoder_using_assign.v | 42 +- .../code_hdl_models_rom_using_case.v | 4 +- tests/asicworld/code_hdl_models_serial_crc.v | 6 +- .../code_hdl_models_tff_async_reset.v | 2 +- .../code_hdl_models_tff_sync_reset.v | 2 +- tests/asicworld/code_hdl_models_uart.v | 14 +- tests/asicworld/code_hdl_models_up_counter.v | 2 +- .../code_hdl_models_up_counter_load.v | 6 +- .../code_hdl_models_up_down_counter.v | 4 +- tests/asicworld/code_specman_switch_fabric.v | 22 +- tests/asicworld/code_tidbits_asyn_reset.v | 8 +- tests/asicworld/code_tidbits_blocking.v | 6 +- .../asicworld/code_tidbits_fsm_using_always.v | 2 +- .../code_tidbits_fsm_using_function.v | 4 +- .../code_tidbits_fsm_using_single_always.v | 2 +- tests/asicworld/code_tidbits_nonblocking.v | 6 +- .../code_tidbits_reg_combo_example.v | 2 +- .../asicworld/code_tidbits_reg_seq_example.v | 2 +- tests/asicworld/code_tidbits_syn_reset.v | 14 +- .../code_verilog_tutorial_always_example.v | 2 +- .../asicworld/code_verilog_tutorial_bus_con.v | 4 +- .../asicworld/code_verilog_tutorial_comment.v | 4 +- .../asicworld/code_verilog_tutorial_counter.v | 4 +- tests/asicworld/code_verilog_tutorial_d_ff.v | 2 +- .../asicworld/code_verilog_tutorial_decoder.v | 16 +- .../code_verilog_tutorial_decoder_always.v | 4 +- .../code_verilog_tutorial_escape_id.v | 2 +- .../code_verilog_tutorial_explicit.v | 2 +- .../code_verilog_tutorial_first_counter.v | 2 +- .../code_verilog_tutorial_first_counter_tb.v | 8 +- .../code_verilog_tutorial_flip_flop.v | 4 +- .../code_verilog_tutorial_fsm_full.v | 8 +- .../code_verilog_tutorial_fsm_full_tb.v | 4 +- .../code_verilog_tutorial_multiply.v | 4 +- .../asicworld/code_verilog_tutorial_mux_21.v | 4 +- .../code_verilog_tutorial_n_out_primitive.v | 6 +- .../code_verilog_tutorial_parallel_if.v | 6 +- .../asicworld/code_verilog_tutorial_parity.v | 4 +- .../code_verilog_tutorial_simple_if.v | 2 +- .../asicworld/code_verilog_tutorial_tri_buf.v | 4 +- .../code_verilog_tutorial_which_clock.v | 2 +- tests/bugpoint/procs.il | 8 +- tests/cxxrtl/test_value_fuzz.cc | 12 +- tests/functional/README.md | 4 +- tests/functional/rkt_vcd.py | 8 +- tests/functional/smt_vcd.py | 14 +- tests/hana/hana_vlib.v | 204 +- tests/hana/test_intermout.v | 50 +- tests/hana/test_parse2synthtrans.v | 2 +- tests/hana/test_simulation_always.v | 22 +- tests/hana/test_simulation_decoder.v | 12 +- tests/hana/test_simulation_mux.v | 8 +- tests/hana/test_simulation_seq.v | 4 +- tests/hana/test_simulation_sop.v | 4 +- tests/hana/test_simulation_techmap.v | 2 +- tests/hana/test_simulation_vlib.v | 4 +- tests/liberty/busdef.lib | 14 +- tests/liberty/dff.lib | 4 +- tests/liberty/issue3498_bad.lib | 8 +- tests/liberty/normal.lib | 72 +- tests/liberty/processdefs.lib | 6 +- tests/liberty/semicolextra.lib | 2 +- tests/liberty/semicolmissing.lib | 20 +- tests/liberty/small.v | 2 +- tests/memlib/memlib_9b1B.txt | 2 +- tests/memlib/memlib_9b1B.v | 2 +- tests/memlib/memlib_block_sp.v | 4 +- tests/memlib/memlib_block_sp_full.v | 4 +- tests/memories/issue00335.v | 10 +- tests/opt/opt_balance_tree.ys | 34 +- tests/pass-fuzzing.md | 4 +- tests/sat/grom.ys | 2 +- tests/sat/grom_cpu.v | 6 +- tests/sdc/alu_sub.sdc | 2 +- tests/sim/generate_mk.py | 2 +- tests/sim/tb/tb_adff.v | 2 +- tests/sim/tb/tb_adffe.v | 2 +- tests/sim/tb/tb_adlatch.v | 2 +- tests/sim/tb/tb_aldff.v | 2 +- tests/sim/tb/tb_aldffe.v | 2 +- tests/sim/tb/tb_dff.v | 2 +- tests/sim/tb/tb_dffe.v | 2 +- tests/sim/tb/tb_dffsr.v | 2 +- tests/sim/tb/tb_dlatch.v | 2 +- tests/sim/tb/tb_dlatchsr.v | 2 +- tests/sim/tb/tb_sdff.v | 2 +- tests/sim/tb/tb_sdffce.v | 2 +- tests/sim/tb/tb_sdffe.v | 2 +- tests/svtypes/struct_simple.sv | 2 +- tests/techmap/dfflibmap_dffn_dffe.lib | 4 +- tests/various/bug1531.ys | 2 +- tests/various/bug1745.ys | 2 +- tests/various/bug4865.ys | 2 +- tests/various/check_4.ys | 2 +- tests/various/dynamic_part_select.ys | 4 +- tests/various/dynamic_part_select/latch_002.v | 2 +- .../dynamic_part_select/multiple_blocking.v | 2 +- .../various/dynamic_part_select/nonblocking.v | 4 +- .../various/dynamic_part_select/reset_test.v | 2 +- tests/various/dynamic_part_select/reversed.v | 2 +- tests/various/equiv_opt_undef.ys | 2 +- tests/various/fsm-arst.ys | 4 +- tests/various/muxpack.v | 4 +- tests/various/shregmap.v | 2 +- tests/various/stat.ys | 2 +- tests/various/stat_area_by_width.lib | 4 +- tests/various/stat_hierarchy.ys | 2 +- tests/verific/blackbox.ys | 2 +- tests/verific/blackbox_ql.ys | 4 +- tests/verific/bounds.vhd | 2 +- tests/verific/case.sv | 8 +- tests/verific/case.ys | 4 +- tests/verific/ext_ramnet_err.sv | 2 +- tests/verific/range_case.ys | 4 +- tests/verific/rom_case.ys | 4 +- tests/verilog/param_default.ys | 2 +- tests/verilog/string-literals.ys | 2 +- 317 files changed, 3136 insertions(+), 3136 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 543209a83..2fd576a90 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -11,7 +11,7 @@ Yosys 0.65 .. Yosys 0.66 - C++ compiler with C++20 support is required. - Please be aware that next release will also migrate to CMake build system. - + * New commands and options - Added "lattice_dsp_nexus" pass for Lattice Nexus DSP inference. @@ -78,7 +78,7 @@ Yosys 0.61 .. Yosys 0.62 cascaded cells into tree of cells to improve timing. - Added "-gatesi" option to "write_blif" pass to init gates under gates_mode in BLIF format. - - Added "-on" and "-off" options to "debug" pass for + - Added "-on" and "-off" options to "debug" pass for persistent debug logging. - Added "linux_perf" pass to control performance recording. @@ -92,7 +92,7 @@ Yosys 0.60 .. Yosys 0.61 * New commands and options - Added "design_equal" pass to support fuzz-test comparison. - Added "lut2bmux" pass to convert $lut to $bmux. - - Added "-legalize" option to "read_rtlil" pass to prevent + - Added "-legalize" option to "read_rtlil" pass to prevent semantic errors. Yosys 0.59 .. Yosys 0.60 @@ -196,7 +196,7 @@ Yosys 0.53 .. Yosys 0.54 - Enable single-bit vector wires in RTLIL. * Xilinx support - - Single-port URAM mapping to support memories 2048 x 144b + - Single-port URAM mapping to support memories 2048 x 144b Yosys 0.52 .. Yosys 0.53 -------------------------- @@ -222,7 +222,7 @@ Yosys 0.51 .. Yosys 0.52 -------------------------- * New commands and options - Added "-pattern-limit" option to "share" pass to limit analysis effort. - - Added "libcache" pass to control caching of technology library + - Added "libcache" pass to control caching of technology library data parsed from liberty files. - Added "read_verilog_file_list" to parse verilog file list. @@ -288,7 +288,7 @@ Yosys 0.47 .. Yosys 0.48 * Gowin support - Added "-family" option to "synth_gowin" pass. - - Cell definitions split by family. + - Cell definitions split by family. * Verific support - Improved blackbox support. @@ -315,7 +315,7 @@ Yosys 0.45 .. Yosys 0.46 - Added new "functional backend" infrastructure with three example backends (C++, SMTLIB and Rosette). - Added new coarse-grain buffer cell type "$buf" to RTLIL. - - Added "-y" command line option to execute a Python script with + - Added "-y" command line option to execute a Python script with libyosys available as a built-in module. - Added support for casting to type in Verilog frontend. @@ -323,7 +323,7 @@ Yosys 0.45 .. Yosys 0.46 - Added "clockgate" pass for automatic clock gating cell insertion. - Added "bufnorm" experimental pass to convert design into buffered-normalized form. - - Added experimental "aiger2" and "xaiger2" backends, and an + - Added experimental "aiger2" and "xaiger2" backends, and an experimental "abc_new" command - Added "-force-detailed-loop-check" option to "check" pass. - Added "-unit_delay" option to "read_liberty" pass. @@ -348,10 +348,10 @@ Yosys 0.43 .. Yosys 0.44 - Build support for Haiku OS. * New commands and options - - Added "keep_hierarchy" pass to add attribute with + - Added "keep_hierarchy" pass to add attribute with same name to modules based on cost. - Added options "-noopt","-bloat" and "-check_cost" to - "test_cell" pass. + "test_cell" pass. * New back-ends - Added initial PolarFire support. ( synth_microchip ) @@ -365,22 +365,22 @@ Yosys 0.42 .. Yosys 0.43 * Verific support - Support building Yosys with various Verific library - configurations. Can be built now without YosysHQ + configurations. Can be built now without YosysHQ specific patch and extension library. Yosys 0.41 .. Yosys 0.42 -------------------------- * New commands and options - Added "box_derive" pass to derive box modules. - - Added option "assert-mod-count" to "select" pass. - - Added option "-header","-push" and "-pop" to "log" pass. + - Added option "assert-mod-count" to "select" pass. + - Added option "-header","-push" and "-pop" to "log" pass. * Intel support - Dropped Quartus support in "synth_intel_alm" pass. Yosys 0.40 .. Yosys 0.41 -------------------------- * New commands and options - - Added "cellmatch" pass for picking out standard cells automatically. + - Added "cellmatch" pass for picking out standard cells automatically. * Various - Extended the experimental incremental JSON API to allow arbitrary @@ -394,7 +394,7 @@ Yosys 0.40 .. Yosys 0.41 Yosys 0.39 .. Yosys 0.40 -------------------------- * New commands and options - - Added option "-vhdl2019" to "read" and "verific" pass. + - Added option "-vhdl2019" to "read" and "verific" pass. * Various - Major documentation overhaul. @@ -408,7 +408,7 @@ Yosys 0.39 .. Yosys 0.40 Yosys 0.38 .. Yosys 0.39 -------------------------- * New commands and options - - Added option "-extra-map" to "synth" pass. + - Added option "-extra-map" to "synth" pass. - Added option "-dont_use" to "dfflibmap" pass. - Added option "-href" to "show" command. - Added option "-noscopeinfo" to "flatten" pass. @@ -422,7 +422,7 @@ Yosys 0.38 .. Yosys 0.39 the hierarchy during flattening. - Added sequential area output to "stat -liberty". - Added ability to record/replay diagnostics in cxxrtl backend. - + * Verific support - Added attributes to module instantiation. @@ -469,7 +469,7 @@ Yosys 0.35 .. Yosys 0.36 * QuickLogic support - Added "K6N10f" support. - - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to + - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to "synth_quicklogic" pass. - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K. - Added "ql_bram_types" pass to change TDP36K depending on configuration. @@ -564,7 +564,7 @@ Yosys 0.29 .. Yosys 0.30 - Added remaining primitives blackboxes. * Various - - "show -colorattr" will now color the cells, wires, and + - "show -colorattr" will now color the cells, wires, and connection arrows. - "show -viewer none" will not execute viewer. @@ -739,7 +739,7 @@ Yosys 0.19 .. Yosys 0.20 operators were not affected. * Verific support - - Proper import of port ranges into Yosys, may result in reversed + - Proper import of port ranges into Yosys, may result in reversed bit-order of top-level ports for some synthesis flows. Yosys 0.18 .. Yosys 0.19 @@ -833,7 +833,7 @@ Yosys 0.14 .. Yosys 0.15 * SystemVerilog - Added support for accessing whole sub-structures in expressions - + * New commands and options - Added glift command, used to create gate-level information flow tracking (GLIFT) models by the "constructive mapping" approach @@ -848,7 +848,7 @@ Yosys 0.13 .. Yosys 0.14 - Added $bmux and $demux cells and related optimization patterns. * New commands and options - - Added "bmuxmap" and "dmuxmap" passes + - Added "bmuxmap" and "dmuxmap" passes - Added "-fst" option to "sim" pass for writing FST files - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate", "-sim-gold" options to "sim" pass for co-simulation diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cc1085f96..522929c50 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -95,7 +95,7 @@ struct XAigerWriter } bit2aig_stack.push_back(bit); - + // NB: Cannot use iterator returned from aig_map.insert() // since this function is called recursively diff --git a/backends/functional/smtlib.cc b/backends/functional/smtlib.cc index 0451af4c7..128dbda6c 100644 --- a/backends/functional/smtlib.cc +++ b/backends/functional/smtlib.cc @@ -187,7 +187,7 @@ struct SmtModule { Functional::IR ir; SmtScope scope; std::string name; - + SmtStruct input_struct; SmtStruct output_struct; SmtStruct state_struct; @@ -256,7 +256,7 @@ struct SmtModule { } void write(std::ostream &out) - { + { SExprWriter w(out); input_struct.write_definition(w); @@ -266,7 +266,7 @@ struct SmtModule { w << list("declare-datatypes", list(list("Pair", 2)), list(list("par", list("X", "Y"), list(list("pair", list("first", "X"), list("second", "Y")))))); - + write_eval(w); write_initial(w); } diff --git a/backends/functional/smtlib_rosette.cc b/backends/functional/smtlib_rosette.cc index b37f948b6..1adceddd5 100644 --- a/backends/functional/smtlib_rosette.cc +++ b/backends/functional/smtlib_rosette.cc @@ -304,7 +304,7 @@ struct SmtrModule { } void write(std::ostream &out) - { + { SExprWriter w(out); input_struct.write_definition(w); diff --git a/backends/functional/test_generic.cc b/backends/functional/test_generic.cc index 343fcfc0f..d6a1ce4af 100644 --- a/backends/functional/test_generic.cc +++ b/backends/functional/test_generic.cc @@ -46,7 +46,7 @@ struct MemContentsTest { error: printf("FAIL\n"); int digits = (data_width + 3) / 4; - + for(auto addr = 0; addr < (1< 1: return len(self.bits[1]) else: return sum([sig.width for sig in self.signals if not sig.init_only]) - + def first_step(self): values = WitnessValues() # may have issues when non_init_bits is 0 diff --git a/cmake/YosysAbc.cmake b/cmake/YosysAbc.cmake index 6e3736712..0632a9b17 100644 --- a/cmake/YosysAbc.cmake +++ b/cmake/YosysAbc.cmake @@ -57,7 +57,7 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) target_include_directories(${arg_LIBNAME} PRIVATE abc/src) target_compile_definitions(${arg_LIBNAME} PUBLIC WIN32_NO_DLL - $<$>:ABC_NAMESPACE=abc> + $<$>:ABC_NAMESPACE=abc> ABC_USE_STDINT_H=1 ABC_USE_CUDD=1 ABC_NO_DYNAMIC_LINKING @@ -68,11 +68,11 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) $<$:HAVE_STRUCT_TIMESPEC> ABC_NO_RLIMIT ) - target_compile_options(${arg_LIBNAME} PRIVATE + target_compile_options(${arg_LIBNAME} PRIVATE $<$:/wd4576> $<$:/Zc:strictStrings-> ) - + target_safe_compile_options(${arg_LIBNAME} PRIVATE -fpermissive -fno-exceptions diff --git a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst index ff404cb53..181bdaa0a 100644 --- a/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst +++ b/docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst @@ -279,9 +279,9 @@ This document was originally published in April 2015: in line 13 provides a mini synthesis-script to be used to process this cell. .. code-block:: c - :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled - using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a - -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` + :caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled + using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a + -mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx`` set and booted with a custom setup routine written in ARM assembler. :name: sieve diff --git a/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst b/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst index 1874b0148..58a0ac39b 100644 --- a/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst +++ b/docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst @@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format. Download ======== -This document was originally published in November 2013: +This document was originally published in November 2013: :download:`Converting Verilog to BTOR PDF` .. diff --git a/docs/source/appendix/primer.rst b/docs/source/appendix/primer.rst index f54f99e52..beb1e6a8a 100644 --- a/docs/source/appendix/primer.rst +++ b/docs/source/appendix/primer.rst @@ -601,7 +601,7 @@ Let's consider the following BNF (in Bison syntax): :class: width-helper invert-helper :name: fig:Basics_parsetree - Example parse tree for the Verilog expression + Example parse tree for the Verilog expression :verilog:`assign foo = bar + 42;` The parser converts the token list to the parse tree in :numref:`Fig. %s @@ -630,7 +630,7 @@ three-address-code intermediate representation. :cite:p:`Dragonbook` :class: width-helper invert-helper :name: fig:Basics_ast - Example abstract syntax tree for the Verilog expression + Example abstract syntax tree for the Verilog expression :verilog:`assign foo = bar + 42;` diff --git a/docs/source/appendix/rtlil_text.rst b/docs/source/appendix/rtlil_text.rst index 352b1af2e..f555d565e 100644 --- a/docs/source/appendix/rtlil_text.rst +++ b/docs/source/appendix/rtlil_text.rst @@ -136,11 +136,11 @@ wires, memories, cells, processes, and connections. ::= * ::= module - ::= ( + ::= ( | - | - | - | + | + | + | | )* ::= parameter ? ::= | | @@ -170,9 +170,9 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications. .. code:: BNF - ::= + ::= | - | [ (:)? ] + | [ (:)? ] | { * } When a ```` is specified, the wire must have been previously declared. @@ -202,12 +202,12 @@ See :ref:`sec:rtlil_cell_wire` for an overview of wires. ::= * ::= wire * ::= - ::= width - | offset - | input - | output - | inout - | upto + ::= width + | offset + | input + | output + | inout + | upto | signed Memories @@ -223,8 +223,8 @@ See :ref:`sec:rtlil_memory` for an overview of memory cells, and ::= * ::= memory * - ::= width - | size + ::= width + | size | offset Cells @@ -299,9 +299,9 @@ be: .. code:: BNF ::= * - ::= sync + ::= sync | sync global - | sync init + | sync init | sync always ::= low | high | posedge | negedge | edge ::= update diff --git a/docs/source/cell/word_logic.rst b/docs/source/cell/word_logic.rst index 9f04e9b99..fadbec140 100644 --- a/docs/source/cell/word_logic.rst +++ b/docs/source/cell/word_logic.rst @@ -29,7 +29,7 @@ There are 2 products to be summed, so ``\DEPTH`` shall be 2. ~A[1]---+|| A[1]--+||| ~A[0]-+|||| - A[0]+||||| + A[0]+||||| |||||| product formula 010000 ~\A[0] 001001 \A[1]~\A[2] diff --git a/docs/source/cmd/index_internal.rst b/docs/source/cmd/index_internal.rst index ab9c13aba..afd194c73 100644 --- a/docs/source/cmd/index_internal.rst +++ b/docs/source/cmd/index_internal.rst @@ -88,7 +88,7 @@ Dumping command help to json by ``Pass::experimental()``) * also title (``short_help`` argument in ``Pass::Pass``), group, and class name - + + dictionary of group name to list of commands in that group - used by sphinx autodoc to generate help content @@ -106,7 +106,7 @@ Dumping command help to json code block is formatted as ``yoscrypt`` (e.g. `synth_ice40`). The caveat here is that if the ``script()`` calls ``run()`` on any commands *prior* to the first ``check_label`` then the auto detection will break and revert to - unformatted code (e.g. `synth_fabulous`). + unformatted code (e.g. `synth_fabulous`). Command line rendering ~~~~~~~~~~~~~~~~~~~~~~ @@ -114,7 +114,7 @@ Command line rendering - if ``Pass::formatted_help()`` returns true, will call ``PrettyHelp::log_help()`` - + traverse over the children of the root node and render as plain text + + traverse over the children of the root node and render as plain text + effectively the reverse of converting unformatted ``Pass::help()`` text + lines are broken at 80 characters while maintaining indentation (controlled by ``MAX_LINE_LEN`` in :file:`kernel/log_help.cc`) diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index eab8349da..623ca9968 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -2,7 +2,7 @@ include ../../../common.mk DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse -MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates +MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells DOTS := $(addsuffix .dot,$(DOT_NAMES)) diff --git a/docs/source/code_examples/fifo/fifo.v b/docs/source/code_examples/fifo/fifo.v index 86f292406..db99f7211 100644 --- a/docs/source/code_examples/fifo/fifo.v +++ b/docs/source/code_examples/fifo/fifo.v @@ -1,5 +1,5 @@ // address generator/counter -module addr_gen +module addr_gen #( parameter MAX_DATA=256, localparam AWIDTH = $clog2(MAX_DATA) ) ( input en, clk, rst, @@ -21,7 +21,7 @@ module addr_gen endmodule //addr_gen // Define our top level fifo entity -module fifo +module fifo #( parameter MAX_DATA=256, localparam AWIDTH = $clog2(MAX_DATA) ) ( input wen, ren, clk, rst, diff --git a/docs/source/code_examples/fifo/fifo.ys b/docs/source/code_examples/fifo/fifo.ys index e6b9bf69d..d8af9a7fd 100644 --- a/docs/source/code_examples/fifo/fifo.ys +++ b/docs/source/code_examples/fifo/fifo.ys @@ -2,7 +2,7 @@ # throw in some extra text to match what we expect if we were opening an # interactive terminal log $ yosys fifo.v -log +log log -- Parsing `fifo.v' using frontend ` -vlog2k' -- read_verilog -defer fifo.v diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index e9b36bb35..fbdd763fc 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -54,7 +54,7 @@ map_gates: ice40_wrapcarry techmap opt -fast - abc -dff -D 1 + abc -dff -D 1 ice40_opt map_ffs: @@ -88,4 +88,4 @@ check: stat check -noinit blackbox =A:whitebox - + diff --git a/docs/source/code_examples/opt/opt_expr.ys b/docs/source/code_examples/opt/opt_expr.ys index e87da339e..f884b2227 100644 --- a/docs/source/code_examples/opt/opt_expr.ys +++ b/docs/source/code_examples/opt/opt_expr.ys @@ -3,7 +3,7 @@ read_verilog <`. .. todo:: consider a brief glossary for terms like adff .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/proc` - :doc:`/using_yosys/synthesis/opt` @@ -321,7 +321,7 @@ and merged with the ``raddr`` wire feeding into the `$memrd` cell. This wire merging happened during the call to `clean` which we can see in the :ref:`flat_clean`. -.. note:: +.. note:: `flatten` and `clean` would normally be combined into a single :yoterm:`yosys> flatten;;` output, but they appear separately here as @@ -394,7 +394,7 @@ highlighted below: ``rdata`` output after `opt_dff` .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/fsm` - :doc:`/using_yosys/synthesis/opt` @@ -461,7 +461,7 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and ``SRST=1'0``) inputs. .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/opt` - :doc:`/using_yosys/synthesis/techmap_synth` - :doc:`/using_yosys/synthesis/memory` @@ -659,7 +659,7 @@ into flip flops (the ``logic fallback``) with `memory_map`. complex. .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/techmap_synth` - :doc:`/using_yosys/synthesis/memory` @@ -757,7 +757,7 @@ cells. ``rdata`` output after :ref:`map_cells` .. seealso:: Advanced usage docs for - + - :doc:`/using_yosys/synthesis/techmap_synth` - :doc:`/using_yosys/synthesis/abc` diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst index cbbe5aa31..ff6f3ac49 100644 --- a/docs/source/getting_started/installation.rst +++ b/docs/source/getting_started/installation.rst @@ -152,7 +152,7 @@ Installing all prerequisites: recommended to use Windows Subsystem for Linux (WSL) and follow the instructions for Ubuntu. -.. +.. tab:: MSYS2 (MINGW64) .. code:: console diff --git a/docs/source/getting_started/scripting_intro.rst b/docs/source/getting_started/scripting_intro.rst index c44ce82a8..d6e482431 100644 --- a/docs/source/getting_started/scripting_intro.rst +++ b/docs/source/getting_started/scripting_intro.rst @@ -149,11 +149,11 @@ represent, see :ref:`interactive_show` and the Calling :yoscrypt:`show addr_gen` after `hierarchy` -.. note:: +.. note:: The `show` command requires a working installation of `GraphViz`_ and `xdot`_ for displaying the actual circuit diagrams. - + .. _GraphViz: http://www.graphviz.org/ .. _xdot: https://github.com/jrfonseca/xdot.py diff --git a/docs/source/introduction.rst b/docs/source/introduction.rst index 376c8043b..48a4fb9fd 100644 --- a/docs/source/introduction.rst +++ b/docs/source/introduction.rst @@ -125,7 +125,7 @@ The first version of the Yosys documentation was published as a bachelor thesis at the Vienna University of Technology :cite:p:`BACC`. :Abstract: - Most of today's digital design is done in HDL code (mostly Verilog or + Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or @@ -164,14 +164,14 @@ for specialised tasks. Benefits of open source HDL synthesis ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Cost (also applies to ``free as in free beer`` solutions): - +- Cost (also applies to ``free as in free beer`` solutions): + Today the cost for a mask set in 180nm technology is far less than the cost for the design tools needed to design the mask layouts. Open Source ASIC flows are an important enabler for ASIC-level Open Source Hardware. -- Availability and Reproducibility: - +- Availability and Reproducibility: + If you are a researcher who is publishing, you want to use tools that everyone else can also use. Even if most universities have access to all major commercial tools, you usually do not have easy access to the version that was @@ -179,14 +179,14 @@ Benefits of open source HDL synthesis can even release the source code of the tool you have used alongside your data. -- Framework: - +- Framework: + Yosys is not only a tool. It is a framework that can be used as basis for other developments, so researchers and hackers alike do not need to re-invent the basic functionality. Extensibility was one of Yosys' design goals. -- All-in-one: - +- All-in-one: + Because of the framework characteristics of Yosys, an increasing number of features become available in one tool. Yosys not only can be used for circuit synthesis but also for formal equivalence checking, SAT solving, and for @@ -194,8 +194,8 @@ Benefits of open source HDL synthesis proprietary software one needs to learn a new tool for each of these applications. -- Educational Tool: - +- Educational Tool: + Proprietary synthesis tools are at times very secretive about their inner workings. They often are ``black boxes``. Yosys is very open about its internals and it is easy to observe the different steps of synthesis. diff --git a/docs/source/literature.bib b/docs/source/literature.bib index 143e3aa36..6d35d2922 100644 --- a/docs/source/literature.bib +++ b/docs/source/literature.bib @@ -66,24 +66,24 @@ year = {1996} } -@ARTICLE{Verilog2005, +@ARTICLE{Verilog2005, journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)}, - title={IEEE Standard for Verilog Hardware Description Language}, + title={IEEE Standard for Verilog Hardware Description Language}, author={IEEE Standards Association and others}, - year={2006}, + year={2006}, doi={10.1109/IEEESTD.2006.99495} } -@ARTICLE{VerilogSynth, +@ARTICLE{VerilogSynth, journal={IEEE Std 1364.1-2002}, - title={IEEE Standard for Verilog Register Transfer Level Synthesis}, + title={IEEE Standard for Verilog Register Transfer Level Synthesis}, author={IEEE Standards Association and others}, - year={2002}, + year={2002}, doi={10.1109/IEEESTD.2002.94220} } @ARTICLE{VHDL, - journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, + journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)}, title={IEEE Standard VHDL Language Reference Manual}, author={IEEE Standards Association and others}, year={2009}, @@ -92,20 +92,20 @@ } @ARTICLE{VHDLSynth, - journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, + journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)}, title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis}, author={IEEE Standards Association and others}, year={2004}, doi={10.1109/IEEESTD.2004.94802} } -@ARTICLE{IP-XACT, - journal={IEEE Std 1685-2009}, - title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, +@ARTICLE{IP-XACT, + journal={IEEE Std 1685-2009}, + title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows}, author={IEEE Standards Association and others}, - year={2010}, - pages={C1-360}, - keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, + year={2010}, + pages={C1-360}, + keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema}, doi={10.1109/IEEESTD.2010.5417309} } @@ -116,7 +116,7 @@ isbn = {0-201-10088-6}, publisher = {Addison-Wesley Longman Publishing Co., Inc.}, address = {Boston, MA, USA} -} +} @INPROCEEDINGS{Cummings00, author = {Clifford E. Cummings and Sunburst Design Inc}, @@ -132,26 +132,26 @@ year={August 1967} } -@INPROCEEDINGS{fsmextract, - author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, - booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, - title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, - year={2010}, - pages={2610-2613}, - keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, +@INPROCEEDINGS{fsmextract, + author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren}, + booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on}, + title={A highly efficient method for extracting FSMs from flattened gate-level netlist}, + year={2010}, + pages={2610-2613}, + keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing}, doi={10.1109/ISCAS.2010.5537093}, } -@ARTICLE{MultiLevelLogicSynth, - author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, - journal={Proceedings of the IEEE}, - title={Multilevel logic synthesis}, - year={1990}, - volume={78}, - number={2}, - pages={264-300}, - keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, - doi={10.1109/5.52213}, +@ARTICLE{MultiLevelLogicSynth, + author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.}, + journal={Proceedings of the IEEE}, + title={Multilevel logic synthesis}, + year={1990}, + volume={78}, + number={2}, + pages={264-300}, + keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon}, + doi={10.1109/5.52213}, ISSN={0018-9219}, } @@ -171,7 +171,7 @@ acmid = {321925}, publisher = {ACM}, address = {New York, NY, USA}, -} +} @article{een2003temporal, title={Temporal induction by incremental SAT solving}, diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index 0d1a17503..ae349bb21 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -56,7 +56,7 @@ is shown. .. figure:: /_images/code_examples/show/example_first.* :class: width-helper invert-helper - + Output of the first `show` command in :numref:`example_ys` The first output shows the design directly after being read by the Verilog @@ -88,7 +88,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram: .. figure:: /_images/code_examples/show/example_second.* :class: width-helper invert-helper - + Output of the second `show` command in :numref:`example_ys` The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if @@ -106,14 +106,14 @@ operations, it is therefore recommended to always call `clean` before calling `show`. In this script we directly call `opt` as the next step, which finally leads us -to the third diagram: +to the third diagram: .. figure:: /_images/code_examples/show/example_third.* :class: width-helper invert-helper :name: example_out - + Output of the third `show` command in :ref:`example_ys` - + Here we see that the `opt` command not only has removed the artifacts left behind by `proc`, but also determined correctly that it can remove the first `$mux` cell without changing the behavior of the circuit. @@ -167,7 +167,7 @@ mapped to a cell library: :class: width-helper invert-helper :name: first_pitfall - A half-adder built from simple CMOS gates, demonstrating common pitfalls when + A half-adder built from simple CMOS gates, demonstrating common pitfalls when using `show` .. literalinclude:: /code_examples/show/cmos.ys @@ -176,7 +176,7 @@ mapped to a cell library: :end-at: cmos_00 :name: pitfall_code :caption: Generating :numref:`first_pitfall` - + First, Yosys did not have access to the cell library when this diagram was generated, resulting in all cell ports defaulting to being inputs. This is why all ports are drawn on the left side the cells are awkwardly arranged in a large @@ -248,7 +248,7 @@ command already fails to verify, it is better to troubleshoot the coarse-grain version of the circuit before `techmap` than the gate-level circuit after `techmap`. -.. Note:: +.. Note:: It is generally recommended to verify the internal state of a design by writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and @@ -327,7 +327,7 @@ tools). - :cmd:title:`dump`. - :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize a design dynamically. - + The code used is included in the Yosys code base under |code_examples/scrambler|_. @@ -438,7 +438,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`: .. figure:: /_images/code_examples/selections/memdemo_00.* :class: width-helper invert-helper - + ``memdemo`` Because this produces a rather large circuit, it can be useful to split it into @@ -459,18 +459,18 @@ below. .. figure:: /_images/code_examples/selections/submod_02.* :class: width-helper invert-helper - + ``outstage`` .. figure:: /_images/code_examples/selections/submod_03.* :class: width-helper invert-helper :name: selstage - + ``selstage`` .. figure:: /_images/code_examples/selections/submod_01.* :class: width-helper invert-helper - + ``scramble`` Evaluation of combinatorial circuits @@ -541,9 +541,9 @@ to solve this kind of problems. .. _MiniSAT: http://minisat.se/ -.. note:: - - While it is possible to perform model checking directly in Yosys, it +.. note:: + + While it is possible to perform model checking directly in Yosys, it is highly recommended to use SBY or EQY for formal hardware verification. The `sat` command works very similar to the `eval` command. The main difference diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst index 9aa028418..178df5682 100644 --- a/docs/source/using_yosys/more_scripting/load_design.rst +++ b/docs/source/using_yosys/more_scripting/load_design.rst @@ -81,7 +81,7 @@ Yosys frontends 'Frontend' here means that the command is implemented as a sub-class of ``RTLIL::Frontend``, as opposed to the usual ``RTLIL::Pass``. -.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under +.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under :doc:`/yosys_internals/extending_yosys/index` The `read_verilog` command diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index 1f3912956..bfabb7a01 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar. If no `select` command has been made, then the "current selection" will be the whole design. -.. note:: Many of the examples on this page make use of the `show` - command to visually demonstrate the effect of selections. For a more +.. note:: Many of the examples on this page make use of the `show` + command to visually demonstrate the effect of selections. For a more detailed look at this command, refer to :ref:`interactive_show`. How to make a selection @@ -106,7 +106,7 @@ glance. When it is called with multiple arguments, each argument is evaluated and pushed separately on a stack. After all arguments have been processed it simply creates the union of all elements on the stack. So :yoscrypt:`select t:$add a:foo` will select all `$add` cells and all objects with the ``foo`` -attribute set: +attribute set: .. literalinclude:: /code_examples/selections/foobaraddsub.v :caption: Test module for operations on selections @@ -130,7 +130,7 @@ select all `$add` cells that have the ``foo`` attribute set: .. code-block:: :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub` - + yosys> select t:$add a:foo %i -list foobaraddsub/$add$foobaraddsub.v:4$1 @@ -282,7 +282,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the .. figure:: /_images/code_examples/selections/memdemo_00.* :class: width-helper invert-helper :name: memdemo_00 - + Complete circuit diagram for the design shown in :numref:`memdemo_src` There's a lot going on there, but maybe we are only interested in the tree of @@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`: .. figure:: /_images/code_examples/selections/memdemo_01.* :class: width-helper invert-helper :name: memdemo_01 - + Output of :yoscrypt:`show y %ci2` From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is @@ -305,7 +305,7 @@ start of the name). Let's go a bit further now and try :yoscrypt:`show y %ci5`: .. figure:: /_images/code_examples/selections/memdemo_02.* :class: width-helper invert-helper :name: memdemo_02 - + Output of :yoscrypt:`show y %ci5` That's starting to get a bit messy, so maybe we want to ignore the mux select @@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`: .. figure:: /_images/code_examples/selections/memdemo_03.* :class: width-helper invert-helper :name: memdemo_03 - + Output of :yoscrypt:`show y %ci5:-$mux[S]` We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D] @@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells: .. figure:: /_images/code_examples/selections/memdemo_05.* :class: width-helper invert-helper :name: memdemo_05 - + Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff`` Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following @@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``: .. figure:: /_images/code_examples/selections/memdemo_04.* :class: width-helper invert-helper :name: memdemo_04 - + Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux` Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst index 50811fd1e..073a05213 100644 --- a/docs/source/using_yosys/synthesis/cell_libs.rst +++ b/docs/source/using_yosys/synthesis/cell_libs.rst @@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document. The :file:`counter.ys` script includes the commands used to generate the images in this document. Code snippets in this document skip these commands; including line numbers to allow the reader to follow along with the source. - + To learn more about these commands, check out :ref:`interactive_show`. .. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro @@ -37,7 +37,7 @@ First, let's quickly look at the design: This is a simple counter with reset and enable. If the reset signal, ``rst``, is high then the counter will reset to 0. Otherwise, if the enable signal, ``en``, is high then the ``count`` register will increment by 1 each rising edge -of the clock, ``clk``. +of the clock, ``clk``. Loading the design ~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst index 8c346412a..c59ac5363 100644 --- a/docs/source/using_yosys/synthesis/extract.rst +++ b/docs/source/using_yosys/synthesis/extract.rst @@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_. .. figure:: /_images/code_examples/macc/macc_simple_test_00a.* :class: width-helper invert-helper - + before `extract` .. literalinclude:: /code_examples/macc/macc_simple_test.ys @@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_. .. figure:: /_images/code_examples/macc/macc_simple_test_00b.* :class: width-helper invert-helper - + after `extract` .. literalinclude:: /code_examples/macc/macc_simple_test.v diff --git a/docs/source/using_yosys/synthesis/fsm.rst b/docs/source/using_yosys/synthesis/fsm.rst index 07a3cc9cc..2da0b1896 100644 --- a/docs/source/using_yosys/synthesis/fsm.rst +++ b/docs/source/using_yosys/synthesis/fsm.rst @@ -92,7 +92,7 @@ transition table. For each state: 3. Set the state signal to the current state 4. Try to evaluate the next state and control output 5. If step 4 was not successful: - + - Recursively goto step 4 with the offending stop-signal set to 0. - Recursively goto step 4 with the offending stop-signal set to 1. diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst index b498bcb1d..44d5698b5 100644 --- a/docs/source/using_yosys/synthesis/memory.rst +++ b/docs/source/using_yosys/synthesis/memory.rst @@ -122,7 +122,7 @@ to four memory primitive classes available for selection: - Can handle arbitrary number and kind of read ports - LUT RAM (aka distributed RAM): uses LUT storage as RAM - + - Supported on most FPGAs (with notable exception of ice40) - Usually has one synchronous write port, one or more asynchronous read ports - Small @@ -141,7 +141,7 @@ to four memory primitive classes available for selection: - Huge RAM: - Only supported on several targets: - + - Some Xilinx UltraScale devices (UltraRAM) - Two ports, both with mutually exclusive synchronous read and write @@ -154,7 +154,7 @@ to four memory primitive classes available for selection: - Does not support initial data - Nexus (large RAM) - + - Two ports, both with mutually exclusive synchronous read and write - Single clock @@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior if (read_enable) begin read_data <= mem[read_addr]; - + if (write_enable && read_addr == write_addr) // this if block read_data <= 'x; @@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior if (write_enable) mem[write_addr] <= write_data; - if (read_enable) + if (read_enable) read_data <= mem[read_addr]; end @@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior if (read_enable) if (write_enable) read_data <= write_data; - else + else read_data <= mem[addr]; end diff --git a/docs/source/using_yosys/synthesis/techmap_synth.rst b/docs/source/using_yosys/synthesis/techmap_synth.rst index 54a715342..c22269fdf 100644 --- a/docs/source/using_yosys/synthesis/techmap_synth.rst +++ b/docs/source/using_yosys/synthesis/techmap_synth.rst @@ -1,4 +1,4 @@ -Technology mapping +Technology mapping ================== .. todo:: less academic, check text is coherent diff --git a/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst b/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst index 22e4b1b7a..64dd36d0e 100644 --- a/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst +++ b/docs/source/yosys_internals/extending_yosys/advanced_bugpoint.rst @@ -240,7 +240,7 @@ the design at each log header. A worked example ~~~~~~~~~~~~~~~~ - + Say you did all the minimization and found that an error in `synth_xilinx` occurs when a call to ``techmap -map +/xilinx/cells_map.v`` with ``MIN_MUX_INPUTS`` defined parses a `$_MUX16_` with all inputs set to ``1'x``. diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst index 949c78586..315ae9c58 100644 --- a/docs/source/yosys_internals/extending_yosys/extensions.rst +++ b/docs/source/yosys_internals/extending_yosys/extensions.rst @@ -68,7 +68,7 @@ with, and lists off the current design's modules. :language: c++ :lines: 1, 4, 6, 7-20 :caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc` - + Note that we are making a global instance of a class derived from ``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`. diff --git a/docs/source/yosys_internals/flow/index.rst b/docs/source/yosys_internals/flow/index.rst index e5afa2540..565cea2bb 100644 --- a/docs/source/yosys_internals/flow/index.rst +++ b/docs/source/yosys_internals/flow/index.rst @@ -10,7 +10,7 @@ These scripts contain three types of commands: - **Backends**, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .). -.. toctree:: +.. toctree:: :maxdepth: 3 overview diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index 8381641b3..73a67f2f2 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -432,12 +432,12 @@ variables: initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are empty. -- | ``subst_lvalue_from`` and ``subst_lvalue_to`` +- | ``subst_lvalue_from`` and ``subst_lvalue_to`` | These two variables contain the mapping from left-hand-side signals (``\ ``) to the current temporary signal for the same thing (initially ``$0\ ``). -- | ``current_case`` +- | ``current_case`` | A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case of the generated ``RTLIL::Process``. @@ -603,13 +603,13 @@ behavioural model in ``RTLIL::Process`` representation. The actual conversion from a behavioural model to an RTL representation is performed by the `proc` pass and the passes it launches: -- | `proc_clean` and `proc_rmdead` +- | `proc_clean` and `proc_rmdead` | These two passes just clean up the ``RTLIL::Process`` structure. The `proc_clean` pass removes empty parts (eg. empty assignments) from the process and `proc_rmdead` detects and removes unreachable branches from the process's decision trees. -- | `proc_arst` +- | `proc_arst` | This pass detects processes that describe d-type flip-flops with asynchronous resets and rewrites the process to better reflect what they are modelling: Before this pass, an asynchronous reset has two @@ -617,7 +617,7 @@ pass and the passes it launches: reset path. After this pass the sync rule for the reset is level-sensitive and the top-level ``RTLIL::SwitchRule`` has been removed. -- | `proc_mux` +- | `proc_mux` | This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to a tree of multiplexers per written signal. After this, the ``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that diff --git a/docs/source/yosys_internals/formats/index.rst b/docs/source/yosys_internals/formats/index.rst index 22d9e964a..a6c29955e 100644 --- a/docs/source/yosys_internals/formats/index.rst +++ b/docs/source/yosys_internals/formats/index.rst @@ -48,7 +48,7 @@ RTLIL and fail to run when unsupported high-level constructs are used. In such cases a pass that transforms the higher-level constructs to lower-level constructs must be called from the synthesis script first. -.. toctree:: +.. toctree:: :maxdepth: 3 rtlil_rep diff --git a/docs/tests/macro_commands.py b/docs/tests/macro_commands.py index acd02e674..cded283b3 100755 --- a/docs/tests/macro_commands.py +++ b/docs/tests/macro_commands.py @@ -94,7 +94,7 @@ for macro in MACRO_SOURCE.glob("*.ys"): if expected_dict[key] and expected_dict[key] != actual_dict[key]: does_match = False - # raise error on mismatch + # raise error on mismatch if not does_match: logging.error(f"Expected {expected!r}, got {actual!r}") raise_error = True diff --git a/docs/util/RtlilLexer.py b/docs/util/RtlilLexer.py index 75aa53ec8..93a401515 100644 --- a/docs/util/RtlilLexer.py +++ b/docs/util/RtlilLexer.py @@ -9,7 +9,7 @@ class RtlilLexer(RegexLexer): filenames = ['*.il'] keyword_re = r'(always|assign|attribute|autoidx|case|cell|connect|edge|end|global|high|init|inout|input|low|memory|module|negedge|offset|output|parameter|posedge|process|real|signed|size|switch|sync|update|upto|width|wire)' - + tokens = { 'common': [ (r'\s+', Whitespace), diff --git a/docs/util/cell_documenter.py b/docs/util/cell_documenter.py index 58e65c2ea..296ae1bfd 100644 --- a/docs/util/cell_documenter.py +++ b/docs/util/cell_documenter.py @@ -34,7 +34,7 @@ class YosysCell: inputs: list[str] outputs: list[str] properties: list[str] - + class YosysCellGroupDocumenter(Documenter): objtype = 'cellgroup' priority = 10 @@ -67,7 +67,7 @@ class YosysCellGroupDocumenter(Documenter): for (name, obj) in cells_obj.get(self.lib_key, {}).items(): self.__cell_lib[name] = obj return self.__cell_lib - + @classmethod def can_document_member( cls, @@ -83,7 +83,7 @@ class YosysCellGroupDocumenter(Documenter): self.content_indent = '' self.fullname = self.modname = self.name return True - + def import_object(self, raiseerror: bool = False) -> bool: # get cell try: @@ -95,16 +95,16 @@ class YosysCellGroupDocumenter(Documenter): self.real_modname = self.modname return True - + def get_sourcename(self) -> str: return self.env.doc2path(self.env.docname) - + def format_name(self) -> str: return self.options.caption or '' def format_signature(self, **kwargs: Any) -> str: return self.modname - + def add_directive_header(self, sig: str) -> None: domain = getattr(self, 'domain', 'cell') directive = getattr(self, 'directivetype', 'group') @@ -118,7 +118,7 @@ class YosysCellGroupDocumenter(Documenter): if self.options.noindex: self.add_line(' :noindex:', sourcename) - + def add_content(self, more_content: Any | None) -> None: # groups have no native content # add additional content (e.g. from document), if present @@ -271,22 +271,22 @@ class YosysCellDocumenter(YosysCellGroupDocumenter): self.fullname = ((self.modname) + (thing or '')) return True - + def import_object(self, raiseerror: bool = False) -> bool: if super().import_object(raiseerror): self.object = YosysCell(self.modname, **self.object[1]) return True return False - + def get_sourcename(self) -> str: return self.object.source.split(":")[0] - + def format_name(self) -> str: return self.object.name def format_signature(self, **kwargs: Any) -> str: return self.groupname + self.fullname + self.attribute - + def add_directive_header(self, sig: str) -> None: domain = getattr(self, 'domain', self.objtype) directive = getattr(self, 'directivetype', 'def') @@ -310,7 +310,7 @@ class YosysCellDocumenter(YosysCellGroupDocumenter): if self.options.noindex: self.add_line(' :noindex:', sourcename) - + def add_content(self, more_content: Any | None) -> None: # set sourcename and add content from attribute documentation sourcename = self.get_sourcename() @@ -360,7 +360,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter): if isinstance(parent, YosysCellDocumenter): return True return False - + def add_directive_header(self, sig: str) -> None: domain = getattr(self, 'domain', 'cell') directive = getattr(self, 'directivetype', 'source') @@ -383,7 +383,7 @@ class YosysCellSourceDocumenter(YosysCellDocumenter): if self.options.noindex: self.add_line(' :noindex:', sourcename) - + def add_content(self, more_content: Any | None) -> None: # set sourcename and add content from attribute documentation sourcename = self.get_sourcename() diff --git a/docs/util/cmd_documenter.py b/docs/util/cmd_documenter.py index 9347d8ffd..2c9384cca 100644 --- a/docs/util/cmd_documenter.py +++ b/docs/util/cmd_documenter.py @@ -78,7 +78,7 @@ class YosysCmd: self.source_func = source_func self.experimental_flag = experimental_flag self.internal_flag = internal_flag - + class YosysCmdGroupDocumenter(Documenter): objtype = 'cmdgroup' priority = 10 @@ -112,7 +112,7 @@ class YosysCmdGroupDocumenter(Documenter): for (name, obj) in cmds_obj.get(self.lib_key, {}).items(): self.__cmd_lib[name] = obj return self.__cmd_lib - + @classmethod def can_document_member( cls, @@ -128,7 +128,7 @@ class YosysCmdGroupDocumenter(Documenter): self.content_indent = '' self.fullname = self.modname = self.name return True - + def import_object(self, raiseerror: bool = False) -> bool: # get cmd try: @@ -140,19 +140,19 @@ class YosysCmdGroupDocumenter(Documenter): self.real_modname = self.modname return True - + def get_sourcename(self) -> str: return self.env.doc2path(self.env.docname) - + def format_name(self) -> str: return self.options.caption or '' def format_signature(self, **kwargs: Any) -> str: return self.modname - + def add_directive_header(self, sig: str) -> None: pass - + def add_content(self, more_content: Any | None) -> None: pass @@ -323,7 +323,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter): return self.object.source_file except AttributeError: return super().get_sourcename() - + def format_name(self) -> str: return self.object.name @@ -347,7 +347,7 @@ class YosysCmdDocumenter(YosysCmdGroupDocumenter): if self.options.noindex: self.add_line(' :noindex:', source_name) - + def add_content(self, more_content: Any | None) -> None: # set sourcename and add content from attribute documentation domain = getattr(self, 'domain', self.objtype) diff --git a/docs/util/custom_directives.py b/docs/util/custom_directives.py index b90584aa7..7072fa1db 100644 --- a/docs/util/custom_directives.py +++ b/docs/util/custom_directives.py @@ -21,7 +21,7 @@ from sphinx.util.nodes import make_refnode from sphinx.util.docfields import Field, GroupedField from sphinx import addnodes -class TocNode(ObjectDescription): +class TocNode(ObjectDescription): def add_target_and_index( self, name: str, @@ -64,7 +64,7 @@ class NodeWithOptions(TocNode): doc_field_types = [ GroupedField('opts', label='Options', names=('option', 'options', 'opt', 'opts')), ] - + def transform_content(self, contentnode: addnodes.desc_content) -> None: """hack `:option -thing: desc` into a proper option list with yoscrypt highlighting""" newchildren = [] @@ -290,7 +290,7 @@ class CellNode(TocNode): self.env.docname, idx, 0)) - + def transform_content(self, contentnode: addnodes.desc_content) -> None: # Add the cell title to the body if 'title' in self.options: @@ -380,7 +380,7 @@ class CellSourceNode(TocNode): # only add target and index entry if this is the first # description of the object with this name in this desc block self.add_target_and_index(name, sig, signode) - + # handle code code = '\n'.join(self.content) literal: Element = nodes.literal_block(code, code) @@ -420,11 +420,11 @@ class CellGroupNode(TocNode): class TagIndex(Index): """A custom directive that creates a tag matrix.""" - + name = 'tag' localname = 'Tag Index' shortname = 'Tag' - + def __init__(self, *args, **kwargs): super(TagIndex, self).__init__(*args, **kwargs) @@ -458,14 +458,14 @@ class TagIndex(Index): objs = {name: (dispname, typ, docname, anchor) for name, dispname, typ, docname, anchor, prio in self.domain.get_objects()} - + tmap = {} tags = self.domain.data[f'obj2{self.name}'] for name, tags in tags.items(): for tag in tags: tmap.setdefault(tag,[]) tmap[tag].append(name) - + for tag in tmap.keys(): lis = content.setdefault(tag, []) objlis = tmap[tag] @@ -480,11 +480,11 @@ class TagIndex(Index): return (ret, True) -class CommandIndex(Index): +class CommandIndex(Index): name = 'cmd' localname = 'Command Reference' shortname = 'Command' - + def __init__(self, *args, **kwargs): super(CommandIndex, self).__init__(*args, **kwargs) @@ -525,7 +525,7 @@ class CommandIndex(Index): lis.append(( dispname, 0, docname, anchor, - '', '', title + '', '', title )) ret = [(k, v) for k, v in sorted(content.items())] @@ -538,7 +538,7 @@ class CellIndex(CommandIndex): class PropIndex(TagIndex): """A custom directive that creates a properties matrix.""" - + name = 'prop' localname = 'Property Index' shortname = 'Prop' @@ -659,7 +659,7 @@ class CommandDomain(Domain): else: print(f"Missing ref for {target} in {fromdocname} ") return None - + class CellDomain(CommandDomain): name = 'cell' label = 'Yosys internal cells' @@ -730,8 +730,8 @@ def setup(app: Sphinx): ('cell-prop', '') app.add_role('autoref', autoref) - + return { - 'version': '0.3', + 'version': '0.3', 'parallel_read_safe': False, } diff --git a/examples/intel/asicworld_lfsr/lfsr_updown.v b/examples/intel/asicworld_lfsr/lfsr_updown.v index 43db1606a..e60012c99 100644 --- a/examples/intel/asicworld_lfsr/lfsr_updown.v +++ b/examples/intel/asicworld_lfsr/lfsr_updown.v @@ -10,7 +10,7 @@ overflow // Overflow output input clk; input reset; - input enable; + input enable; input up_down; output [7 : 0] count; @@ -18,11 +18,11 @@ overflow // Overflow output reg [7 : 0] count; - assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : + assign overflow = (up_down) ? (count == {{7{1'b0}}, 1'b1}) : (count == {1'b1, {7{1'b0}}}) ; always @(posedge clk) - if (reset) + if (reset) count <= {7{1'b0}}; else if (enable) begin if (up_down) begin diff --git a/examples/intel/asicworld_lfsr/lfsr_updown_tb.v b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v index db29e60f1..65681801c 100644 --- a/examples/intel/asicworld_lfsr/lfsr_updown_tb.v +++ b/examples/intel/asicworld_lfsr/lfsr_updown_tb.v @@ -31,4 +31,4 @@ lfsr_updown U( .overflow ( overflow ) ); -endmodule +endmodule diff --git a/examples/smtbmc/glift/C7552.v b/examples/smtbmc/glift/C7552.v index 47a8b0d37..1dff5338e 100644 --- a/examples/smtbmc/glift/C7552.v +++ b/examples/smtbmc/glift/C7552.v @@ -1,428 +1,428 @@ -module C7552_lev2(pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, - pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, - pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, - pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, - pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, - pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, - pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, - pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, - pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, - pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, - pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, - pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, - pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, - pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, - pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, - pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, - pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, - pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, - pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, - pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, - pi200, pi201, pi202, pi203, pi204, pi205, pi206, po000, po001, po002, - po003, po004, po005, po006, po007, po008, po009, po010, po011, po012, - po013, po014, po015, po016, po017, po018, po019, po020, po021, po022, - po023, po024, po025, po026, po027, po028, po029, po030, po031, po032, - po033, po034, po035, po036, po037, po038, po039, po040, po041, po042, - po043, po044, po045, po046, po047, po048, po049, po050, po051, po052, - po053, po054, po055, po056, po057, po058, po059, po060, po061, po062, - po063, po064, po065, po066, po067, po068, po069, po070, po071, po072, - po073, po074, po075, po076, po077, po078, po079, po080, po081, po082, - po083, po084, po085, po086, po087, po088, po089, po090, po091, po092, - po093, po094, po095, po096, po097, po098, po099, po100, po101, po102, +module C7552_lev2(pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, + pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, + pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, + pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, + pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, + pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, + pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, + pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, + pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, + pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, + pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, + pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, + pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, + pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, + pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, + pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, + pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, + pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, + pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, + pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, + pi200, pi201, pi202, pi203, pi204, pi205, pi206, po000, po001, po002, + po003, po004, po005, po006, po007, po008, po009, po010, po011, po012, + po013, po014, po015, po016, po017, po018, po019, po020, po021, po022, + po023, po024, po025, po026, po027, po028, po029, po030, po031, po032, + po033, po034, po035, po036, po037, po038, po039, po040, po041, po042, + po043, po044, po045, po046, po047, po048, po049, po050, po051, po052, + po053, po054, po055, po056, po057, po058, po059, po060, po061, po062, + po063, po064, po065, po066, po067, po068, po069, po070, po071, po072, + po073, po074, po075, po076, po077, po078, po079, po080, po081, po082, + po083, po084, po085, po086, po087, po088, po089, po090, po091, po092, + po093, po094, po095, po096, po097, po098, po099, po100, po101, po102, po103, po104, po105, po106, po107); -input pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, - pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, - pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, - pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, - pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, - pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, - pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, - pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, - pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, - pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, - pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, - pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, - pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, - pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, - pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, - pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, - pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, - pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, - pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, - pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, +input pi000, pi001, pi002, pi003, pi004, pi005, pi006, pi007, pi008, pi009, + pi010, pi011, pi012, pi013, pi014, pi015, pi016, pi017, pi018, pi019, + pi020, pi021, pi022, pi023, pi024, pi025, pi026, pi027, pi028, pi029, + pi030, pi031, pi032, pi033, pi034, pi035, pi036, pi037, pi038, pi039, + pi040, pi041, pi042, pi043, pi044, pi045, pi046, pi047, pi048, pi049, + pi050, pi051, pi052, pi053, pi054, pi055, pi056, pi057, pi058, pi059, + pi060, pi061, pi062, pi063, pi064, pi065, pi066, pi067, pi068, pi069, + pi070, pi071, pi072, pi073, pi074, pi075, pi076, pi077, pi078, pi079, + pi080, pi081, pi082, pi083, pi084, pi085, pi086, pi087, pi088, pi089, + pi090, pi091, pi092, pi093, pi094, pi095, pi096, pi097, pi098, pi099, + pi100, pi101, pi102, pi103, pi104, pi105, pi106, pi107, pi108, pi109, + pi110, pi111, pi112, pi113, pi114, pi115, pi116, pi117, pi118, pi119, + pi120, pi121, pi122, pi123, pi124, pi125, pi126, pi127, pi128, pi129, + pi130, pi131, pi132, pi133, pi134, pi135, pi136, pi137, pi138, pi139, + pi140, pi141, pi142, pi143, pi144, pi145, pi146, pi147, pi148, pi149, + pi150, pi151, pi152, pi153, pi154, pi155, pi156, pi157, pi158, pi159, + pi160, pi161, pi162, pi163, pi164, pi165, pi166, pi167, pi168, pi169, + pi170, pi171, pi172, pi173, pi174, pi175, pi176, pi177, pi178, pi179, + pi180, pi181, pi182, pi183, pi184, pi185, pi186, pi187, pi188, pi189, + pi190, pi191, pi192, pi193, pi194, pi195, pi196, pi197, pi198, pi199, pi200, pi201, pi202, pi203, pi204, pi205, pi206; -output po000, po001, po002, po003, po004, po005, po006, po007, po008, po009, - po010, po011, po012, po013, po014, po015, po016, po017, po018, po019, - po020, po021, po022, po023, po024, po025, po026, po027, po028, po029, - po030, po031, po032, po033, po034, po035, po036, po037, po038, po039, - po040, po041, po042, po043, po044, po045, po046, po047, po048, po049, - po050, po051, po052, po053, po054, po055, po056, po057, po058, po059, - po060, po061, po062, po063, po064, po065, po066, po067, po068, po069, - po070, po071, po072, po073, po074, po075, po076, po077, po078, po079, - po080, po081, po082, po083, po084, po085, po086, po087, po088, po089, - po090, po091, po092, po093, po094, po095, po096, po097, po098, po099, +output po000, po001, po002, po003, po004, po005, po006, po007, po008, po009, + po010, po011, po012, po013, po014, po015, po016, po017, po018, po019, + po020, po021, po022, po023, po024, po025, po026, po027, po028, po029, + po030, po031, po032, po033, po034, po035, po036, po037, po038, po039, + po040, po041, po042, po043, po044, po045, po046, po047, po048, po049, + po050, po051, po052, po053, po054, po055, po056, po057, po058, po059, + po060, po061, po062, po063, po064, po065, po066, po067, po068, po069, + po070, po071, po072, po073, po074, po075, po076, po077, po078, po079, + po080, po081, po082, po083, po084, po085, po086, po087, po088, po089, + po090, po091, po092, po093, po094, po095, po096, po097, po098, po099, po100, po101, po102, po103, po104, po105, po106, po107; -wire n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, - n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, - n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, - n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, - n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, - n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, - n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, - n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, - n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, - n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, - n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, - n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, - n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, - n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, - n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, - n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, - n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, - n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, - n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, - n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, - n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, - n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, - n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, - n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, - n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, - n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, - n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, - n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, - n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, - n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, - n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, - n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, - n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, - n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, - n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, - n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, - n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, - n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, - n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, - n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, - n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, - n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, - n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, - n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, - n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, - n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, - n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, - n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, - n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, - n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, - n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, - n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, - n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, - n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, - n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, - n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, - n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, - n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, - n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, - n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, - n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, - n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, - n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, - n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, - n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, - n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, - n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, - n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, - n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, - n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, - n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, - n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, - n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, - n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, - n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, - n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, - n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, - n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, - n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, - n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, - n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, - n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, - n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, - n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, - n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, - n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, - n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, - n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, - n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, - n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, - n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, - n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, - n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, - n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, - n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, - n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, - n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, - n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, - n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, - n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, - n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, - n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, - n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, - n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, - n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, - n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, - n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, - n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, - n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, - n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, - n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, - n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, - n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, - n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, - n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, - n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, - n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, - n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, - n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, - n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, - n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, - n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, - n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, - n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, - n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, - n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, - n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, - n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, - n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, - n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, - n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, - n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, - n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, - n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, - n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, - n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, - n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, - n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, - n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, - n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, - n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, - n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, - n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, - n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, - n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, - n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, - n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, - n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, - n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, - n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, - n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, - n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, - n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, - n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, - n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, - n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, - n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, - n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, - n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, - n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, - n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, - n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, - n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, - n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, - n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, - n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, - n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, - n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, - n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, - n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, - n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, - n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, - n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, - n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, - n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, - n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, - n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, - n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, - n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, - n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, - n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, - n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, - n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, - n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, - n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, - n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, - n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, - n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, - n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, - n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, - n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, - n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, - n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, - n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, - n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, - n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, - n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, - n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, - n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, - n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, - n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, - n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, - n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, - n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, - n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, - n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, - n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, - n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, - n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, - n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, - n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, - n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, - n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, - n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, - n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, - n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, - n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, - n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, - n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, - n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, - n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, - n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, - n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, - n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, - n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, - n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, - n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, - n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, - n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, - n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, - n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, - n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, - n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, - n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, - n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, - n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, - n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, - n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, - n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, - n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, - n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, - n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, - n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, - n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, - n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, - n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, - n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, - n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, - n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, - n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, - n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, - n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, - n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, - n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, - n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, - n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, - n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, - n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, - n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, - n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, - n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, - n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, - n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, - n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, - n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, - n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, - n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, - n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, - n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, - n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, - n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, - n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, - n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, - n5552, n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, - n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, - n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, - n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, - n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, - n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, - n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, - n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, - n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, - n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, - n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, - n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, - n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, - n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, - n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, - n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, - n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, - n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, - n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, - n5742, n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, - n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, - n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, - n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, - n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, - n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, - n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, - n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, - n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, - n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, - n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, - n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, - n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, - n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, - n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, - n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, - n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, - n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, - n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, - n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, - n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, - n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, - n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, - n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, - n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, - n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, - n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, - n6012, n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, - n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, - n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, - n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, - n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, - n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, - n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, - n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, - n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, - n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, - n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, - n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, - n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, - n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, - n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, - n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, - n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, - n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, - n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, - n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, - n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, - n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, - n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, - n6242, n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, - n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, - n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, - n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, - n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, - n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, - n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, - n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, - n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, - n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, - n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, - n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, - n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, - n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, - n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, - n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, +wire n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, + n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, + n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, + n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, + n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, + n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, + n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, + n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, + n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, + n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, + n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, + n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, + n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, + n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, + n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, + n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, + n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, + n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, + n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, + n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, + n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, + n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, + n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, + n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, + n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, + n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, + n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, + n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, + n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, + n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, + n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, + n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, + n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, + n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, + n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, + n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, + n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, + n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, + n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, + n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, + n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, + n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, + n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, + n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, + n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, + n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, + n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, + n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, + n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, + n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, + n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, + n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, + n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, + n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, + n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, + n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, + n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, + n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, + n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, + n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, + n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, + n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, + n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, + n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, + n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, + n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, + n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, + n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, + n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, + n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, + n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, + n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, + n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, + n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, + n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, + n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, + n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, + n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, + n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, + n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, + n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, + n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, + n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, + n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, + n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, + n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, + n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, + n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, + n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, + n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, + n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, + n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, + n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, + n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, + n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, + n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, + n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, + n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, + n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, + n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, + n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, + n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, + n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, + n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, + n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, + n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, + n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, + n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, + n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, + n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, + n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, + n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, + n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, + n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, + n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, + n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, + n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, + n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, + n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, + n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, + n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, + n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, + n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, + n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, + n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, + n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, + n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, + n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, + n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, + n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, + n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, + n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, + n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, + n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, + n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, + n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, + n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, + n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, + n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, + n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, + n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, + n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, + n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, + n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, + n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, + n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, + n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, + n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, + n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, + n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, + n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, + n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, + n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, + n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, + n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, + n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, + n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, + n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, + n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, + n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, + n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, + n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, + n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, + n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, + n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, + n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, + n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, + n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, + n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, + n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, + n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, + n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, + n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, + n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, + n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, + n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, + n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, + n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, + n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, + n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, + n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, + n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, + n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, + n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, + n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, + n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, + n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, + n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, + n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, + n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, + n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, + n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, + n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, + n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, + n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, + n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, + n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, + n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, + n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, + n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, + n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, + n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, + n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, + n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, + n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, + n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, + n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, + n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, + n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, + n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, + n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, + n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, + n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, + n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, + n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, + n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, + n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, + n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, + n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, + n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, + n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, + n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, + n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, + n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, + n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, + n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, + n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, + n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, + n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, + n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, + n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, + n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, + n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, + n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, + n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, + n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, + n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, + n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, + n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, + n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, + n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, + n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, + n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, + n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, + n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, + n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, + n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, + n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, + n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, + n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, + n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, + n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, + n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, + n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, + n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, + n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, + n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, + n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, + n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, + n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, + n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, + n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, + n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, + n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, + n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, + n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, + n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, + n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, + n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, + n5512, n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, + n5522, n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, + n5532, n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, + n5542, n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, + n5552, n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, + n5562, n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, + n5572, n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, + n5582, n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, + n5592, n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, + n5602, n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, + n5612, n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, + n5622, n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, + n5632, n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, + n5642, n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, + n5652, n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, + n5662, n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, + n5672, n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, + n5682, n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, + n5692, n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, + n5702, n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, + n5712, n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, + n5722, n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, + n5732, n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, + n5742, n5743, n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, + n5752, n5753, n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, + n5762, n5763, n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, + n5772, n5773, n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, + n5782, n5783, n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, + n5792, n5793, n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, + n5802, n5803, n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, + n5812, n5813, n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, + n5822, n5823, n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, + n5832, n5833, n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, + n5842, n5843, n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, + n5852, n5853, n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, + n5862, n5863, n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, + n5872, n5873, n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, + n5882, n5883, n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, + n5892, n5893, n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, + n5902, n5903, n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, + n5912, n5913, n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, + n5922, n5923, n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, + n5932, n5933, n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, + n5942, n5943, n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, + n5952, n5953, n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, + n5962, n5963, n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, + n5972, n5973, n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, + n5982, n5983, n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, + n5992, n5993, n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, + n6002, n6003, n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, + n6012, n6013, n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, + n6022, n6023, n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, + n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, + n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, + n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, + n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, + n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, + n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, + n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, + n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, + n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, + n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, + n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, + n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, + n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, + n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, + n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, + n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, + n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, + n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, + n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, + n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, + n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, + n6242, n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, + n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, + n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, + n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, + n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, + n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, + n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, + n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, + n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, + n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, + n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, + n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, + n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, + n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, + n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, + n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405; assign po001 = pi187; diff --git a/examples/smtbmc/glift/C7552.ys b/examples/smtbmc/glift/C7552.ys index a9a1f5dc2..dcae30e85 100644 --- a/examples/smtbmc/glift/C7552.ys +++ b/examples/smtbmc/glift/C7552.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/C880.v b/examples/smtbmc/glift/C880.v index 20e665f4a..799c02ddf 100644 --- a/examples/smtbmc/glift/C880.v +++ b/examples/smtbmc/glift/C880.v @@ -1,58 +1,58 @@ -module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, - pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59, - po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, +module C880_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, + pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59, + po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20, po21, po22, po23, po24, po25); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, pi50, pi51, pi52, pi53, pi54, pi55, pi56, pi57, pi58, pi59; -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20, po21, po22, po23, po24, po25; -wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357, - n358, n359, n360, n361, n362, n363, n365, n366, n367, n368, - n369, n370, n371, n372, n373, n374, n375, n376, n378, n379, - n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, - n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n416, n417, n418, n419, n420, - n421, n422, n423, n424, n425, n426, n428, n429, n430, n431, - n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, - n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, - n452, n453, n455, n456, n457, n458, n459, n460, n461, n462, - n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, - n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, - n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, - n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, - n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, - n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, - n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, - n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, - n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, - n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, - n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, - n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, - n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, - n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, - n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, - n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, - n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, - n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, - n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, - n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, - n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, - n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, - n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, +wire n137, n346, n364, n415, n295, n427, n351, n377, n454, n357, + n358, n359, n360, n361, n362, n363, n365, n366, n367, n368, + n369, n370, n371, n372, n373, n374, n375, n376, n378, n379, + n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, + n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n416, n417, n418, n419, n420, + n421, n422, n423, n424, n425, n426, n428, n429, n430, n431, + n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, + n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, + n452, n453, n455, n456, n457, n458, n459, n460, n461, n462, + n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, + n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, + n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, + n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, + n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, + n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, + n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, + n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, + n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, + n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, + n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, + n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, + n583, n584, n585, n586, n587, n588, n589, n590, n591, n592, + n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, + n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, + n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, + n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, + n633, n634, n635, n636, n637, n638, n639, n640, n641, n642, + n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, + n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, + n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, + n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, + n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695, n696; diff --git a/examples/smtbmc/glift/C880.ys b/examples/smtbmc/glift/C880.ys index 410768f21..37b568da1 100644 --- a/examples/smtbmc/glift/C880.ys +++ b/examples/smtbmc/glift/C880.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/alu2.v b/examples/smtbmc/glift/alu2.v index 6b6e3d7af..ac2b2b10c 100644 --- a/examples/smtbmc/glift/alu2.v +++ b/examples/smtbmc/glift/alu2.v @@ -1,42 +1,42 @@ -module alu2_lev2(pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9, +module alu2_lev2(pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9, po0, po1, po2, po3, po4, po5); input pi0, pi1, pi2, pi3, pi4, pi5, pi6, pi7, pi8, pi9; output po0, po1, po2, po3, po4, po5; -wire n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, - n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, - n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, - n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, - n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, - n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, - n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, - n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, - n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, - n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, - n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, - n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, - n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, - n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, - n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, - n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, - n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, - n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, - n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, - n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, - n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, - n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, - n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, - n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, - n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, - n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, - n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, - n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, - n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, - n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, - n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, - n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, +wire n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, + n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, + n378, n379, n380, n381, n382, n383, n384, n385, n386, n387, + n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, + n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, + n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, + n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, + n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, + n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, + n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, + n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, + n468, n469, n470, n471, n472, n473, n474, n475, n476, n477, + n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, + n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, + n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, + n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, + n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, + n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, + n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, + n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, + n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, + n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, + n578, n579, n580, n581, n582, n583, n584, n585, n586, n587, + n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, + n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, + n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, + n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, + n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, + n638, n639, n640, n641, n642, n643, n644, n645, n646, n647, + n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, + n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, + n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687; AN2 U363 ( .A(n358), .B(po2), .Z(po5)); diff --git a/examples/smtbmc/glift/alu2.ys b/examples/smtbmc/glift/alu2.ys index b1671752e..f43dad075 100644 --- a/examples/smtbmc/glift/alu2.ys +++ b/examples/smtbmc/glift/alu2.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/alu4.v b/examples/smtbmc/glift/alu4.v index e110612e5..bc221eb04 100644 --- a/examples/smtbmc/glift/alu4.v +++ b/examples/smtbmc/glift/alu4.v @@ -1,80 +1,80 @@ -module alu4_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +module alu4_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13, po0, po1, po2, po3, po4, po5, po6, po7); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13; output po0, po1, po2, po3, po4, po5, po6, po7; -wire n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, - n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, - n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, - n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, - n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, - n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, - n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, - n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, - n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, - n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, - n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, - n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, - n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, - n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, - n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, - n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, - n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, - n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, - n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, - n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, - n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, - n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, - n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, - n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, - n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, - n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, - n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, - n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, - n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, - n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, - n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, - n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, - n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, - n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, - n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, - n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, - n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, - n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, - n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, - n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, - n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, - n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, - n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, - n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, - n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, - n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, - n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, - n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, - n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, - n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, - n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, - n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, - n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, - n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, - n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, - n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, - n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, - n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, - n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, - n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, - n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, - n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, - n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, - n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, - n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, - n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, - n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, - n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, - n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, +wire n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, + n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, + n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, + n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, + n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, + n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, + n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, + n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, + n785, n786, n787, n788, n789, n790, n791, n792, n793, n794, + n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, + n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, + n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, + n825, n826, n827, n828, n829, n830, n831, n832, n833, n834, + n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, + n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, + n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, + n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, + n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, + n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, + n895, n896, n897, n898, n899, n900, n901, n902, n903, n904, + n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, + n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, + n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, + n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, + n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, + n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, + n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, + n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, + n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, + n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, + n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, + n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, + n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, + n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, + n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, + n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, + n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, + n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, + n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, + n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, + n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, + n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, + n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, + n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, + n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, + n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, + n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, + n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, + n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, + n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, + n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, + n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, + n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, + n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, + n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, + n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, + n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, + n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, + n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, + n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, + n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, + n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, + n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, + n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, + n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, + n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, + n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, + n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, + n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396; AN2 U712 ( .A(n705), .B(po4), .Z(po7)); diff --git a/examples/smtbmc/glift/alu4.ys b/examples/smtbmc/glift/alu4.ys index 8e8d14225..593ba45a7 100644 --- a/examples/smtbmc/glift/alu4.ys +++ b/examples/smtbmc/glift/alu4.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/t481.v b/examples/smtbmc/glift/t481.v index b23c8b211..6735fc9a9 100644 --- a/examples/smtbmc/glift/t481.v +++ b/examples/smtbmc/glift/t481.v @@ -1,15 +1,15 @@ -module t481_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +module t481_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13, pi14, pi15, po0); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, pi10, pi11, pi12, pi13, pi14, pi15; output po0; -wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, - n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, - n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, - n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, +wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, + n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, + n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, + n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90; OR2 U47 ( .A(n46), .B(n47), .Z(po0)); diff --git a/examples/smtbmc/glift/t481.ys b/examples/smtbmc/glift/t481.ys index 0e4afffda..ac31f8fc1 100644 --- a/examples/smtbmc/glift/t481.ys +++ b/examples/smtbmc/glift/t481.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/too_large.v b/examples/smtbmc/glift/too_large.v index 67605cc34..8392a7a13 100644 --- a/examples/smtbmc/glift/too_large.v +++ b/examples/smtbmc/glift/too_large.v @@ -1,43 +1,43 @@ -module too_large_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, po0, po1, +module too_large_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, po0, po1, po2); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37; output po0, po1, po2; -wire n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, - n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, - n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, - n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, - n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, - n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, - n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, - n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, - n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, - n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, - n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, - n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, - n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, - n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, - n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, - n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, - n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, - n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, - n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, - n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, - n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, - n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, - n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, - n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, - n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, - n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, - n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, +wire n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, + n290, n291, n292, n293, n294, n295, n296, n297, n298, n299, + n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, + n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, + n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, + n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, + n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, + n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, + n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, + n370, n371, n372, n373, n374, n375, n376, n377, n378, n379, + n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, + n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, + n400, n401, n402, n403, n404, n405, n406, n407, n408, n409, + n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, + n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, + n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, + n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, + n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, + n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, + n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, + n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, + n490, n491, n492, n493, n494, n495, n496, n497, n498, n499, + n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, + n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, + n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, + n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, + n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556; AN2 U283 ( .A(n280), .B(n281), .Z(po2)); diff --git a/examples/smtbmc/glift/too_large.ys b/examples/smtbmc/glift/too_large.ys index 77be61e17..ec5edd0ca 100644 --- a/examples/smtbmc/glift/too_large.ys +++ b/examples/smtbmc/glift/too_large.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/ttt2.v b/examples/smtbmc/glift/ttt2.v index 47ca7684a..1c538b917 100644 --- a/examples/smtbmc/glift/ttt2.v +++ b/examples/smtbmc/glift/ttt2.v @@ -1,31 +1,31 @@ -module ttt2_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, po00, po01, po02, po03, po04, po05, - po06, po07, po08, po09, po10, po11, po12, po13, po14, po15, +module ttt2_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, po00, po01, po02, po03, po04, po05, + po06, po07, po08, po09, po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, pi20, pi21, pi22, pi23; -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, po20; -wire n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, - n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, - n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, - n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, - n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, - n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, - n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, - n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, - n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, - n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, - n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, - n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, - n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, - n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, +wire n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, + n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, + n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, + n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, + n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, + n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, + n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, + n218, n219, n220, n221, n222, n223, n224, n225, n226, n227, + n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, + n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, + n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, + n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, + n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, + n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293; AN2 U168 ( .A(n148), .B(n149), .Z(po20)); diff --git a/examples/smtbmc/glift/ttt2.ys b/examples/smtbmc/glift/ttt2.ys index 1314d4975..e1f9e05a8 100644 --- a/examples/smtbmc/glift/ttt2.ys +++ b/examples/smtbmc/glift/ttt2.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/examples/smtbmc/glift/x1.v b/examples/smtbmc/glift/x1.v index 39b5284d3..6b2f51917 100644 --- a/examples/smtbmc/glift/x1.v +++ b/examples/smtbmc/glift/x1.v @@ -1,52 +1,52 @@ -module x1_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, - pi50, po00, po01, po02, po03, po04, po05, po06, po07, po08, - po09, po10, po11, po12, po13, po14, po15, po16, po17, po18, - po19, po20, po21, po22, po23, po24, po25, po26, po27, po28, +module x1_lev2(pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, + pi50, po00, po01, po02, po03, po04, po05, po06, po07, po08, + po09, po10, po11, po12, po13, po14, po15, po16, po17, po18, + po19, po20, po21, po22, po23, po24, po25, po26, po27, po28, po29, po30, po31, po32, po33, po34); -input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, - pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, - pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, - pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, - pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, +input pi00, pi01, pi02, pi03, pi04, pi05, pi06, pi07, pi08, pi09, + pi10, pi11, pi12, pi13, pi14, pi15, pi16, pi17, pi18, pi19, + pi20, pi21, pi22, pi23, pi24, pi25, pi26, pi27, pi28, pi29, + pi30, pi31, pi32, pi33, pi34, pi35, pi36, pi37, pi38, pi39, + pi40, pi41, pi42, pi43, pi44, pi45, pi46, pi47, pi48, pi49, pi50; -output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, - po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, - po20, po21, po22, po23, po24, po25, po26, po27, po28, po29, +output po00, po01, po02, po03, po04, po05, po06, po07, po08, po09, + po10, po11, po12, po13, po14, po15, po16, po17, po18, po19, + po20, po21, po22, po23, po24, po25, po26, po27, po28, po29, po30, po31, po32, po33, po34; -wire po05, po16, po18, po24, po25, po28, po29, n270, n271, n272, - n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, - n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, - n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, - n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, - n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, - n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, - n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, - n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, - n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, - n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, - n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, - n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, - n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, - n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, - n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, - n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, - n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, - n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, - n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, - n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, - n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, - n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, - n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, - n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, - n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, - n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, +wire po05, po16, po18, po24, po25, po28, po29, n270, n271, n272, + n273, n274, n275, n276, n277, n278, n279, n280, n281, n282, + n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, + n293, n294, n295, n296, n297, n298, n299, n300, n301, n302, + n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, + n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, + n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, + n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, + n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, + n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, + n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, + n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, + n383, n384, n385, n386, n387, n388, n389, n390, n391, n392, + n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, + n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, + n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, + n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, + n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, + n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, + n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, + n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, + n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, + n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, + n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, + n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, + n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, + n523, n524, n525, n526, n527, n528, n529, n530, n531, n532, n533; assign po05 = pi32; diff --git a/examples/smtbmc/glift/x1.ys b/examples/smtbmc/glift/x1.ys index b588dea92..406127c10 100644 --- a/examples/smtbmc/glift/x1.ys +++ b/examples/smtbmc/glift/x1.ys @@ -36,6 +36,6 @@ opt solved miter -equiv spec solved satmiter flatten sat -prove trigger 0 satmiter -delete satmiter +delete satmiter stat shell diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 20a23ef8f..7beb152cb 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -130,13 +130,13 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil if (log_verific_callback) { string full_message = stringf("%s%s\n", message_prefix, message); -#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), - linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, +#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? linefile->GetLeftLine() : 0, linefile ? linefile->GetLeftCol() : 0, linefile ? linefile->GetRightLine() : 0, linefile ? linefile->GetRightCol() : 0, full_message.c_str()); #else - log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), - linefile ? LineFile::GetLineNo(linefile) : 0, 0, + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), + linefile ? LineFile::GetLineNo(linefile) : 0, 0, linefile ? LineFile::GetLineNo(linefile) : 0, 0, full_message.c_str()); #endif } else { @@ -323,7 +323,7 @@ static const RTLIL::Const extract_vhdl_const(const char *value, bool output_sig bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; }); if (isBinary) c = RTLIL::Const::from_string(data); - else + else c = RTLIL::Const(data); } else if (val.size()==3 && val[0]=='\'' && val.back()=='\'') { c = RTLIL::Const::from_string(val.substr(1,val.size()-2)); @@ -413,7 +413,7 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value // SystemVerilog if (type_name && strcmp(type_name, "real")==0) { return extract_real_value(val); - } else + } else return extract_verilog_const(value, allow_string, output_signed); } @@ -1277,7 +1277,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr for (unsigned j = 0 ; j < selector->GetNumConditions(i) ; ++j) { Array left_bound, right_bound ; selector->GetCondition(i, j, &left_bound, &right_bound); - + SigSpec sel_left = sig_select_values.extract(offset_select, select_width); offset_select += select_width; @@ -1565,7 +1565,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma char *architecture_name = name_space.ReName(nl->Name()) ; module->set_string_attribute(ID(architecture), (architecture_name) ? architecture_name : nl->Name()); } -#endif +#endif const char *param_name ; const char *param_value ; MapIter mi; @@ -2827,13 +2827,13 @@ void save_blackbox_msg_state() void restore_blackbox_msg_state() { #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - Message::ClearMessageType("VERI-1063") ; + Message::ClearMessageType("VERI-1063") ; if (Message::GetMessageType("VERI-1063")!=prev_1063) Message::SetMessageType("VERI-1063", prev_1063); #endif #ifdef VERIFIC_VHDL_SUPPORT - Message::ClearMessageType("VHDL-1240") ; - Message::ClearMessageType("VHDL-1241") ; + Message::ClearMessageType("VHDL-1240") ; + Message::ClearMessageType("VHDL-1241") ; if (Message::GetMessageType("VHDL-1240")!=prev_1240) Message::SetMessageType("VHDL-1240", prev_1240); if (Message::GetMessageType("VHDL-1241")!=prev_1241) @@ -3414,7 +3414,7 @@ struct VerificPass : public Pass { log("\n"); #if defined(YOSYS_ENABLE_VERIFIC) and defined(YOSYSHQ_VERIFIC_EXTENSIONS) VerificExtensions::Help(); -#endif +#endif log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"); log("https://www.yosyshq.com/\n"); log("\n"); @@ -3470,7 +3470,7 @@ struct VerificPass : public Pass { VhdlPrimaryUnit *unit ; if (!flag_lib) return; VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); - if (vhdl_lib) { + if (vhdl_lib) { FOREACH_VHDL_PRIMARY_UNIT(vhdl_lib, mi, unit) { if (!unit) continue; map.Insert(unit,unit); @@ -3502,7 +3502,7 @@ struct VerificPass : public Pass { VeriModule *veri_module ; if (!flag_lib) return; VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); - if (veri_lib) { + if (veri_lib) { FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { if (!veri_module) continue; map.Insert(veri_module,veri_module); @@ -4433,12 +4433,12 @@ struct VerificPass : public Pass { } } #ifdef YOSYSHQ_VERIFIC_EXTENSIONS - if (VerificExtensions::Execute(args, argidx, work, + if (VerificExtensions::Execute(args, argidx, work, [this](const std::vector &args, size_t argidx, std::string msg) { cmd_error(args, argidx, msg); } )) { goto check_error; } -#endif +#endif cmd_error(args, argidx, "Missing or unsupported mode parameter.\n"); diff --git a/kernel/cellhelp.py b/kernel/cellhelp.py index f834ead83..a92922fe6 100644 --- a/kernel/cellhelp.py +++ b/kernel/cellhelp.py @@ -19,7 +19,7 @@ class SimHelper: def __init__(self) -> None: self.desc = [] self.tags = [] - + def __str__(self) -> str: printed_fields = [ "name", "title", "ports", "source", "desc", "code", "group", "ver", @@ -65,7 +65,7 @@ for line in fileinput.input(): elif line.startswith("//* "): _, key, val = line.split(maxsplit=2) setattr(simHelper, key, val) - + # code parsing if line.startswith("module "): clean_line = line[7:].replace("\\", "").replace(";", "") diff --git a/kernel/compressor_tree.cc b/kernel/compressor_tree.cc index de2260d26..b02a8fd5c 100644 --- a/kernel/compressor_tree.cc +++ b/kernel/compressor_tree.cc @@ -99,7 +99,7 @@ std::vector generate_partial_products(Module *module, SigSpec a, SigSp // Correction constants auto push_one_at = [&](int col) { - if (col < 0 || col >= width) + if (col < 0 || col >= width) return; std::vector v(width, RTLIL::State::S0); v[col] = RTLIL::State::S1; diff --git a/kernel/functional.h b/kernel/functional.h index 3334f02c8..6d98da949 100644 --- a/kernel/functional.h +++ b/kernel/functional.h @@ -33,7 +33,7 @@ YOSYS_NAMESPACE_BEGIN namespace Functional { // each function is documented with a short pseudocode declaration or definition // standard C/Verilog operators are used to describe the result - // + // // the sorts used in this are: // - bit[N]: a bitvector of N bits // bit[N] can be indicated as signed or unsigned. this is not tracked by the functional backend @@ -345,9 +345,9 @@ namespace Functional { case Fn::reduce_xor: return v.reduce_xor(*this, arg(0)); break; case Fn::equal: return v.equal(*this, arg(0), arg(1)); break; case Fn::not_equal: return v.not_equal(*this, arg(0), arg(1)); break; - case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; + case Fn::signed_greater_than: return v.signed_greater_than(*this, arg(0), arg(1)); break; case Fn::signed_greater_equal: return v.signed_greater_equal(*this, arg(0), arg(1)); break; - case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; + case Fn::unsigned_greater_than: return v.unsigned_greater_than(*this, arg(0), arg(1)); break; case Fn::unsigned_greater_equal: return v.unsigned_greater_equal(*this, arg(0), arg(1)); break; case Fn::logical_shift_left: return v.logical_shift_left(*this, arg(0), arg(1)); break; case Fn::logical_shift_right: return v.logical_shift_right(*this, arg(0), arg(1)); break; @@ -510,7 +510,7 @@ namespace Functional { return a; return add(Fn::reduce_or, Sort(1), {a}); } - Node reduce_xor(Node a) { + Node reduce_xor(Node a) { check_unary(a); if(a.width() == 1) return a; diff --git a/kernel/io.h b/kernel/io.h index e15194e79..f80b9e908 100644 --- a/kernel/io.h +++ b/kernel/io.h @@ -202,7 +202,7 @@ static auto has_name_member_imp(int) -> decltype(static_cast(std::declval().name), std::true_type{}); template -static auto has_name_member_imp(long) +static auto has_name_member_imp(long) -> std::false_type; template @@ -213,7 +213,7 @@ static auto ptr_has_name_member_imp(int) -> decltype(static_cast(std::declval()->name), std::true_type{}); template -static auto ptr_has_name_member_imp(long) +static auto ptr_has_name_member_imp(long) -> std::false_type; template @@ -475,7 +475,7 @@ public: private: std::string_view fmt; bool has_escapes = false; - // Making array at least size of one to make MSVC happy and strict to standards + // Making array at least size of one to make MSVC happy and strict to standards FoundFormatSpec specs[sizeof...(Args) ? sizeof...(Args) : 1] = {}; }; diff --git a/kernel/tclapi.cc b/kernel/tclapi.cc index 2479b7e3c..70d587904 100644 --- a/kernel/tclapi.cc +++ b/kernel/tclapi.cc @@ -567,7 +567,7 @@ int yosys_tcl_interp_init(Tcl_Interp *interp) // unpack // pack - // Note (dev jf 24-12-02): Make log_id escape everything that’s not a valid + // Note (dev jf 24-12-02): Make log_id escape everything that’s not a valid // verilog identifier before adding any tcl API that returns IdString values // to avoid -option injection diff --git a/kernel/topo_scc.h b/kernel/topo_scc.h index 7e730bb27..6b4ffc1e2 100644 --- a/kernel/topo_scc.h +++ b/kernel/topo_scc.h @@ -241,7 +241,7 @@ public: } // process all remaining nodes in the graph - TopoSortedSccs &process_all() { + TopoSortedSccs &process_all() { node_enumerator nodes = graph.enumerate_nodes(); // iterate over all nodes to ensure we process the whole graph while (!nodes.finished()) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 426216800..d219f8da3 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -217,7 +217,7 @@ struct CheckPass : public Pass { const int threshold = 1024; - // if the multiplication may overflow we will catch it here + // if the multiplication may overflow we will catch it here if (in_widths + out_widths >= threshold) return true; @@ -400,7 +400,7 @@ struct CheckPass : public Pass { message += stringf(" cell %s (%s)%s\n", driver, driver->type.unescape(), driver_src); - if (!coarsened_cells.count(driver)) { + if (!coarsened_cells.count(driver)) { MatchingEdgePrinter printer(message, sigmap, prev, bit); printer.add_edges_from_cell(driver); } else { @@ -414,7 +414,7 @@ struct CheckPass : public Pass { std::string src_attr = wire->get_src_attribute(); wire_src = stringf(" source: %s", src_attr); } - message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src); + message += stringf(" wire %s%s\n", log_signal(SigBit(wire, pair.second)), wire_src); } prev = bit; diff --git a/passes/cmds/linecoverage.cc b/passes/cmds/linecoverage.cc index 2f77f6f21..a65667f38 100644 --- a/passes/cmds/linecoverage.cc +++ b/passes/cmds/linecoverage.cc @@ -90,7 +90,7 @@ struct CoveragePass : public Pass { std::map> uncovered_lines; std::map> all_lines; - + for (auto module : design->modules()) { log_debug("Module %s:\n", module); @@ -136,7 +136,7 @@ struct CoveragePass : public Pass { fout << "DA:" << l << ","; if (uncovered_lines.count(file_entry.first) && uncovered_lines[file_entry.first].count(l)) fout << "0"; - else + else fout << "1"; fout << "\n"; } diff --git a/passes/cmds/linux_perf.cc b/passes/cmds/linux_perf.cc index 2b75a3a79..bbe23c9e5 100644 --- a/passes/cmds/linux_perf.cc +++ b/passes/cmds/linux_perf.cc @@ -36,7 +36,7 @@ struct LinuxPerf : public Pass { bool formatted_help() override { auto *help = PrettyHelp::get_current(); - + auto content_root = help->get_root(); content_root->usage("linux_perf [on|off]"); diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index cab4ab81c..4d75b3872 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -106,7 +106,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-warn" && argidx+1 < args.size()) { std::string pattern = args[++argidx]; - if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { log("Added regex '%s' for warnings to warn list.\n", pattern); log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); @@ -118,7 +118,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-nowarn" && argidx+1 < args.size()) { std::string pattern = args[++argidx]; - if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { log("Added regex '%s' for warnings to nowarn list.\n", pattern); log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); @@ -130,7 +130,7 @@ struct LoggerPass : public Pass { } if (args[argidx] == "-werror" && argidx+1 < args.size()) { std::string pattern = args[++argidx]; - if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); + if (pattern.front() == '\"' && pattern.back() == '\"') pattern = pattern.substr(1, pattern.size() - 2); try { log("Added regex '%s' for warnings to werror list.\n", pattern); log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 1fcc35dfa..76b323338 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1472,7 +1472,7 @@ struct SelectPass : public Pass { const char *common_flagset = "-add, -del, -assert-none, -assert-any, -assert-mod-count, -assert-count, -assert-max, or -assert-min"; if (common_flagset_tally > 1) - log_cmd_error("Options %s can not be combined.\n", common_flagset); + log_cmd_error("Options %s can not be combined.\n", common_flagset); if ((list_mode || !write_file.empty() || count_mode) && common_flagset_tally) log_cmd_error("Options -list, -list-mod, -write and -count can not be combined with %s.\n", common_flagset); diff --git a/passes/cmds/setenv.cc b/passes/cmds/setenv.cc index 90eeab702..bb071b271 100644 --- a/passes/cmds/setenv.cc +++ b/passes/cmds/setenv.cc @@ -47,14 +47,14 @@ struct SetenvPass : public Pass { std::string name = args[1]; std::string value = args[2]; if (value.front() == '\"' && value.back() == '\"') value = value.substr(1, value.size() - 2); - + #if defined(_WIN32) _putenv_s(name.c_str(), value.c_str()); #else if (setenv(name.c_str(), value.c_str(), 1)) log_cmd_error("Invalid name \"%s\".\n", name); #endif - + } } SetenvPass; diff --git a/passes/cmds/timeest.cc b/passes/cmds/timeest.cc index 579a9c48e..80843aaee 100644 --- a/passes/cmds/timeest.cc +++ b/passes/cmds/timeest.cc @@ -122,7 +122,7 @@ struct EstimateSta { if (aigs.at(fingerprint).name.empty()) { log_error("Unsupported cell '%s' in module '%s'", cell->type.unescape(), m); - } + } } combinational.push_back(cell); @@ -217,9 +217,9 @@ struct EstimateSta { if (!topo.sort()) log_error("Module '%s' contains combinational loops", m); - + // now we determine how long it takes for signals to stabilize - + // `levels` records the time after a clock edge after which a signal is stable dict, arrivalint> levels; diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index a7be16577..7d7091c42 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -343,7 +343,7 @@ struct MemMapping { rejected_cfg_debug_msgs += "\n"; } } - + void log_reject(const Ram &ram, const PortGroup &pg, int pvi, std::string message) { if(ys_debug(1)) { rejected_cfg_debug_msgs += stringf("can't map to option selection ["); @@ -516,7 +516,7 @@ std::pair search_for_attribute(Mem mem, IdString attr) { for (SigBit bit: port.addr) if (bit.is_wire() && bit.wire->has_attribute(attr)) return std::make_pair(true, bit.wire->attributes.at(attr)); - + return std::make_pair(false, Const()); } diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 773bbfde9..f78da20c0 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -159,7 +159,7 @@ struct MuxpackWorker if (cell->type == ID($mux)) b_sig = sigmap(cell->getPort(ID::B)); SigSpec y_sig = sigmap(cell->getPort(ID::Y)); - + if (sig_chain_next.count(a_sig)) for (auto a_bit : a_sig) sigbit_with_non_chain_users.insert(a_bit); diff --git a/passes/opt/opt_balance_tree.cc b/passes/opt/opt_balance_tree.cc index 98d5b9928..915a6fb39 100644 --- a/passes/opt/opt_balance_tree.cc +++ b/passes/opt/opt_balance_tree.cc @@ -73,15 +73,15 @@ struct OptBalanceTreeWorker { // Base case: if we have only one source, return it if (sources.size() == 1) return sources[0]; - + // Base case: if we have two sources, create a single cell if (sources.size() == 2) { // Create a new cell of the same type Cell* new_cell = module->addCell(NEW_ID, cell_type); - + // Copy attributes from reference cell new_cell->attributes = cell->attributes; - + // Create output wire int out_width = cell->getParam(ID::Y_WIDTH).as_int(); if (cell_type == ID($add)) @@ -89,7 +89,7 @@ struct OptBalanceTreeWorker { else if (cell_type == ID($mul)) out_width = sources[0].size() + sources[1].size(); Wire* out_wire = module->addWire(NEW_ID, out_width); - + // Connect ports and fix up parameters new_cell->setPort(ID::A, sources[0]); new_cell->setPort(ID::B, sources[1]); @@ -97,26 +97,26 @@ struct OptBalanceTreeWorker { new_cell->fixup_parameters(); new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); - + // Update count and return output wire cell_count[cell_type]++; return out_wire; } - + // Recursive case: split sources into two groups and create subtrees int mid = (sources.size() + 1) / 2; vector left_sources(sources.begin(), sources.begin() + mid); vector right_sources(sources.begin() + mid, sources.end()); - + SigSpec left_tree = create_balanced_tree(left_sources, cell_type, cell); SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell); - + // Create a cell to combine the two subtrees Cell* new_cell = module->addCell(NEW_ID, cell_type); - + // Copy attributes from reference cell new_cell->attributes = cell->attributes; - + // Create output wire int out_width = cell->getParam(ID::Y_WIDTH).as_int(); if (cell_type == ID($add)) @@ -124,7 +124,7 @@ struct OptBalanceTreeWorker { else if (cell_type == ID($mul)) out_width = left_tree.size() + right_tree.size(); Wire* out_wire = module->addWire(NEW_ID, out_width); - + // Connect ports and fix up parameters new_cell->setPort(ID::A, left_tree); new_cell->setPort(ID::B, right_tree); @@ -132,7 +132,7 @@ struct OptBalanceTreeWorker { new_cell->fixup_parameters(); new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED)); new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED)); - + // Update count and return output wire cell_count[cell_type]++; return out_wire; @@ -280,7 +280,7 @@ struct OptBalanceTreeWorker { { // Create a tree log_debug(" Creating tree for %s with %d sources and %d inner cells...\n", head_cell, GetSize(sources), inner_cells); - + // Build a vector of all source signals vector source_signals; vector signed_flags; @@ -295,10 +295,10 @@ struct OptBalanceTreeWorker { if (!std::all_of(signed_flags.begin(), signed_flags.end(), [&](bool flag) { return flag == signed_flags[0]; })) { continue; } - + // Create the balanced tree SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell); - + // Connect the tree output to the head cell's output SigSpec head_output = sigmap(head_cell->getPort(ID::Y)); int connect_width = std::min(head_output.size(), tree_output.size()); @@ -313,7 +313,7 @@ struct OptBalanceTreeWorker { } } } - + // Remove all consumed cells, which now have been replaced by trees for (auto cell : consumed_cells) module->remove(cell); diff --git a/passes/opt/opt_hier.cc b/passes/opt/opt_hier.cc index 532bcad63..878ccfe0a 100644 --- a/passes/opt/opt_hier.cc +++ b/passes/opt/opt_hier.cc @@ -75,7 +75,7 @@ struct ModuleIndex { } else { classes[pair.second[i]].append(pair.first[i]); } - } + } } } @@ -217,7 +217,7 @@ struct UsageData { for (auto port_name : module->ports) { Wire *port = module->wire(port_name); log_assert(port); - + if (port->port_input && port->port_output) { // ignore bidirectional: hard to come up with sound handling continue; diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 72c465ead..039c02d7d 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -296,7 +296,7 @@ struct OptLutWorker luts_dlogic_inputs.erase(lut); module->remove(lut); - + eliminated_count++; if (limit > 0) limit--; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index b213048aa..1836806cc 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -445,7 +445,7 @@ struct OptSharePass : public Pass { while (mux_port_offset + op_conn_width < mux_port_size && op_outsig_offset + op_conn_width < op_outsig_size && mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width]) - op_conn_width++; + op_conn_width++; log_assert(op_conn_width >= 1); diff --git a/passes/opt/peepopt_muldiv_c.pmg b/passes/opt/peepopt_muldiv_c.pmg index eb8b31e13..a0b10d584 100644 --- a/passes/opt/peepopt_muldiv_c.pmg +++ b/passes/opt/peepopt_muldiv_c.pmg @@ -55,19 +55,19 @@ code int c_const_int = c_const.as_int(c_const_signed); int b_const_int_shifted = b_const_int << offset; - // Helper lambdas for two's complement math + // Helper lambdas for two's complement math auto sign2sComplement = [](auto value, int numBits) { if (value & (1 << (numBits - 1))) { - return -1; + return -1; } else { - return 1; + return 1; } }; auto twosComplement = [](auto value, int numBits) { if (value & (1 << (numBits - 1))) { return (~value) + 1; // invert bits before adding 1 } else { - return value; + return value; } }; diff --git a/passes/opt/peepopt_shiftadd.pmg b/passes/opt/peepopt_shiftadd.pmg index 6144e44ef..622516062 100644 --- a/passes/opt/peepopt_shiftadd.pmg +++ b/passes/opt/peepopt_shiftadd.pmg @@ -104,8 +104,8 @@ code std::string location = shift->get_src_attribute(); if(shiftadd_max_ratio>0 && offset<0 && -offset*shiftadd_max_ratio > old_a.size()) { - log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) " - "was ignored to avoid high resource usage, see help peepopt\n", + log_warning("at %s: candiate for shiftadd optimization (shifting '%s' by '%s - %d' bits) " + "was ignored to avoid high resource usage, see help peepopt\n", location.c_str(), log_signal(old_a), log_signal(var_signal), -offset); reject; } diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 2680252a7..6ceb2b9b7 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -116,7 +116,7 @@ struct CutpointPass : public Pass { for (auto bit : sigmap(conn.second)) if (bit.wire) wire_drivers.insert(bit); - + for (auto wire : module->wires()) if (wire->port_input) for (auto bit : sigmap(wire)) diff --git a/passes/sat/qbfsat.h b/passes/sat/qbfsat.h index 3441b7819..ea5d44d7a 100644 --- a/passes/sat/qbfsat.h +++ b/passes/sat/qbfsat.h @@ -132,7 +132,7 @@ struct QbfSolutionType { //More importantly, we want to have the ability to port hole assignments to other modules with compatible //hole names and widths. Obviously in those cases source locations of the $anyconst cells will not match. // - //Option 2 has the benefits previously described, but wire names can be changed automatically by + //Option 2 has the benefits previously described, but wire names can be changed automatically by //optimization or techmapping passes, especially when (ex/im)porting from BLIF for optimization with ABC. // //The approach taken here is to allow both options. We write the assignment information for each bit of diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 2144b6266..bbddb2c16 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -155,7 +155,7 @@ void zinit(Const &v) struct SimInstance { SimShared *shared; - + std::string scope; Module *module; Cell *instance; @@ -183,7 +183,7 @@ struct SimInstance State past_clk; State past_ce; State past_srst; - + FfData data; }; @@ -1050,7 +1050,7 @@ struct SimInstance } } } - + for (auto signal : signal_database) { if (shared->hdlname && signal.first->name.isPublic() && signal.first->has_attribute(ID::hdlname)) { @@ -1182,7 +1182,7 @@ struct SimInstance { if (cell->is_mem_cell()) { std::string memid = cell->parameters.at(ID::MEMID).decode_string(); - for (auto &data : fst_memories[memid]) + for (auto &data : fst_memories[memid]) { std::string v = shared->fst->valueOf(data.second); set_memory_state(memid, Const(data.first), Const::from_string(v)); @@ -1399,7 +1399,7 @@ struct SimWorker : SimShared } for(auto& writer : outputfiles) writer->write(use_signal); - + if (writeback) { pool wbmods; top->writeback(wbmods); @@ -1592,7 +1592,7 @@ struct SimWorker : SimShared if (start_time.time < fst->getStartTime()) log_warning("Start time is before simulation file start time\n"); startCount = fst->getStartTime(); - } else if (start_time.end) + } else if (start_time.end) startCount = fst->getEndTime(); else { startCount = start_time.time * pow10(start_time.scale - fst->getScale()); @@ -1605,7 +1605,7 @@ struct SimWorker : SimShared if (stop_time.time < fst->getStartTime()) log_warning("Stop time is before simulation file start time\n"); stopCount = fst->getStartTime(); - } else if (stop_time.end) + } else if (stop_time.end) stopCount = fst->getEndTime(); else { stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale()); @@ -1621,7 +1621,7 @@ struct SimWorker : SimShared bool initial = true; int cycle = 0; log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString()); - if (cycles_set) + if (cycles_set) log(" for %d clock cycle(s)",numcycles); log("\n"); bool all_samples = fst_clock.empty(); @@ -1839,9 +1839,9 @@ struct SimWorker : SimShared std::getline(f, line); if (line.size()==0) continue; - if (line[0]=='#' || line[0]=='@' || line[0]=='.') { + if (line[0]=='#' || line[0]=='@' || line[0]=='.') { if (line[0]!='.') - curr_cycle = atoi(line.c_str()+1); + curr_cycle = atoi(line.c_str()+1); else curr_cycle = -1; // force detect change @@ -1907,7 +1907,7 @@ struct SimWorker : SimShared log_error("Cell %s not present in module %s\n",escaped_s.unescape(),topmod); if (!c->is_mem_cell()) log_error("Cell %s is not memory cell in module %s\n",escaped_s.unescape(),topmod); - + Const addr = Const::from_string(parts[1].substr(1,parts[1].size()-2)); Const data = Const::from_string(parts[2]); top->set_memory_state(c->parameters.at(ID::MEMID).decode_string(), addr, data); @@ -2252,7 +2252,7 @@ struct SimWorker : SimShared if (start_time.time < fst->getStartTime()) log_warning("Start time is before simulation file start time\n"); startCount = fst->getStartTime(); - } else if (start_time.end) + } else if (start_time.end) startCount = fst->getEndTime(); else { startCount = start_time.time * pow10(start_time.scale - fst->getScale()); @@ -2265,7 +2265,7 @@ struct SimWorker : SimShared if (stop_time.time < fst->getStartTime()) log_warning("Stop time is before simulation file start time\n"); stopCount = fst->getStartTime(); - } else if (stop_time.end) + } else if (stop_time.end) stopCount = fst->getEndTime(); else { stopCount = stop_time.time * pow10(stop_time.scale - fst->getScale()); @@ -2280,7 +2280,7 @@ struct SimWorker : SimShared int cycle = 0; log("Generate testbench data from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString()); - if (cycles_set) + if (cycles_set) log(" for %d clock cycle(s)",numcycles); log("\n"); @@ -2351,22 +2351,22 @@ struct SimWorker : SimShared f << initstate.str(); f << stringf("\t\t$readmemb(\"%s.txt\", data);\n",tb_filename); - f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1); - f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1); + f << stringf("\t\t#(data[0][%d:%d]);\n", data_len-32, data_len-1); + f << stringf("\t\t{%s } = data[0][%d:%d];\n", signal_list(clocks), 0, clk_len-1); f << stringf("\t\t{%s } <= data[0][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1); f << stringf("\t\tfor (i = 1; i < %d; i++) begin\n",cycle); - f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1); - f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1); + f << stringf("\t\t\t#(data[i][%d:%d]);\n", data_len-32, data_len-1); + f << stringf("\t\t\t{%s } = data[i][%d:%d];\n", signal_list(clocks), 0, clk_len-1); f << stringf("\t\t\t{%s } <= data[i][%d:%d];\n", signal_list(inputs), clk_len, clk_len+inputs_len-1); - + f << stringf("\t\t\tif ({%s } != data[i-1][%d:%d]) begin\n", signal_list(outputs), clk_len+inputs_len, clk_len+inputs_len+outputs_len-1); f << "\t\t\t\t$error(\"Signal difference detected\\n\");\n"; f << "\t\t\tend\n"; - + f << "\t\tend\n"; - + f << "\t\t$finish;\n"; f << "\tend\n"; f << "endmodule\n"; @@ -2483,7 +2483,7 @@ struct FSTWriter : public OutputWriter fstWriterSetPackType(fstfile, FST_WR_PT_FASTLZ); fstWriterSetRepackOnClose(fstfile, 1); - + worker->top->write_output_header( [this](IdString name) { fstWriterSetScope(fstfile, FST_ST_VCD_MODULE, stringf("%s",name.unescape()).c_str(), nullptr); }, [this]() { fstWriterSetUpscope(fstfile); }, @@ -2632,7 +2632,7 @@ struct AIWWriter : public OutputWriter aiwfile << '0'; } aiwfile << '\n'; - } + } } std::ofstream aiwfile; @@ -3038,7 +3038,7 @@ struct Fst2TbPass : public Pass { log("\n"); log(" -n \n"); log(" number of clock cycles to simulate (default: 20)\n"); - log("\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index a54eef199..70748271e 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -159,7 +159,7 @@ void SynthPropWorker::run() if (tracing_data[module].names.size() == 0) return; if (!reset_name.empty()) { - int width = tracing_data[module].names.size(); + int width = tracing_data[module].names.size(); SigSpec reset = module->wire(reset_name); reset.extend_u0(width, true); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index f7e2b53b5..164033a28 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -398,7 +398,7 @@ struct Abc9Pass : public ScriptPass log_error("Can't handle partially selected module %s!\n", mod); std::string tempdir_name; - if (cleanup) + if (cleanup) tempdir_name = get_base_tmpdir() + "/"; else tempdir_name = "_tmp_"; diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc index 0a312fb77..91e17882f 100644 --- a/passes/techmap/abc_new.cc +++ b/passes/techmap/abc_new.cc @@ -135,7 +135,7 @@ struct AbcNewPass : public ScriptPass { void script() override { if (check_label("check")) { - run("abc9_ops -check"); + run("abc9_ops -check"); } if (check_label("prep_boxes")) { diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 972edc431..fb7084569 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -260,7 +260,7 @@ struct BoothPassWorker { y_sz_revised = y_sz + 1; } else { x_sz_revised = y_sz; - } + } } else { if (x_sz % 2 != 0) { y_sz_revised = x_sz + 1; @@ -804,7 +804,7 @@ struct BoothPassWorker { c_result = c_wire; debug_csa_trees[column_ix].push_back(csa); - csa_ix++; + csa_ix++; if (var_ix <= column_bits.size() - 1) carry_bits_to_sum.append(c_wire); diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index d2755b53e..53f25c341 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -139,7 +139,7 @@ struct DffLegalizePass : public Pass { } // Table of all supported cell types. - // First index in the array is one of the FF_* values, second + // First index in the array is one of the FF_* values, second // index is the set of negative-polarity inputs (OR of NEG_* // values), and the value is the set of supported init values // (OR of INIT_* values). diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index c0e45a70e..02e3c82c6 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -326,12 +326,12 @@ int counter_tryextract( return 24; //Mux should have A driven by count Q, and B by muxy //if A and B are swapped, CE polarity is inverted - if(sigmap(cemux->getPort(ID::B)) == muxy && + if(sigmap(cemux->getPort(ID::B)) == muxy && sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q))) { extract.ce_inverted = false; } - else if(sigmap(cemux->getPort(ID::A)) == muxy && + else if(sigmap(cemux->getPort(ID::A)) == muxy && sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q))) { extract.ce_inverted = true; diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index facf4972f..fe3815cd1 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -652,7 +652,7 @@ LibertyAst *LibertyParser::parse(bool top_level) return NULL; if (tok != 'v') { - report_unexpected_token(tok); + report_unexpected_token(tok); } LibertyAst *ast = new LibertyAst; @@ -662,7 +662,7 @@ LibertyAst *LibertyParser::parse(bool top_level) { tok = lexer(str); - // allow both ';' and new lines to + // allow both ';' and new lines to // terminate a statement. if ((tok == ';') || (tok == 'n')) break; diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 2ddb16d61..e8ea2be05 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -33,7 +33,7 @@ int lut2mux(Cell *cell, bool word_mode) if (GetSize(sig_a) == 1) { if (!word_mode) - cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); + cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); else cell->module->addMux(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y); } @@ -47,11 +47,11 @@ int lut2mux(Cell *cell, bool word_mode) Const lut1 = lut.extract(0, GetSize(lut)/2); Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2); - count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); + count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1), word_mode); count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2), word_mode); if (!word_mode) - cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); + cell->module->addMuxGate(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); else cell->module->addMux(NEW_ID, sig_y1, sig_y2, sig_a_hi, sig_y); } diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 984926be8..1cc95f2c4 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -333,7 +333,7 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - + if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) { c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype)); c->attributes.erase(ID::techmap_chtype); diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v index 2bf958d8f..e15c3f40d 100644 --- a/techlibs/analogdevices/cells_sim.v +++ b/techlibs/analogdevices/cells_sim.v @@ -958,7 +958,7 @@ module RAMD64X1 ( (DPRA2 => DPO) = 147; (DPRA3 => DPO) = 139; (DPRA4 => DPO) = 131; - (DPRA5 => DPO) = 64; + (DPRA5 => DPO) = 64; (posedge WCLK => (SPO : D)) = 761; (posedge WCLK => (DPO : D)) = 733; endspecify @@ -984,7 +984,7 @@ module RAMD64X1 ( (DPRA2 => DPO) = 513; (DPRA3 => DPO) = 505; (DPRA4 => DPO) = 496; - (DPRA5 => DPO) = 199; + (DPRA5 => DPO) = 199; (posedge WCLK => (SPO : D)) = 1798; (posedge WCLK => (DPO : D)) = 1807; endspecify diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index 5d09498f2..aec62a0dc 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -48,8 +48,8 @@ static void fix_carry_chain(Module *module) SigSpec o = cell->getPort(ID(o)); if (GetSize(o) == 2) { SigBit bit_o = o[0]; - ci_bits.insert(bit_ci); - mapping_bits[bit_ci] = bit_o; + ci_bits.insert(bit_ci); + mapping_bits[bit_ci] = bit_o; } } } @@ -64,8 +64,8 @@ static void fix_carry_chain(Module *module) SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b))); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) - continue; - if (bit_i0 == State::S0 && bit_i1== State::S0) + continue; + if (bit_i0 == State::S0 && bit_i1== State::S0) continue; adders_to_fix_cells.push_back(cell); @@ -90,10 +90,10 @@ static void fix_carry_chain(Module *module) c->setPort(ID(b), State::S0); c->setPort(ID(c), State::S0); c->setPort(ID(o), bits); - + cell->setPort(ID(c), new_bit); } - + } struct AnlogicCarryFixPass : public Pass { @@ -110,7 +110,7 @@ struct AnlogicCarryFixPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n"); - + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -123,7 +123,7 @@ struct AnlogicCarryFixPass : public Pass { if (module == nullptr) log_cmd_error("No top module found.\n"); - fix_carry_chain(module); + fix_carry_chain(module); } } AnlogicCarryFixPass; diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index f0cec4909..13d89d003 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -36,7 +36,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); input CI, BI; (* force_downto *) output [Y_WIDTH-1:0] CO; - + wire CIx; (* force_downto *) wire [Y_WIDTH-1:0] COx; @@ -85,7 +85,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); .c(COx[i]), .o({cout, CO[i]}) ); - end: slice + end: slice endgenerate /* End implementation */ diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v index e8ecf4f03..dfddc385a 100644 --- a/techlibs/anlogic/cells_sim.v +++ b/techlibs/anlogic/cells_sim.v @@ -82,7 +82,7 @@ module AL_MAP_LUT1 ( parameter [1:0] INIT = 2'h0; parameter EQN = "(A)"; - assign o = a ? INIT[1] : INIT[0]; + assign o = a ? INIT[1] : INIT[0]; endmodule module AL_MAP_LUT2 ( @@ -94,7 +94,7 @@ module AL_MAP_LUT2 ( parameter EQN = "(A)"; wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0]; - assign o = a ? s1[1] : s1[0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT3 ( @@ -108,7 +108,7 @@ module AL_MAP_LUT3 ( wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0]; wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; - assign o = a ? s1[1] : s1[0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT4 ( @@ -124,7 +124,7 @@ module AL_MAP_LUT4 ( wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0]; wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0]; wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0]; - assign o = a ? s1[1] : s1[0]; + assign o = a ? s1[1] : s1[0]; endmodule module AL_MAP_LUT5 ( @@ -186,6 +186,6 @@ module AL_MAP_ADDER ( "A_LE_B_CARRY": assign o = { a, 1'b0 }; default: assign o = a + b + c; endcase - endgenerate + endgenerate endmodule diff --git a/techlibs/anlogic/eagle_bb.v b/techlibs/anlogic/eagle_bb.v index 7cbec331a..5ad4c7a7c 100644 --- a/techlibs/anlogic/eagle_bb.v +++ b/techlibs/anlogic/eagle_bb.v @@ -44,7 +44,7 @@ endmodule (* blackbox *) module EG_LOGIC_MBOOT( input rebootn, - input [7:0] dynamic_addr + input [7:0] dynamic_addr ); parameter ADDR_SOURCE_SEL = "STATIC"; parameter STATIC_ADDR = 8'b00000000; @@ -242,7 +242,7 @@ module EG_LOGIC_MULT( input rstan, input rstbn, input rstpdn -); +); parameter INPUT_WIDTH_A = 18; parameter INPUT_WIDTH_B = 18; parameter OUTPUT_WIDTH = 36; @@ -561,7 +561,7 @@ module EG_PHY_FIFO( parameter [13:0] F = 14'b01111111110000; parameter [13:0] AEP1 = 14'b00000001110000; parameter [13:0] AFM1 = 14'b01111110000000; - parameter [13:0] FM1 = 14'b01111111100000; + parameter [13:0] FM1 = 14'b01111111100000; parameter [4:0] E = 5'b00000; parameter [5:0] EP1 = 6'b010000; parameter GSR = "ENABLE"; @@ -604,8 +604,8 @@ module EG_PHY_MULT18( input rstbn, input rstpdn, input sourcea, - input sourceb -); + input sourceb +); parameter INPUTREGA = "ENABLE"; parameter INPUTREGB = "ENABLE"; parameter OUTPUTREG = "ENABLE"; @@ -628,7 +628,7 @@ endmodule module EG_PHY_GCLK( input clki, output clko -); +); endmodule (* blackbox *) @@ -647,7 +647,7 @@ module EG_PHY_CLKDIV( input clki, input rst, input rls -); +); parameter GSR = "DISABLE"; parameter DIV = 2; endmodule @@ -677,7 +677,7 @@ module EG_PHY_CONFIG( input dna_shift_en, input mboot_rebootn, input [7:0] mboot_dynamic_addr -); +); parameter MBOOT_AUTO_SEL = "DISABLE"; parameter ADDR_SOURCE_SEL = "STATIC"; parameter STATIC_ADDR = 8'b0; @@ -694,7 +694,7 @@ endmodule module EG_PHY_OSC( input osc_dis, output osc_clk -); +); parameter STDBY = "DISABLE"; endmodule @@ -919,7 +919,7 @@ module EG_PHY_PLL( parameter CLKC3_DIV2_ENABLE = "DISABLE"; parameter CLKC4_DIV2_ENABLE = "DISABLE"; parameter FEEDBK_MODE = "NORMAL"; - parameter FEEDBK_PATH = "VCO_PHASE_0"; + parameter FEEDBK_PATH = "VCO_PHASE_0"; parameter STDBY_ENABLE = "ENABLE"; parameter CLKC0_FPHASE = 0; parameter CLKC1_FPHASE = 0; @@ -992,7 +992,7 @@ module EG_LOGIC_BRAM( parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B; parameter BYTE_ENABLE = 0; parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE; - parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE; + parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE; parameter MODE = "DP"; parameter REGMODE_A = "NOREG"; parameter REGMODE_B = "NOREG"; @@ -1005,7 +1005,7 @@ module EG_LOGIC_BRAM( parameter INIT_FILE = "NONE"; parameter FILL_ALL = "NONE"; parameter IMPLEMENT = "9K"; -endmodule +endmodule (* blackbox *) module EG_PHY_ADC( diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index ca2b3c5cf..4ac03cad4 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -20,8 +20,8 @@ * --- * * Tech-mapping rules for decomposing arbitrarily-sized $mul cells - * into an equivalent collection of smaller `DSP_NAME cells (with the - * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached + * into an equivalent collection of smaller `DSP_NAME cells (with the + * same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached * to $shl and $add cells. * */ diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 3f34bfd22..2f3998f68 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -476,7 +476,7 @@ endmodule //- $sshl (A, B, Y) //* group binary //- -//- An arithmatic shift-left operation. +//- An arithmatic shift-left operation. //- This corresponds to the Verilog '<<<' operator. //- module \$sshl (A, B, Y); @@ -720,7 +720,7 @@ endmodule //- $lt (A, B, Y) //* group binary //- -//- A less-than comparison between inputs 'A' and 'B'. +//- A less-than comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '<' operator. //- module \$lt (A, B, Y); @@ -752,7 +752,7 @@ endmodule //- $le (A, B, Y) //* group binary //- -//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. +//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '<=' operator. //- module \$le (A, B, Y); @@ -784,7 +784,7 @@ endmodule //- $eq (A, B, Y) //* group binary //- -//- An equality comparison between inputs 'A' and 'B'. +//- An equality comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '==' operator. //- module \$eq (A, B, Y); @@ -816,7 +816,7 @@ endmodule //- $ne (A, B, Y) //* group binary //- -//- An inequality comparison between inputs 'A' and 'B'. +//- An inequality comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '!=' operator. //- module \$ne (A, B, Y); @@ -944,7 +944,7 @@ endmodule //- $gt (A, B, Y) //* group binary //- -//- A greater-than comparison between inputs 'A' and 'B'. +//- A greater-than comparison between inputs 'A' and 'B'. //- This corresponds to the Verilog '>' operator. //- module \$gt (A, B, Y); @@ -1477,7 +1477,7 @@ endmodule //- $pow (A, B, Y) //* group binary //- -//- Exponentiation of an input (Y = A ** B). +//- Exponentiation of an input (Y = A ** B). //- This corresponds to the Verilog '**' operator. //- `ifndef SIMLIB_NOPOW @@ -1809,7 +1809,7 @@ endmodule //- //- $tribuf (A, EN, Y) //- -//- A tri-state buffer. +//- A tri-state buffer. //- This buffer conditionally drives the output with the value of the input //- based on the enable signal. //- diff --git a/techlibs/efinix/arith_map.v b/techlibs/efinix/arith_map.v index 6bda0505c..551950980 100644 --- a/techlibs/efinix/arith_map.v +++ b/techlibs/efinix/arith_map.v @@ -36,7 +36,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); input CI, BI; (* force_downto *) output [Y_WIDTH-1:0] CO; - + wire CIx; (* force_downto *) wire [Y_WIDTH-1:0] COx; @@ -73,14 +73,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO); .O(Y[i]), .CO(COx[i]) ); - EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) + EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1)) adder_cout ( .I0(1'b0), .I1(1'b0), .CI(COx[i]), .O(CO[i]) ); - end: slice + end: slice endgenerate /* End implementation */ diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v index 752010f45..23e4420f3 100644 --- a/techlibs/efinix/brams_map.v +++ b/techlibs/efinix/brams_map.v @@ -33,14 +33,14 @@ module $__EFINIX_5K_ (...); PORT_W_WIDTH == 10 ? 9 : 8; - localparam READ_WIDTH = + localparam READ_WIDTH = PORT_R_WIDTH == 1 ? 1 : PORT_R_WIDTH == 2 ? 2 : PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) : PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) : (IS_5BIT ? 20 : 16); - localparam WRITE_WIDTH = + localparam WRITE_WIDTH = PORT_W_WIDTH == 1 ? 1 : PORT_W_WIDTH == 2 ? 2 : PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) : diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index 26e454646..dce4397b1 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -1,5 +1,5 @@ module EFX_LUT4( - output O, + output O, input I0, input I1, input I2, @@ -10,7 +10,7 @@ module EFX_LUT4( wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0]; wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0]; wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; + assign O = I0 ? s1[1] : s1[0]; endmodule module EFX_ADD( @@ -64,9 +64,9 @@ module EFX_FF( initial Q = 1'b0; generate - if (SR_SYNC == 1) + if (SR_SYNC == 1) begin - if (SR_SYNC_PRIORITY == 1) + if (SR_SYNC_PRIORITY == 1) begin always @(posedge clk) if (sr) @@ -93,7 +93,7 @@ module EFX_FF( Q <= SR_VALUE; else if (ce) Q <= d; - + end endgenerate endmodule @@ -108,16 +108,16 @@ module EFX_GBUFCE( wire ce; assign ce = CE_POLARITY ? CE : ~CE; - + assign O = I & ce; - + endmodule module EFX_RAM_5K # ( parameter READ_WIDTH = 20, parameter WRITE_WIDTH = 20, - localparam READ_ADDR_WIDTH = + localparam READ_ADDR_WIDTH = (READ_WIDTH == 16) ? 8 : // 256x16 (READ_WIDTH == 8) ? 9 : // 512x8 (READ_WIDTH == 4) ? 10 : // 1024x4 @@ -126,8 +126,8 @@ module EFX_RAM_5K (READ_WIDTH == 20) ? 8 : // 256x20 (READ_WIDTH == 10) ? 9 : // 512x10 (READ_WIDTH == 5) ? 10 : -1, // 1024x5 - - localparam WRITE_ADDR_WIDTH = + + localparam WRITE_ADDR_WIDTH = (WRITE_WIDTH == 16) ? 8 : // 256x16 (WRITE_WIDTH == 8) ? 9 : // 512x8 (WRITE_WIDTH == 4) ? 10 : // 1024x4 @@ -140,13 +140,13 @@ module EFX_RAM_5K ( input [WRITE_WIDTH-1:0] WDATA, input [WRITE_ADDR_WIDTH-1:0] WADDR, - input WE, + input WE, (* clkbuf_sink *) input WCLK, - input WCLKE, - output [READ_WIDTH-1:0] RDATA, + input WCLKE, + output [READ_WIDTH-1:0] RDATA, input [READ_ADDR_WIDTH-1:0] RADDR, - input RE, + input RE, (* clkbuf_sink *) input RCLK ); diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index 5056dec1a..47432d72c 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -45,12 +45,12 @@ static void fix_carry_chain(Module *module) if (bit_i0 == State::S0 && bit_i1== State::S0) { SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI)); SigBit bit_o = sigmap(cell->getPort(ID::O)); - ci_bits.insert(bit_ci); + ci_bits.insert(bit_ci); mapping_bits[bit_ci] = bit_o; } } } - + vector adders_to_fix_cells; for (auto cell : module->cells()) { @@ -60,8 +60,8 @@ static void fix_carry_chain(Module *module) SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1))); SigBit canonical_bit = sigmap(bit_ci); if (!ci_bits.count(canonical_bit)) - continue; - if (bit_i0 == State::S0 && bit_i1== State::S0) + continue; + if (bit_i0 == State::S0 && bit_i1== State::S0) continue; adders_to_fix_cells.push_back(cell); @@ -83,7 +83,7 @@ static void fix_carry_chain(Module *module) c->setPort(ID(I1), State::S1); c->setPort(ID::CI, State::S0); c->setPort(ID::CO, new_bit); - + cell->setPort(ID::CI, new_bit); } } @@ -102,7 +102,7 @@ struct EfinixCarryFixPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n"); - + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -115,7 +115,7 @@ struct EfinixCarryFixPass : public Pass { if (module == nullptr) log_cmd_error("No top module found.\n"); - fix_carry_chain(module); + fix_carry_chain(module); } } EfinixCarryFixPass; diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v index 0dab9b8fd..d1c493080 100644 --- a/techlibs/fabulous/prims.v +++ b/techlibs/fabulous/prims.v @@ -108,7 +108,7 @@ module FABULOUS_LC #( output Q ); wire f_wire; - + //LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); generate if (K == 1) begin @@ -124,7 +124,7 @@ module FABULOUS_LC #( LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3])); end endgenerate - + LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); assign O = f_wire; @@ -255,15 +255,15 @@ module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label - wire [7:0] A; // port A read data - wire [7:0] B; // port B read data - wire [19:0] C; // port B read data + wire [7:0] A; // port A read data + wire [7:0] B; // port B read data + wire [19:0] C; // port B read data reg [7:0] A_q; // port A read data register reg [7:0] B_q; // port B read data register reg [19:0] C_q; // port B read data register - wire [7:0] OPA; // port A - wire [7:0] OPB; // port B - wire [19:0] OPC; // port B + wire [7:0] OPA; // port A + wire [7:0] OPB; // port B + wire [19:0] OPC; // port B reg [19:0] ACC_data ; // accumulator register wire [19:0] sum;// port B read data register wire [19:0] sum_in;// port B read data register @@ -337,7 +337,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e input W_ADR3; input W_ADR4; input W_en; - + output AD0;// Register File read port A output AD1; output AD2; @@ -359,9 +359,9 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e input B_ADR4; input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) - + // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label - + //type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit //signal mem : memtype := (others => (others => '0')); @@ -377,7 +377,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e reg [3:0] AD_q; // port A read data register reg [3:0] BD_q; // port B read data register - + integer i; assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0}; @@ -385,7 +385,7 @@ module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_e assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0}; assign D = {D3,D2,D1,D0}; - + initial begin for (i=0; i<32; i=i+1) begin mem[i] = 4'b0000; diff --git a/techlibs/fix_mod.py b/techlibs/fix_mod.py index d6406108d..647bb0dfb 100644 --- a/techlibs/fix_mod.py +++ b/techlibs/fix_mod.py @@ -23,7 +23,7 @@ def main(): in_mod = True elif in_mod: decl += line - + if in_mod and decl.rstrip()[-1] == ';': in_mod = False modules[mod] = decl diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index a69f27619..aa1764639 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -211,7 +211,7 @@ struct GatemateFoldInvPass : public Pass { for (Module *module : design->selected_modules()) { FoldInvWorker worker(module); worker(); - } + } } } GatemateFoldInvPass; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 716c212d2..ff94e4c84 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -25,7 +25,7 @@ module LUT3(output F, input I0, I1, I2); (I0 => F) = (1054, 1486); (I1 => F) = (867, 1184); (I2 => F) = (555, 902); - endspecify + endspecify wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; assign F = I0 ? s1[1] : s1[0]; @@ -39,7 +39,7 @@ module LUT4(output F, input I0, I1, I2, I3); (I1 => F) = (1053, 1583); (I2 => F) = (867, 1184); (I3 => F) = (555, 902); - endspecify + endspecify wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; @@ -54,7 +54,7 @@ module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0); (I2 => F) = (995, 1371); (I3 => F) = (808, 1116); (M0 => F) = (486, 680); - endspecify + endspecify endmodule (* abc9_lut=4 *) @@ -66,7 +66,7 @@ module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1); (I3 => F) = (808 + 136, 1116 + 255); (M0 => F) = (486 + 136, 680 + 255); (M1 => F) = (478, 723); - endspecify + endspecify endmodule (* abc9_lut=8 *) @@ -79,7 +79,7 @@ module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2); (M0 => F) = (486 + 136 + 136, 680 + 255 + 255); (M1 => F) = (478 + 136, 723 + 255); (M2 => F) = (478, 723); - endspecify + endspecify endmodule (* abc9_lut=16 *) @@ -93,7 +93,7 @@ module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3); (M1 => F) = (478 + 136 + 136, 723 + 255 + 255); (M2 => F) = (478 + 136, 723 + 255); (M3 => F) = (478, 723); - endspecify + endspecify endmodule module MUX2 (O, I0, I1, S0); @@ -212,7 +212,7 @@ module DFFS (output reg Q, input D, CLK, SET); if (SET) Q <= 1'b1; else - Q <= D; + Q <= D; end endmodule // DFFS (positive clock edge; synchronous set) @@ -388,7 +388,7 @@ endmodule // DFFNE (negative clock edge; clock enable) module DFFNS (output reg Q, input D, CLK, SET); parameter [0:0] INIT = 1'b1; initial Q = INIT; - + specify (negedge CLK => (Q : D)) = (480, 660); $setup(D, negedge CLK, 576); @@ -399,7 +399,7 @@ module DFFNS (output reg Q, input D, CLK, SET); if (SET) Q <= 1'b1; else - Q <= D; + Q <= D; end endmodule // DFFNS (negative clock edge; synchronous set) @@ -485,7 +485,7 @@ endmodule // DFFNP (negative clock edge; asynchronous preset) module DFFNPE (output reg Q, input D, CLK, CE, PRESET); parameter [0:0] INIT = 1'b1; initial Q = INIT; - + specify if (CE) (negedge CLK => (Q : D)) = (480, 660); (PRESET => Q) = (1800, 2679); @@ -793,7 +793,7 @@ module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q); parameter LSREN = "true"; endmodule -module OSER16(D15, D14, D13, D12, D11, D10, +module OSER16(D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q); output Q; @@ -918,7 +918,7 @@ RESET, CALIB, D); parameter LSREN = "true"; endmodule -module IDES16(Q15, Q14, Q13, Q12, Q11, Q10, +module IDES16(Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, RESET, CALIB, D); input D; diff --git a/techlibs/gowin/cells_xtra_gw1n.v b/techlibs/gowin/cells_xtra_gw1n.v index 0ab375ec8..2bf35eb40 100644 --- a/techlibs/gowin/cells_xtra_gw1n.v +++ b/techlibs/gowin/cells_xtra_gw1n.v @@ -36,7 +36,7 @@ endmodule module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); -parameter C_STATIC_DLY = 0; +parameter C_STATIC_DLY = 0; input DI; input SDTAP; input SETN; @@ -47,9 +47,9 @@ endmodule module IEM(D, CLK, RESET, MCLK, LAG, LEAD); -parameter WINSIZE = "SMALL"; -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter WINSIZE = "SMALL"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, CLK, RESET, MCLK; output LAG, LEAD; endmodule @@ -63,10 +63,10 @@ endmodule module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -132,9 +132,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [31:0] DO; @@ -142,11 +142,11 @@ endmodule module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -211,9 +211,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [35:0] DO; @@ -221,9 +221,9 @@ endmodule module pROM(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; -parameter RESET_MODE = "SYNC"; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -289,18 +289,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [31:0] DO; endmodule module pROMX9(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -365,20 +365,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [35:0] DO; endmodule module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 32; -parameter BIT_WIDTH_1 = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -444,8 +444,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSELA, BLKSELB; @@ -454,13 +454,13 @@ endmodule module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 36; -parameter BIT_WIDTH_1 = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -525,8 +525,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [35:0] DI; @@ -535,15 +535,15 @@ endmodule module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 16; -parameter BIT_WIDTH_1 = 16; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -609,9 +609,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [15:0] DIA, DIB; @@ -620,16 +620,16 @@ endmodule module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 18; -parameter BIT_WIDTH_1 = 18; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -694,9 +694,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [17:0] DIA, DIB; input [2:0] BLKSELA, BLKSELB; @@ -712,11 +712,11 @@ input CE,CLK,RESET; input [17:0] SI,SBI; output [17:0] SO,SBO; output [17:0] DOUT; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -728,11 +728,11 @@ input CE,CLK,RESET; input [8:0] SI,SBI; output [8:0] SO,SBO; output [8:0] DOUT; -parameter AREG = 1'b0; -parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -752,8 +752,8 @@ parameter OUT_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); @@ -773,7 +773,7 @@ parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); @@ -791,7 +791,7 @@ parameter OUT1_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); @@ -814,9 +814,9 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; -parameter MULTALU36X18_MODE = 0; -parameter C_ADD_SUB = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter MULTALU36X18_MODE = 0; +parameter C_ADD_SUB = 1'b0; endmodule module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); @@ -836,7 +836,7 @@ input ACCLOAD; output [53:0] DOUT; output [54:0] CASO; output [17:0] SOA, SOB; -parameter A0REG = 1'b0; +parameter A0REG = 1'b0; parameter A1REG = 1'b0; parameter B0REG = 1'b0; parameter B1REG = 1'b0; @@ -851,7 +851,7 @@ parameter ACCLOAD_REG1 = 1'b0; parameter BSIGN0_REG = 1'b0; parameter BSIGN1_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; @@ -875,12 +875,12 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; parameter PIPE_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; -parameter MULTALU18X18_MODE = 0; +parameter MULTALU18X18_MODE = 0; endmodule module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); @@ -891,13 +891,13 @@ input [54:0] CASI; input CLK, CE, RESET; output [53:0] DOUT; output [54:0] CASO; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; @@ -918,41 +918,41 @@ endmodule module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3); input CLKIN; input CLKFB; -input RESET; -input RESET_P; +input RESET; +input RESET_P; input RESET_I; input RESET_S; -input [5:0] FBDSEL; +input [5:0] FBDSEL; input [5:0] IDSEL; input [5:0] ODSEL; -input [3:0] PSDA,FDLY; +input [3:0] PSDA,FDLY; input [3:0] DUTYDA; output CLKOUT; output LOCK; output CLKOUTP; output CLKOUTD; output CLKOUTD3; -parameter FCLKIN = "100.0"; +parameter FCLKIN = "100.0"; parameter DYN_IDIV_SEL= "false"; -parameter IDIV_SEL = 0; +parameter IDIV_SEL = 0; parameter DYN_FBDIV_SEL= "false"; -parameter FBDIV_SEL = 0; +parameter FBDIV_SEL = 0; parameter DYN_ODIV_SEL= "false"; -parameter ODIV_SEL = 8; +parameter ODIV_SEL = 8; parameter PSDA_SEL= "0000"; parameter DYN_DA_EN = "false"; parameter DUTYDA_SEL= "1000"; -parameter CLKOUT_FT_DIR = 1'b1; -parameter CLKOUTP_FT_DIR = 1'b1; -parameter CLKOUT_DLY_STEP = 0; -parameter CLKOUTP_DLY_STEP = 0; -parameter CLKFB_SEL = "internal"; -parameter CLKOUT_BYPASS = "false"; -parameter CLKOUTP_BYPASS = "false"; -parameter CLKOUTD_BYPASS = "false"; -parameter DYN_SDIV_SEL = 2; -parameter CLKOUTD_SRC = "CLKOUT"; -parameter CLKOUTD3_SRC = "CLKOUT"; +parameter CLKOUT_FT_DIR = 1'b1; +parameter CLKOUTP_FT_DIR = 1'b1; +parameter CLKOUT_DLY_STEP = 0; +parameter CLKOUTP_DLY_STEP = 0; +parameter CLKFB_SEL = "internal"; +parameter CLKOUT_BYPASS = "false"; +parameter CLKOUTP_BYPASS = "false"; +parameter CLKOUTD_BYPASS = "false"; +parameter DYN_SDIV_SEL = 2; +parameter CLKOUTD_SRC = "CLKOUT"; +parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW1N-4"; endmodule @@ -1034,8 +1034,8 @@ input HCLKIN; input RESETN; input CALIB; output CLKOUT; -parameter DIV_MODE = "2"; -parameter GSREN = "false"; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; endmodule module DHCEN(CLKIN, CE, CLKOUT); @@ -1049,9 +1049,9 @@ input [7:0] DLLSTEP; input DIR,LOADN,MOVE; output CLKOUT; output FLAG; -parameter DLL_INSEL = 1'b1; -parameter DLY_SIGN = 1'b0; -parameter DLY_ADJ = 0; +parameter DLL_INSEL = 1'b1; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; endmodule module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT); @@ -1084,7 +1084,7 @@ parameter IDLE = 4'd0, PRO_S4 = 4'd9, PRO_S5 = 4'd10, RD_S1 = 4'd11, - RD_S2 = 4'd12; + RD_S2 = 4'd12; endmodule module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); @@ -1113,7 +1113,7 @@ module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; - parameter DCS_MODE = "RISING"; + parameter DCS_MODE = "RISING"; endmodule module DQCE(CLKIN, CE, CLKOUT); @@ -1123,7 +1123,7 @@ output CLKOUT; endmodule module CLKDIV2(HCLKIN, RESETN, CLKOUT); -parameter GSREN = "false"; +parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule @@ -1153,7 +1153,7 @@ parameter IDLE = 4'd0, PRO_S4 = 4'd9, PRO_S5 = 4'd10, RD_S1 = 4'd11, - RD_S2 = 4'd12; + RD_S2 = 4'd12; endmodule module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT); @@ -1175,5 +1175,5 @@ parameter IDLE = 4'd0, PRO_S4 = 4'd9, PRO_S5 = 4'd10, RD_S1 = 4'd11, - RD_S2 = 4'd12; + RD_S2 = 4'd12; endmodule diff --git a/techlibs/gowin/cells_xtra_gw2a.v b/techlibs/gowin/cells_xtra_gw2a.v index 643723db6..404a3e502 100644 --- a/techlibs/gowin/cells_xtra_gw2a.v +++ b/techlibs/gowin/cells_xtra_gw2a.v @@ -36,8 +36,8 @@ endmodule module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, ICLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -47,10 +47,10 @@ endmodule module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter GSREN = "false"; +parameter LSREN = "true"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1; input TX, PCLK, TCLK, RESET; output Q0, Q1; @@ -58,8 +58,8 @@ endmodule module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3); -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -69,8 +69,8 @@ endmodule module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, ICLK, FCLK, PCLK; input [2:0] WADDR; input [2:0] RADDR; @@ -80,11 +80,11 @@ endmodule module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter GSREN = "false"; +parameter LSREN = "true"; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3; input TX0, TX1; input PCLK, FCLK, TCLK, RESET; @@ -93,11 +93,11 @@ endmodule module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter GSREN = "false"; -parameter LSREN = "true"; -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter GSREN = "false"; +parameter LSREN = "true"; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3, D4, D5, D6, D7; input TX0, TX1, TX2, TX3; input PCLK, FCLK, TCLK, RESET; @@ -106,7 +106,7 @@ endmodule module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO); -parameter C_STATIC_DLY = 0; +parameter C_STATIC_DLY = 0; input DI; input SDTAP; input SETN; @@ -117,9 +117,9 @@ endmodule module IEM(D, CLK, RESET, MCLK, LAG, LEAD); -parameter WINSIZE = "SMALL"; -parameter GSREN = "false"; -parameter LSREN = "true"; +parameter WINSIZE = "SMALL"; +parameter GSREN = "false"; +parameter LSREN = "true"; input D, CLK, RESET, MCLK; output LAG, LEAD; endmodule @@ -133,10 +133,10 @@ endmodule module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -202,9 +202,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [31:0] DO; @@ -212,11 +212,11 @@ endmodule module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; parameter BLK_SEL = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -281,9 +281,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; -input WRE; +input OCE; +input RESET; +input WRE; input [13:0] AD; input [2:0] BLKSEL; output [35:0] DO; @@ -291,9 +291,9 @@ endmodule module pROM(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; -parameter RESET_MODE = "SYNC"; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -359,18 +359,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [31:0] DO; endmodule module pROMX9(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -435,20 +435,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [35:0] DO; endmodule module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 32; -parameter BIT_WIDTH_1 = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -514,8 +514,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSELA, BLKSELB; @@ -524,13 +524,13 @@ endmodule module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 36; -parameter BIT_WIDTH_1 = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -595,8 +595,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESETA, RESETB; +input OCE; +input RESETA, RESETB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [35:0] DI; @@ -605,15 +605,15 @@ endmodule module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 16; -parameter BIT_WIDTH_1 = 16; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -679,9 +679,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [15:0] DIA, DIB; @@ -690,16 +690,16 @@ endmodule module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 18; -parameter BIT_WIDTH_1 = 18; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -764,9 +764,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [17:0] DIA, DIB; input [2:0] BLKSELA, BLKSELB; @@ -782,11 +782,11 @@ input CE,CLK,RESET; input [17:0] SI,SBI; output [17:0] SO,SBO; output [17:0] DOUT; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -798,11 +798,11 @@ input CE,CLK,RESET; input [8:0] SI,SBI; output [8:0] SO,SBO; output [8:0] DOUT; -parameter AREG = 1'b0; -parameter BREG = 1'b0; -parameter ADD_SUB = 1'b0; -parameter PADD_RESET_MODE = "SYNC"; -parameter BSEL_MODE = 1'b1; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; parameter SOREG = 1'b0; endmodule @@ -822,8 +822,8 @@ parameter OUT_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB); @@ -843,7 +843,7 @@ parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT); @@ -861,7 +861,7 @@ parameter OUT1_REG = 1'b0; parameter PIPE_REG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; endmodule module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO); @@ -884,9 +884,9 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; -parameter MULTALU36X18_MODE = 0; -parameter C_ADD_SUB = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter MULTALU36X18_MODE = 0; +parameter C_ADD_SUB = 1'b0; endmodule module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB); @@ -906,7 +906,7 @@ input ACCLOAD; output [53:0] DOUT; output [54:0] CASO; output [17:0] SOA, SOB; -parameter A0REG = 1'b0; +parameter A0REG = 1'b0; parameter A1REG = 1'b0; parameter B0REG = 1'b0; parameter B1REG = 1'b0; @@ -921,7 +921,7 @@ parameter ACCLOAD_REG1 = 1'b0; parameter BSIGN0_REG = 1'b0; parameter BSIGN1_REG = 1'b0; parameter SOA_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter MULTADDALU18X18_MODE = 0; parameter MULT_RESET_MODE = "SYNC"; @@ -945,12 +945,12 @@ parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG0 = 1'b0; parameter ACCLOAD_REG1 = 1'b0; -parameter MULT_RESET_MODE = "SYNC"; +parameter MULT_RESET_MODE = "SYNC"; parameter PIPE_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; -parameter MULTALU18X18_MODE = 0; +parameter MULTALU18X18_MODE = 0; endmodule module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO); @@ -961,13 +961,13 @@ input [54:0] CASI; input CLK, CE, RESET; output [53:0] DOUT; output [54:0] CASO; -parameter AREG = 1'b0; +parameter AREG = 1'b0; parameter BREG = 1'b0; parameter ASIGN_REG = 1'b0; parameter BSIGN_REG = 1'b0; parameter ACCLOAD_REG = 1'b0; parameter OUT_REG = 1'b0; -parameter B_ADD_SUB = 1'b0; +parameter B_ADD_SUB = 1'b0; parameter C_ADD_SUB = 1'b0; parameter ALUD_MODE = 0; parameter ALU_RESET_MODE = "SYNC"; @@ -1002,27 +1002,27 @@ output LOCK; output CLKOUTP; output CLKOUTD; output CLKOUTD3; -parameter FCLKIN = "100.0"; +parameter FCLKIN = "100.0"; parameter DYN_IDIV_SEL= "false"; -parameter IDIV_SEL = 0; +parameter IDIV_SEL = 0; parameter DYN_FBDIV_SEL= "false"; -parameter FBDIV_SEL = 0; +parameter FBDIV_SEL = 0; parameter DYN_ODIV_SEL= "false"; -parameter ODIV_SEL = 8; +parameter ODIV_SEL = 8; parameter PSDA_SEL= "0000"; parameter DYN_DA_EN = "false"; parameter DUTYDA_SEL= "1000"; -parameter CLKOUT_FT_DIR = 1'b1; -parameter CLKOUTP_FT_DIR = 1'b1; -parameter CLKOUT_DLY_STEP = 0; -parameter CLKOUTP_DLY_STEP = 0; -parameter CLKFB_SEL = "internal"; -parameter CLKOUT_BYPASS = "false"; -parameter CLKOUTP_BYPASS = "false"; -parameter CLKOUTD_BYPASS = "false"; -parameter DYN_SDIV_SEL = 2; -parameter CLKOUTD_SRC = "CLKOUT"; -parameter CLKOUTD3_SRC = "CLKOUT"; +parameter CLKOUT_FT_DIR = 1'b1; +parameter CLKOUTP_FT_DIR = 1'b1; +parameter CLKOUT_DLY_STEP = 0; +parameter CLKOUTP_DLY_STEP = 0; +parameter CLKFB_SEL = "internal"; +parameter CLKOUT_BYPASS = "false"; +parameter CLKOUTP_BYPASS = "false"; +parameter CLKOUTD_BYPASS = "false"; +parameter DYN_SDIV_SEL = 2; +parameter CLKOUTD_SRC = "CLKOUT"; +parameter CLKOUTD3_SRC = "CLKOUT"; parameter DEVICE = "GW2A-18"; endmodule @@ -1063,8 +1063,8 @@ input HCLKIN; input RESETN; input CALIB; output CLKOUT; -parameter DIV_MODE = "2"; -parameter GSREN = "false"; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; endmodule module DHCEN(CLKIN, CE, CLKOUT); @@ -1080,14 +1080,14 @@ input [2:0] RCLKSEL; input [7:0] DLLSTEP; input [7:0] WSTEP; input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD; -output DQSR90, DQSW0, DQSW270; +output DQSR90, DQSW0, DQSW270; output [2:0] RPOINT, WPOINT; output RVALID,RBURST, RFLAG, WFLAG; - parameter FIFO_MODE_SEL = 1'b0; - parameter RD_PNTR = 3'b000; - parameter DQS_MODE = "X1"; - parameter HWL = "false"; - parameter GSREN = "false"; + parameter FIFO_MODE_SEL = 1'b0; + parameter RD_PNTR = 3'b000; + parameter DQS_MODE = "X1"; + parameter HWL = "false"; + parameter GSREN = "false"; endmodule module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG); @@ -1096,16 +1096,16 @@ input [7:0] DLLSTEP; input DIR,LOADN,MOVE; output CLKOUT; output FLAG; -parameter DLL_INSEL = 1'b1; -parameter DLY_SIGN = 1'b0; -parameter DLY_ADJ = 0; +parameter DLL_INSEL = 1'b1; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; endmodule module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT); input CLK0, CLK1, CLK2, CLK3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; - parameter DCS_MODE = "RISING"; + parameter DCS_MODE = "RISING"; endmodule module DQCE(CLKIN, CE, CLKOUT); @@ -1115,7 +1115,7 @@ output CLKOUT; endmodule module CLKDIV2(HCLKIN, RESETN, CLKOUT); -parameter GSREN = "false"; +parameter GSREN = "false"; input HCLKIN, RESETN; output CLKOUT; endmodule diff --git a/techlibs/gowin/cells_xtra_gw5a.v b/techlibs/gowin/cells_xtra_gw5a.v index ba85e928f..a06c4f936 100644 --- a/techlibs/gowin/cells_xtra_gw5a.v +++ b/techlibs/gowin/cells_xtra_gw5a.v @@ -120,12 +120,12 @@ input OEN, OENB, MODESEL, VCOME; endmodule module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, BLKSELA, BLKSELB, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 32; -parameter BIT_WIDTH_1 = 32; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -191,8 +191,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] ADA, ADB; input [31:0] DI; input [2:0] BLKSELA, BLKSELB; @@ -201,13 +201,13 @@ endmodule module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, BLKSELA, BLKSELB, DI, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH_0 = 36; -parameter BIT_WIDTH_1 = 36; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -272,8 +272,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [35:0] DI; @@ -282,15 +282,15 @@ endmodule module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 16; -parameter BIT_WIDTH_1 = 16; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -356,9 +356,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [2:0] BLKSELA, BLKSELB; input [15:0] DIA, DIB; @@ -367,16 +367,16 @@ endmodule module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB); -parameter READ_MODE0 = 1'b0; -parameter READ_MODE1 = 1'b0; -parameter WRITE_MODE0 = 2'b00; -parameter WRITE_MODE1 = 2'b00; -parameter BIT_WIDTH_0 = 18; -parameter BIT_WIDTH_1 = 18; +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; parameter BLK_SEL_0 = 3'b000; parameter BLK_SEL_1 = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -441,9 +441,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCEA, OCEB; -input RESETA, RESETB; -input WREA, WREB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; input [13:0] ADA, ADB; input [17:0] DIA, DIB; input [2:0] BLKSELA, BLKSELB; @@ -452,9 +452,9 @@ endmodule module pROM(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 32; -parameter RESET_MODE = "SYNC"; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -520,18 +520,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [31:0] DO; endmodule module pROMX9(CLK, CE, OCE, RESET, AD, DO); -parameter READ_MODE = 1'b0; -parameter BIT_WIDTH = 36; -parameter RESET_MODE = "SYNC"; -parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; @@ -596,21 +596,21 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000 parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; input CLK, CE; -input OCE; -input RESET; +input OCE; +input RESET; input [13:0] AD; output [35:0] DO; endmodule module SDP36KE(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, DIP, BLKSELA, BLKSELB, DECCI, SECCI, DO, DOP, DECCO, SECCO, ECCP); -parameter ECC_WRITE_EN="TRUE"; -parameter ECC_READ_EN="TRUE"; -parameter READ_MODE = 1'b0; +parameter ECC_WRITE_EN="TRUE"; +parameter ECC_READ_EN="TRUE"; +parameter READ_MODE = 1'b0; parameter BLK_SEL_A = 3'b000; parameter BLK_SEL_B = 3'b000; -parameter RESET_MODE = "SYNC"; -parameter INIT_FILE = "NONE"; +parameter RESET_MODE = "SYNC"; +parameter INIT_FILE = "NONE"; parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -756,8 +756,8 @@ parameter INITP_RAM_0D = 256'h00000000000000000000000000000000000000000000000000 parameter INITP_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; input CLKA, CEA, CLKB, CEB; -input OCE; -input RESET; +input OCE; +input RESET; input [8:0] ADA, ADB; input [63:0] DI; input [7:0] DIP; @@ -779,52 +779,52 @@ output [67:0] DO; endmodule module MULTADDALU12X12(DOUT, CASO, A0, B0, A1, B1, CASI, ACCSEL, CASISEL, ADDSUB, CLK, CE, RESET); -parameter A0REG_CLK = "BYPASS"; -parameter A0REG_CE = "CE0"; -parameter A0REG_RESET = "RESET0"; -parameter A1REG_CLK = "BYPASS"; -parameter A1REG_CE = "CE0"; -parameter A1REG_RESET = "RESET0"; -parameter B0REG_CLK = "BYPASS"; -parameter B0REG_CE = "CE0"; -parameter B0REG_RESET = "RESET0"; -parameter B1REG_CLK = "BYPASS"; -parameter B1REG_CE = "CE0"; -parameter B1REG_RESET = "RESET0"; -parameter ACCSEL_IREG_CLK = "BYPASS"; -parameter ACCSEL_IREG_CE = "CE0"; -parameter ACCSEL_IREG_RESET = "RESET0"; -parameter CASISEL_IREG_CLK = "BYPASS"; -parameter CASISEL_IREG_CE = "CE0"; -parameter CASISEL_IREG_RESET = "RESET0"; -parameter ADDSUB0_IREG_CLK = "BYPASS"; -parameter ADDSUB0_IREG_CE = "CE0"; -parameter ADDSUB0_IREG_RESET = "RESET0"; -parameter ADDSUB1_IREG_CLK = "BYPASS"; -parameter ADDSUB1_IREG_CE = "CE0"; -parameter ADDSUB1_IREG_RESET = "RESET0"; -parameter PREG0_CLK = "BYPASS"; -parameter PREG0_CE = "CE0"; -parameter PREG0_RESET = "RESET0"; -parameter PREG1_CLK = "BYPASS"; -parameter PREG1_CE = "CE0"; -parameter PREG1_RESET = "RESET0"; -parameter FB_PREG_EN = "FALSE"; -parameter ACCSEL_PREG_CLK = "BYPASS"; -parameter ACCSEL_PREG_CE = "CE0"; -parameter ACCSEL_PREG_RESET = "RESET0"; -parameter CASISEL_PREG_CLK = "BYPASS"; -parameter CASISEL_PREG_CE = "CE0"; -parameter CASISEL_PREG_RESET = "RESET0"; -parameter ADDSUB0_PREG_CLK = "BYPASS"; -parameter ADDSUB0_PREG_CE = "CE0"; -parameter ADDSUB0_PREG_RESET = "RESET0"; -parameter ADDSUB1_PREG_CLK = "BYPASS"; -parameter ADDSUB1_PREG_CE = "CE0"; -parameter ADDSUB1_PREG_RESET = "RESET0"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter A0REG_CLK = "BYPASS"; +parameter A0REG_CE = "CE0"; +parameter A0REG_RESET = "RESET0"; +parameter A1REG_CLK = "BYPASS"; +parameter A1REG_CE = "CE0"; +parameter A1REG_RESET = "RESET0"; +parameter B0REG_CLK = "BYPASS"; +parameter B0REG_CE = "CE0"; +parameter B0REG_RESET = "RESET0"; +parameter B1REG_CLK = "BYPASS"; +parameter B1REG_CE = "CE0"; +parameter B1REG_RESET = "RESET0"; +parameter ACCSEL_IREG_CLK = "BYPASS"; +parameter ACCSEL_IREG_CE = "CE0"; +parameter ACCSEL_IREG_RESET = "RESET0"; +parameter CASISEL_IREG_CLK = "BYPASS"; +parameter CASISEL_IREG_CE = "CE0"; +parameter CASISEL_IREG_RESET = "RESET0"; +parameter ADDSUB0_IREG_CLK = "BYPASS"; +parameter ADDSUB0_IREG_CE = "CE0"; +parameter ADDSUB0_IREG_RESET = "RESET0"; +parameter ADDSUB1_IREG_CLK = "BYPASS"; +parameter ADDSUB1_IREG_CE = "CE0"; +parameter ADDSUB1_IREG_RESET = "RESET0"; +parameter PREG0_CLK = "BYPASS"; +parameter PREG0_CE = "CE0"; +parameter PREG0_RESET = "RESET0"; +parameter PREG1_CLK = "BYPASS"; +parameter PREG1_CE = "CE0"; +parameter PREG1_RESET = "RESET0"; +parameter FB_PREG_EN = "FALSE"; +parameter ACCSEL_PREG_CLK = "BYPASS"; +parameter ACCSEL_PREG_CE = "CE0"; +parameter ACCSEL_PREG_RESET = "RESET0"; +parameter CASISEL_PREG_CLK = "BYPASS"; +parameter CASISEL_PREG_CE = "CE0"; +parameter CASISEL_PREG_RESET = "RESET0"; +parameter ADDSUB0_PREG_CLK = "BYPASS"; +parameter ADDSUB0_PREG_CE = "CE0"; +parameter ADDSUB0_PREG_RESET = "RESET0"; +parameter ADDSUB1_PREG_CLK = "BYPASS"; +parameter ADDSUB1_PREG_CE = "CE0"; +parameter ADDSUB1_PREG_RESET = "RESET0"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; parameter PRE_LOAD = 48'h000000000000; parameter DYN_ADD_SUB_0 = "FALSE"; @@ -845,65 +845,65 @@ input [1:0] CLK, CE, RESET; endmodule module MULTALU27X18(DOUT, CASO, SOA, A, SIA, B, C, D, CASI, ACCSEL, PSEL, ASEL, PADDSUB, CSEL, CASISEL, ADDSUB, CLK, CE, RESET); -parameter AREG_CLK = "BYPASS"; -parameter AREG_CE = "CE0"; -parameter AREG_RESET = "RESET0"; -parameter BREG_CLK = "BYPASS"; -parameter BREG_CE = "CE0"; -parameter BREG_RESET = "RESET0"; -parameter DREG_CLK = "BYPASS"; -parameter DREG_CE = "CE0"; -parameter DREG_RESET = "RESET0"; -parameter C_IREG_CLK = "BYPASS"; -parameter C_IREG_CE = "CE0"; -parameter C_IREG_RESET = "RESET0"; -parameter PSEL_IREG_CLK = "BYPASS"; -parameter PSEL_IREG_CE = "CE0"; -parameter PSEL_IREG_RESET = "RESET0"; -parameter PADDSUB_IREG_CLK = "BYPASS"; -parameter PADDSUB_IREG_CE = "CE0"; -parameter PADDSUB_IREG_RESET = "RESET0"; -parameter ADDSUB0_IREG_CLK = "BYPASS"; -parameter ADDSUB0_IREG_CE = "CE0"; -parameter ADDSUB0_IREG_RESET = "RESET0"; -parameter ADDSUB1_IREG_CLK = "BYPASS"; -parameter ADDSUB1_IREG_CE = "CE0"; -parameter ADDSUB1_IREG_RESET = "RESET0"; -parameter CSEL_IREG_CLK = "BYPASS"; -parameter CSEL_IREG_CE = "CE0"; -parameter CSEL_IREG_RESET = "RESET0"; -parameter CASISEL_IREG_CLK = "BYPASS"; -parameter CASISEL_IREG_CE = "CE0"; -parameter CASISEL_IREG_RESET = "RESET0"; -parameter ACCSEL_IREG_CLK = "BYPASS"; -parameter ACCSEL_IREG_CE = "CE0"; -parameter ACCSEL_IREG_RESET = "RESET0"; -parameter PREG_CLK = "BYPASS"; -parameter PREG_CE = "CE0"; -parameter PREG_RESET = "RESET0"; -parameter ADDSUB0_PREG_CLK = "BYPASS"; -parameter ADDSUB0_PREG_CE = "CE0"; -parameter ADDSUB0_PREG_RESET = "RESET0"; -parameter ADDSUB1_PREG_CLK = "BYPASS"; -parameter ADDSUB1_PREG_CE = "CE0"; -parameter ADDSUB1_PREG_RESET = "RESET0"; -parameter CSEL_PREG_CLK = "BYPASS"; -parameter CSEL_PREG_CE = "CE0"; -parameter CSEL_PREG_RESET = "RESET0"; -parameter CASISEL_PREG_CLK = "BYPASS"; -parameter CASISEL_PREG_CE = "CE0"; -parameter CASISEL_PREG_RESET = "RESET0"; -parameter ACCSEL_PREG_CLK = "BYPASS"; -parameter ACCSEL_PREG_CE = "CE0"; -parameter ACCSEL_PREG_RESET = "RESET0"; -parameter C_PREG_CLK = "BYPASS"; -parameter C_PREG_CE = "CE0"; -parameter C_PREG_RESET = "RESET0"; -parameter FB_PREG_EN = "FALSE"; -parameter SOA_PREG_EN = "FALSE"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter AREG_CLK = "BYPASS"; +parameter AREG_CE = "CE0"; +parameter AREG_RESET = "RESET0"; +parameter BREG_CLK = "BYPASS"; +parameter BREG_CE = "CE0"; +parameter BREG_RESET = "RESET0"; +parameter DREG_CLK = "BYPASS"; +parameter DREG_CE = "CE0"; +parameter DREG_RESET = "RESET0"; +parameter C_IREG_CLK = "BYPASS"; +parameter C_IREG_CE = "CE0"; +parameter C_IREG_RESET = "RESET0"; +parameter PSEL_IREG_CLK = "BYPASS"; +parameter PSEL_IREG_CE = "CE0"; +parameter PSEL_IREG_RESET = "RESET0"; +parameter PADDSUB_IREG_CLK = "BYPASS"; +parameter PADDSUB_IREG_CE = "CE0"; +parameter PADDSUB_IREG_RESET = "RESET0"; +parameter ADDSUB0_IREG_CLK = "BYPASS"; +parameter ADDSUB0_IREG_CE = "CE0"; +parameter ADDSUB0_IREG_RESET = "RESET0"; +parameter ADDSUB1_IREG_CLK = "BYPASS"; +parameter ADDSUB1_IREG_CE = "CE0"; +parameter ADDSUB1_IREG_RESET = "RESET0"; +parameter CSEL_IREG_CLK = "BYPASS"; +parameter CSEL_IREG_CE = "CE0"; +parameter CSEL_IREG_RESET = "RESET0"; +parameter CASISEL_IREG_CLK = "BYPASS"; +parameter CASISEL_IREG_CE = "CE0"; +parameter CASISEL_IREG_RESET = "RESET0"; +parameter ACCSEL_IREG_CLK = "BYPASS"; +parameter ACCSEL_IREG_CE = "CE0"; +parameter ACCSEL_IREG_RESET = "RESET0"; +parameter PREG_CLK = "BYPASS"; +parameter PREG_CE = "CE0"; +parameter PREG_RESET = "RESET0"; +parameter ADDSUB0_PREG_CLK = "BYPASS"; +parameter ADDSUB0_PREG_CE = "CE0"; +parameter ADDSUB0_PREG_RESET = "RESET0"; +parameter ADDSUB1_PREG_CLK = "BYPASS"; +parameter ADDSUB1_PREG_CE = "CE0"; +parameter ADDSUB1_PREG_RESET = "RESET0"; +parameter CSEL_PREG_CLK = "BYPASS"; +parameter CSEL_PREG_CE = "CE0"; +parameter CSEL_PREG_RESET = "RESET0"; +parameter CASISEL_PREG_CLK = "BYPASS"; +parameter CASISEL_PREG_CE = "CE0"; +parameter CASISEL_PREG_RESET = "RESET0"; +parameter ACCSEL_PREG_CLK = "BYPASS"; +parameter ACCSEL_PREG_CE = "CE0"; +parameter ACCSEL_PREG_RESET = "RESET0"; +parameter C_PREG_CLK = "BYPASS"; +parameter C_PREG_CE = "CE0"; +parameter C_PREG_RESET = "RESET0"; +parameter FB_PREG_EN = "FALSE"; +parameter SOA_PREG_EN = "FALSE"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; parameter PRE_LOAD = 48'h000000000000; parameter DYN_P_SEL = "FALSE"; @@ -940,18 +940,18 @@ input [1:0] CLK, CE, RESET; endmodule module MULT12X12(DOUT, A, B, CLK, CE, RESET); -parameter AREG_CLK = "BYPASS"; -parameter AREG_CE = "CE0"; -parameter AREG_RESET = "RESET0"; -parameter BREG_CLK = "BYPASS"; -parameter BREG_CE = "CE0"; -parameter BREG_RESET = "RESET0"; -parameter PREG_CLK = "BYPASS"; -parameter PREG_CE = "CE0"; -parameter PREG_RESET = "RESET0"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter AREG_CLK = "BYPASS"; +parameter AREG_CE = "CE0"; +parameter AREG_RESET = "RESET0"; +parameter BREG_CLK = "BYPASS"; +parameter BREG_CE = "CE0"; +parameter BREG_RESET = "RESET0"; +parameter PREG_CLK = "BYPASS"; +parameter PREG_CE = "CE0"; +parameter PREG_RESET = "RESET0"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; output [23:0] DOUT; input [11:0] A, B; @@ -959,27 +959,27 @@ input [1:0] CLK, CE, RESET; endmodule module MULT27X36(DOUT, A, B, D, CLK, CE, RESET, PSEL, PADDSUB); -parameter AREG_CLK = "BYPASS"; -parameter AREG_CE = "CE0"; -parameter AREG_RESET = "RESET0"; -parameter BREG_CLK = "BYPASS"; -parameter BREG_CE = "CE0"; -parameter BREG_RESET = "RESET0"; -parameter DREG_CLK = "BYPASS"; -parameter DREG_CE = "CE0"; -parameter DREG_RESET = "RESET0"; -parameter PADDSUB_IREG_CLK = "BYPASS"; -parameter PADDSUB_IREG_CE = "CE0"; -parameter PADDSUB_IREG_RESET = "RESET0"; -parameter PREG_CLK = "BYPASS"; -parameter PREG_CE = "CE0"; -parameter PREG_RESET = "RESET0"; -parameter PSEL_IREG_CLK = "BYPASS"; -parameter PSEL_IREG_CE = "CE0"; -parameter PSEL_IREG_RESET = "RESET0"; -parameter OREG_CLK = "BYPASS"; -parameter OREG_CE = "CE0"; -parameter OREG_RESET = "RESET0"; +parameter AREG_CLK = "BYPASS"; +parameter AREG_CE = "CE0"; +parameter AREG_RESET = "RESET0"; +parameter BREG_CLK = "BYPASS"; +parameter BREG_CE = "CE0"; +parameter BREG_RESET = "RESET0"; +parameter DREG_CLK = "BYPASS"; +parameter DREG_CE = "CE0"; +parameter DREG_RESET = "RESET0"; +parameter PADDSUB_IREG_CLK = "BYPASS"; +parameter PADDSUB_IREG_CE = "CE0"; +parameter PADDSUB_IREG_RESET = "RESET0"; +parameter PREG_CLK = "BYPASS"; +parameter PREG_CE = "CE0"; +parameter PREG_RESET = "RESET0"; +parameter PSEL_IREG_CLK = "BYPASS"; +parameter PSEL_IREG_CE = "CE0"; +parameter PSEL_IREG_RESET = "RESET0"; +parameter OREG_CLK = "BYPASS"; +parameter OREG_CE = "CE0"; +parameter OREG_RESET = "RESET0"; parameter MULT_RESET_MODE = "SYNC"; parameter DYN_P_SEL = "FALSE"; parameter P_SEL = 1'b0; @@ -1002,14 +1002,14 @@ input [9:0] DATAIN0, DATAIN1; input [9:0] DATAIN2; input RSTN; input [23:0] CASI; -parameter COFFIN_WIDTH = 4; -parameter DATAIN_WIDTH = 8; -parameter IREG = 1'b0; -parameter OREG = 1'b0; -parameter PREG = 1'b0; -parameter ACC_EN = "FALSE"; -parameter CASI_EN = "FALSE"; -parameter CASO_EN = "FALSE"; +parameter COFFIN_WIDTH = 4; +parameter DATAIN_WIDTH = 8; +parameter IREG = 1'b0; +parameter OREG = 1'b0; +parameter PREG = 1'b0; +parameter ACC_EN = "FALSE"; +parameter CASI_EN = "FALSE"; +parameter CASO_EN = "FALSE"; endmodule module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1); @@ -1022,8 +1022,8 @@ endmodule module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1); -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1; input TX, PCLK, TCLK, RESET; output Q0, Q1; @@ -1060,9 +1060,9 @@ endmodule module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3; input TX0, TX1; input PCLK, FCLK, TCLK, RESET; @@ -1071,9 +1071,9 @@ endmodule module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1); -parameter HWL = "false"; -parameter TCLK_SOURCE = "DQSW"; -parameter TXCLK_POL = 1'b0; +parameter HWL = "false"; +parameter TCLK_SOURCE = "DQSW"; +parameter TXCLK_POL = 1'b0; input D0, D1, D2, D3, D4, D5, D6, D7; input TX0, TX1, TX2, TX3; input PCLK, FCLK, TCLK, RESET; @@ -1088,7 +1088,7 @@ output Q; endmodule module IODELAY(DI, SDTAP, VALUE, DLYSTEP, DF, DO); -parameter C_STATIC_DLY = 0; +parameter C_STATIC_DLY = 0; parameter DYN_DLY_EN = "FALSE"; parameter ADAPT_EN = "FALSE"; input DI; @@ -1109,10 +1109,10 @@ output DF0, DF1; input SDTAP0, SDTAP1; input VALUE0,VALUE1; input [7:0] DLYSTEP0,DLYSTEP1; -parameter C_STATIC_DLY_0 = 0; +parameter C_STATIC_DLY_0 = 0; parameter DYN_DLY_EN_0 = "FALSE"; parameter ADAPT_EN_0 = "FALSE"; -parameter C_STATIC_DLY_1 = 0; +parameter C_STATIC_DLY_1 = 0; parameter DYN_DLY_EN_1 = "FALSE"; parameter ADAPT_EN_1 = "FALSE"; endmodule @@ -1127,16 +1127,16 @@ output DF0, DF1, DF2, DF3; input SDTAP0, SDTAP1, SDTAP2, SDTAP3; input VALUE0, VALUE1, VALUE2, VALUE3; input [7:0] DLYSTEP0, DLYSTEP1, DLYSTEP2, DLYSTEP3; -parameter C_STATIC_DLY_0 = 0; +parameter C_STATIC_DLY_0 = 0; parameter DYN_DLY_EN_0 = "FALSE"; parameter ADAPT_EN_0 = "FALSE"; -parameter C_STATIC_DLY_1 = 0; +parameter C_STATIC_DLY_1 = 0; parameter DYN_DLY_EN_1 = "FALSE"; parameter ADAPT_EN_1 = "FALSE"; -parameter C_STATIC_DLY_2 = 0; +parameter C_STATIC_DLY_2 = 0; parameter DYN_DLY_EN_2 = "FALSE"; parameter ADAPT_EN_2 = "FALSE"; -parameter C_STATIC_DLY_3 = 0; +parameter C_STATIC_DLY_3 = 0; parameter DYN_DLY_EN_3 = "FALSE"; parameter ADAPT_EN_3 = "FALSE"; endmodule @@ -1151,7 +1151,7 @@ module DCS(CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE, CLKSEL, CLKOUT); input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE; input [3:0] CLKSEL; output CLKOUT; -parameter DCS_MODE = "RISING"; +parameter DCS_MODE = "RISING"; endmodule module DDRDLL(CLKIN, STOP, UPDNCNTL, RESET, STEP, LOCK); @@ -1164,7 +1164,7 @@ output LOCK; parameter DLL_FORCE = "FALSE"; parameter CODESCAL = "000"; parameter SCAL_EN = "TRUE"; -parameter DIV_SEL = 1'b0; +parameter DIV_SEL = 1'b0; endmodule module DLLDLY(CLKIN, DLLSTEP, CSTEP, LOADN, MOVE, CLKOUT, FLAG); @@ -1173,8 +1173,8 @@ input [7:0] DLLSTEP, CSTEP; input LOADN,MOVE; output CLKOUT; output FLAG; -parameter DLY_SIGN = 1'b0; -parameter DLY_ADJ = 0; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; parameter DYN_DLY_EN = "FALSE"; parameter ADAPT_EN = "FALSE"; parameter STEP_SEL = 1'b0; @@ -1185,7 +1185,7 @@ input HCLKIN; input RESETN; input CALIB; output CLKOUT; -parameter DIV_MODE = "2"; +parameter DIV_MODE = "2"; endmodule module CLKDIV2(HCLKIN, RESETN, CLKOUT); @@ -1200,20 +1200,20 @@ output CLKOUT; endmodule module OSCA(OSCOUT, OSCEN); -parameter FREQ_DIV = 100; +parameter FREQ_DIV = 100; output OSCOUT; input OSCEN; endmodule module OSCB(OSCOUT, OSCREF, OSCEN, FMODE, RTRIM, RTCTRIM); -parameter FREQ_MODE = "25"; -parameter FREQ_DIV = 10; -parameter DYN_TRIM_EN = "FALSE"; +parameter FREQ_MODE = "25"; +parameter FREQ_DIV = 10; +parameter DYN_TRIM_EN = "FALSE"; output OSCOUT; output OSCREF; input OSCEN, FMODE; input [7:0] RTRIM; -input [5:0] RTCTRIM; +input [5:0] RTCTRIM; endmodule module PLL(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, FBDSEL, IDSEL, MDSEL, MDSEL_FRAC, ODSEL0, ODSEL0_FRAC, ODSEL1, ODSEL2, ODSEL3, ODSEL4, ODSEL5, ODSEL6, DT0, DT1, DT2 @@ -1264,29 +1264,29 @@ output CLKOUT4; output CLKOUT5; output CLKOUT6; output CLKFBOUT; -parameter FCLKIN = "100.0"; +parameter FCLKIN = "100.0"; parameter DYN_IDIV_SEL= "FALSE"; -parameter IDIV_SEL = 1; +parameter IDIV_SEL = 1; parameter DYN_FBDIV_SEL= "FALSE"; -parameter FBDIV_SEL = 1; +parameter FBDIV_SEL = 1; parameter DYN_ODIV0_SEL= "FALSE"; -parameter ODIV0_SEL = 8; +parameter ODIV0_SEL = 8; parameter DYN_ODIV1_SEL= "FALSE"; -parameter ODIV1_SEL = 8; +parameter ODIV1_SEL = 8; parameter DYN_ODIV2_SEL= "FALSE"; -parameter ODIV2_SEL = 8; +parameter ODIV2_SEL = 8; parameter DYN_ODIV3_SEL= "FALSE"; -parameter ODIV3_SEL = 8; +parameter ODIV3_SEL = 8; parameter DYN_ODIV4_SEL= "FALSE"; -parameter ODIV4_SEL = 8; +parameter ODIV4_SEL = 8; parameter DYN_ODIV5_SEL= "FALSE"; -parameter ODIV5_SEL = 8; +parameter ODIV5_SEL = 8; parameter DYN_ODIV6_SEL= "FALSE"; -parameter ODIV6_SEL = 8; +parameter ODIV6_SEL = 8; parameter DYN_MDIV_SEL= "FALSE"; -parameter MDIV_SEL = 8; -parameter MDIV_FRAC_SEL = 0; -parameter ODIV0_FRAC_SEL = 0; +parameter MDIV_SEL = 8; +parameter MDIV_FRAC_SEL = 0; +parameter ODIV0_FRAC_SEL = 0; parameter CLKOUT0_EN = "TRUE"; parameter CLKOUT1_EN = "FALSE"; parameter CLKOUT2_EN = "FALSE"; @@ -1294,19 +1294,19 @@ parameter CLKOUT3_EN = "FALSE"; parameter CLKOUT4_EN = "FALSE"; parameter CLKOUT5_EN = "FALSE"; parameter CLKOUT6_EN = "FALSE"; -parameter CLKFB_SEL = "INTERNAL"; -parameter DYN_DT0_SEL = "FALSE"; -parameter DYN_DT1_SEL = "FALSE"; -parameter DYN_DT2_SEL = "FALSE"; -parameter DYN_DT3_SEL = "FALSE"; -parameter CLKOUT0_DT_DIR = 1'b1; -parameter CLKOUT1_DT_DIR = 1'b1; -parameter CLKOUT2_DT_DIR = 1'b1; -parameter CLKOUT3_DT_DIR = 1'b1; -parameter CLKOUT0_DT_STEP = 0; -parameter CLKOUT1_DT_STEP = 0; -parameter CLKOUT2_DT_STEP = 0; -parameter CLKOUT3_DT_STEP = 0; +parameter CLKFB_SEL = "INTERNAL"; +parameter DYN_DT0_SEL = "FALSE"; +parameter DYN_DT1_SEL = "FALSE"; +parameter DYN_DT2_SEL = "FALSE"; +parameter DYN_DT3_SEL = "FALSE"; +parameter CLKOUT0_DT_DIR = 1'b1; +parameter CLKOUT1_DT_DIR = 1'b1; +parameter CLKOUT2_DT_DIR = 1'b1; +parameter CLKOUT3_DT_DIR = 1'b1; +parameter CLKOUT0_DT_STEP = 0; +parameter CLKOUT1_DT_STEP = 0; +parameter CLKOUT2_DT_STEP = 0; +parameter CLKOUT3_DT_STEP = 0; parameter CLK0_IN_SEL = 1'b0; parameter CLK0_OUT_SEL = 1'b0; parameter CLK1_IN_SEL = 1'b0; @@ -1389,19 +1389,19 @@ output CLKOUT4; output CLKOUT5; output CLKOUT6; output CLKFBOUT; -parameter FCLKIN = "100.0"; -parameter IDIV_SEL = 1; -parameter FBDIV_SEL = 1; -parameter ODIV0_SEL = 8; -parameter ODIV1_SEL = 8; -parameter ODIV2_SEL = 8; -parameter ODIV3_SEL = 8; -parameter ODIV4_SEL = 8; -parameter ODIV5_SEL = 8; -parameter ODIV6_SEL = 8; -parameter MDIV_SEL = 8; -parameter MDIV_FRAC_SEL = 0; -parameter ODIV0_FRAC_SEL = 0; +parameter FCLKIN = "100.0"; +parameter IDIV_SEL = 1; +parameter FBDIV_SEL = 1; +parameter ODIV0_SEL = 8; +parameter ODIV1_SEL = 8; +parameter ODIV2_SEL = 8; +parameter ODIV3_SEL = 8; +parameter ODIV4_SEL = 8; +parameter ODIV5_SEL = 8; +parameter ODIV6_SEL = 8; +parameter MDIV_SEL = 8; +parameter MDIV_FRAC_SEL = 0; +parameter ODIV0_FRAC_SEL = 0; parameter CLKOUT0_EN = "TRUE"; parameter CLKOUT1_EN = "FALSE"; parameter CLKOUT2_EN = "FALSE"; @@ -1409,15 +1409,15 @@ parameter CLKOUT3_EN = "FALSE"; parameter CLKOUT4_EN = "FALSE"; parameter CLKOUT5_EN = "FALSE"; parameter CLKOUT6_EN = "FALSE"; -parameter CLKFB_SEL = "INTERNAL"; -parameter CLKOUT0_DT_DIR = 1'b1; -parameter CLKOUT1_DT_DIR = 1'b1; -parameter CLKOUT2_DT_DIR = 1'b1; -parameter CLKOUT3_DT_DIR = 1'b1; -parameter CLKOUT0_DT_STEP = 0; -parameter CLKOUT1_DT_STEP = 0; -parameter CLKOUT2_DT_STEP = 0; -parameter CLKOUT3_DT_STEP = 0; +parameter CLKFB_SEL = "INTERNAL"; +parameter CLKOUT0_DT_DIR = 1'b1; +parameter CLKOUT1_DT_DIR = 1'b1; +parameter CLKOUT2_DT_DIR = 1'b1; +parameter CLKOUT3_DT_DIR = 1'b1; +parameter CLKOUT0_DT_STEP = 0; +parameter CLKOUT1_DT_STEP = 0; +parameter CLKOUT2_DT_STEP = 0; +parameter CLKOUT3_DT_STEP = 0; parameter CLK0_IN_SEL = 1'b0; parameter CLK0_OUT_SEL = 1'b0; parameter CLK1_IN_SEL = 1'b0; @@ -1500,8 +1500,8 @@ input [15:0] GP_INT; input [ 7:0] DMA_REQ; output [ 7:0] DMA_ACK; output CORE0_WFI_MODE; -input WAKEUP_IN; -output RTC_WAKEUP; +input WAKEUP_IN; +output RTC_WAKEUP; input TEST_CLK; input TEST_MODE; input TEST_RSTN; @@ -1554,7 +1554,7 @@ output [2:0] DDR_HSIZE; output [1:0] DDR_HTRANS; output [63:0] DDR_HWDATA; output DDR_HWRITE; -input TMS_IN; +input TMS_IN; input TRST_IN; input TDI_IN; output TDO_OUT; @@ -1659,14 +1659,14 @@ input RET2N; endmodule module SAMB(SPIAD, LOAD, ADWSEL); -parameter MODE = 2'b00; +parameter MODE = 2'b00; input [23:0] SPIAD; input LOAD; -input ADWSEL; +input ADWSEL; endmodule module OTP(CLK, READ, SHIFT, DOUT); -parameter MODE = 2'b01; +parameter MODE = 2'b01; input CLK, READ, SHIFT; output DOUT; endmodule @@ -1676,11 +1676,11 @@ output RUNNING; output CRCERR; output CRCDONE; output ECCCORR; -output ECCUNCORR; +output ECCUNCORR; output [27:0] ERRLOC; output ECCDEC; output DSRRD; -output DSRWR; +output DSRWR; output ASRRESET; output ASRINC; output REFCLK; @@ -1695,12 +1695,12 @@ output RUNNING; output CRCERR; output CRCDONE; output ECCCORR; -output ECCUNCORR; +output ECCUNCORR; output [26:0] ERR0LOC; output [26:0] ERR1LOC; output ECCDEC; output DSRRD; -output DSRWR; +output DSRWR; output ASRRESET; output ASRINC; output REFCLK; @@ -1715,11 +1715,11 @@ output RUNNING; output CRCERR; output CRCDONE; output ECCCORR; -output ECCUNCORR; +output ECCUNCORR; output [12:0] ERRLOC; output ECCDEC; output DSRRD; -output DSRWR; +output DSRWR; output ASRRESET; output ASRINC; output REFCLK; @@ -1730,17 +1730,17 @@ input [6:0] ERRINJ0LOC,ERRINJ1LOC; endmodule module SAMBA(SPIAD, LOAD); -parameter MODE = 2'b00; +parameter MODE = 2'b00; input SPIAD; input LOAD; endmodule module LICD(); - parameter STAGE_NUM = 2'b00; - parameter ENCDEC_NUM = 2'b00; - parameter CODE_WIDTH = 2'b00; - parameter INTERLEAVE_EN = 3'b000; - parameter INTERLEAVE_MODE = 3'b000; + parameter STAGE_NUM = 2'b00; + parameter ENCDEC_NUM = 2'b00; + parameter CODE_WIDTH = 2'b00; + parameter INTERLEAVE_EN = 3'b000; + parameter INTERLEAVE_MODE = 3'b000; endmodule module MIPI_DPHY(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N @@ -1764,9 +1764,9 @@ input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; input HSTXD_VLD; input CK0, CK90, CK180, CK270; input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; -input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, +input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, - LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; output [7:0] MRDATA; input MA_INC, MCLK; @@ -1780,269 +1780,269 @@ input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3 input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK; input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK; input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK; -parameter TX_PLLCLK = "NONE"; -parameter RX_ALIGN_BYTE = 8'b10111000 ; -parameter RX_HS_8BIT_MODE = 1'b0 ; -parameter RX_LANE_ALIGN_EN = 1'b0 ; -parameter TX_HS_8BIT_MODE = 1'b0 ; -parameter HSREG_EN_LN0 = 1'b0; -parameter HSREG_EN_LN1 = 1'b0; -parameter HSREG_EN_LN2 = 1'b0; -parameter HSREG_EN_LN3 = 1'b0; -parameter HSREG_EN_LNCK = 1'b0; -parameter LANE_DIV_SEL = 2'b00; -parameter HSRX_EN = 1'b1 ; -parameter HSRX_LANESEL = 4'b1111 ; -parameter HSRX_LANESEL_CK = 1'b1 ; -parameter HSTX_EN_LN0 = 1'b0 ; -parameter HSTX_EN_LN1 = 1'b0 ; -parameter HSTX_EN_LN2 = 1'b0 ; -parameter HSTX_EN_LN3 = 1'b0 ; -parameter HSTX_EN_LNCK = 1'b0 ; -parameter LPTX_EN_LN0 = 1'b1 ; -parameter LPTX_EN_LN1 = 1'b1 ; -parameter LPTX_EN_LN2 = 1'b1 ; -parameter LPTX_EN_LN3 = 1'b1 ; -parameter LPTX_EN_LNCK = 1'b1 ; -parameter TXDP_EN_LN0 = 1'b0 ; -parameter TXDP_EN_LN1 = 1'b0 ; -parameter TXDP_EN_LN2 = 1'b0 ; -parameter TXDP_EN_LN3 = 1'b0 ; +parameter TX_PLLCLK = "NONE"; +parameter RX_ALIGN_BYTE = 8'b10111000 ; +parameter RX_HS_8BIT_MODE = 1'b0 ; +parameter RX_LANE_ALIGN_EN = 1'b0 ; +parameter TX_HS_8BIT_MODE = 1'b0 ; +parameter HSREG_EN_LN0 = 1'b0; +parameter HSREG_EN_LN1 = 1'b0; +parameter HSREG_EN_LN2 = 1'b0; +parameter HSREG_EN_LN3 = 1'b0; +parameter HSREG_EN_LNCK = 1'b0; +parameter LANE_DIV_SEL = 2'b00; +parameter HSRX_EN = 1'b1 ; +parameter HSRX_LANESEL = 4'b1111 ; +parameter HSRX_LANESEL_CK = 1'b1 ; +parameter HSTX_EN_LN0 = 1'b0 ; +parameter HSTX_EN_LN1 = 1'b0 ; +parameter HSTX_EN_LN2 = 1'b0 ; +parameter HSTX_EN_LN3 = 1'b0 ; +parameter HSTX_EN_LNCK = 1'b0 ; +parameter LPTX_EN_LN0 = 1'b1 ; +parameter LPTX_EN_LN1 = 1'b1 ; +parameter LPTX_EN_LN2 = 1'b1 ; +parameter LPTX_EN_LN3 = 1'b1 ; +parameter LPTX_EN_LNCK = 1'b1 ; +parameter TXDP_EN_LN0 = 1'b0 ; +parameter TXDP_EN_LN1 = 1'b0 ; +parameter TXDP_EN_LN2 = 1'b0 ; +parameter TXDP_EN_LN3 = 1'b0 ; parameter TXDP_EN_LNCK = 1'b0 ; -parameter CKLN_DELAY_EN = 1'b0; -parameter CKLN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DELAY_EN = 1'b0; -parameter D0LN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DESKEW_BYPASS = 1'b0; -parameter D1LN_DELAY_EN = 1'b0; -parameter D1LN_DELAY_OVR_VAL = 7'b0000000; -parameter D1LN_DESKEW_BYPASS = 1'b0; -parameter D2LN_DELAY_EN = 1'b0; -parameter D2LN_DELAY_OVR_VAL = 7'b0000000; -parameter D2LN_DESKEW_BYPASS = 1'b0; -parameter D3LN_DELAY_EN = 1'b0; -parameter D3LN_DELAY_OVR_VAL = 7'b0000000; -parameter D3LN_DESKEW_BYPASS = 1'b0; -parameter DESKEW_EN_LOW_DELAY = 1'b0; -parameter DESKEW_EN_ONE_EDGE = 1'b0; -parameter DESKEW_FAST_LOOP_TIME = 4'b0000; -parameter DESKEW_FAST_MODE = 1'b0; -parameter DESKEW_HALF_OPENING = 6'b010110; -parameter DESKEW_LSB_MODE = 2'b00; -parameter DESKEW_M = 3'b011; -parameter DESKEW_M_TH = 13'b0000110100110; -parameter DESKEW_MAX_SETTING = 7'b0100001; -parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; -parameter DESKEW_RST_BYPASS = 1'b0 ; -parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; -parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; -parameter RX_INVERT = 1'b0 ; -parameter RX_ONE_BYTE0_MATCH = 1'b0 ; -parameter RX_RD_START_DEPTH = 5'b00001; -parameter RX_SYNC_MODE = 1'b0 ; -parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; -parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; -parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter TX_BYPASS_MODE = 1'b0 ; -parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; -parameter TX_OCLK_USE_CIBCLK = 1'b0 ; -parameter TX_RD_START_DEPTH = 5'b00001; -parameter TX_SYNC_MODE = 1'b0 ; -parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter EQ_CS_LANE0 = 3'b100; -parameter EQ_CS_LANE1 = 3'b100; -parameter EQ_CS_LANE2 = 3'b100; -parameter EQ_CS_LANE3 = 3'b100; -parameter EQ_CS_LANECK = 3'b100; -parameter EQ_RS_LANE0 = 3'b100; -parameter EQ_RS_LANE1 = 3'b100; -parameter EQ_RS_LANE2 = 3'b100; -parameter EQ_RS_LANE3 = 3'b100; -parameter EQ_RS_LANECK = 3'b100; -parameter HSCLK_LANE_LN0 = 1'b0; -parameter HSCLK_LANE_LN1 = 1'b0; -parameter HSCLK_LANE_LN2 = 1'b0; -parameter HSCLK_LANE_LN3 = 1'b0; -parameter HSCLK_LANE_LNCK = 1'b1; -parameter ALP_ED_EN_LANE0 = 1'b1 ; -parameter ALP_ED_EN_LANE1 = 1'b1 ; -parameter ALP_ED_EN_LANE2 = 1'b1 ; -parameter ALP_ED_EN_LANE3 = 1'b1 ; -parameter ALP_ED_EN_LANECK = 1'b1 ; -parameter ALP_ED_TST_LANE0 = 1'b0 ; -parameter ALP_ED_TST_LANE1 = 1'b0 ; -parameter ALP_ED_TST_LANE2 = 1'b0 ; -parameter ALP_ED_TST_LANE3 = 1'b0 ; -parameter ALP_ED_TST_LANECK = 1'b0 ; -parameter ALP_EN_LN0 = 1'b0 ; -parameter ALP_EN_LN1 = 1'b0 ; -parameter ALP_EN_LN2 = 1'b0 ; -parameter ALP_EN_LN3 = 1'b0 ; -parameter ALP_EN_LNCK = 1'b0 ; -parameter ALP_HYS_EN_LANE0 = 1'b1 ; -parameter ALP_HYS_EN_LANE1 = 1'b1 ; -parameter ALP_HYS_EN_LANE2 = 1'b1 ; -parameter ALP_HYS_EN_LANE3 = 1'b1 ; -parameter ALP_HYS_EN_LANECK = 1'b1 ; -parameter ALP_TH_LANE0 = 4'b1000 ; -parameter ALP_TH_LANE1 = 4'b1000 ; -parameter ALP_TH_LANE2 = 4'b1000 ; -parameter ALP_TH_LANE3 = 4'b1000 ; -parameter ALP_TH_LANECK = 4'b1000 ; -parameter ANA_BYTECLK_PH = 2'b00 ; -parameter BIT_REVERSE_LN0 = 1'b0 ; -parameter BIT_REVERSE_LN1 = 1'b0 ; -parameter BIT_REVERSE_LN2 = 1'b0 ; -parameter BIT_REVERSE_LN3 = 1'b0 ; -parameter BIT_REVERSE_LNCK = 1'b0 ; -parameter BYPASS_TXHCLKEN = 1'b1 ; -parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; -parameter BYTE_CLK_POLAR = 1'b0 ; -parameter BYTE_REVERSE_LN0 = 1'b0 ; -parameter BYTE_REVERSE_LN1 = 1'b0 ; -parameter BYTE_REVERSE_LN2 = 1'b0 ; -parameter BYTE_REVERSE_LN3 = 1'b0 ; -parameter BYTE_REVERSE_LNCK = 1'b0 ; -parameter EN_CLKB1X = 1'b1 ; -parameter EQ_PBIAS_LANE0 = 4'b1000 ; -parameter EQ_PBIAS_LANE1 = 4'b1000 ; -parameter EQ_PBIAS_LANE2 = 4'b1000 ; -parameter EQ_PBIAS_LANE3 = 4'b1000 ; -parameter EQ_PBIAS_LANECK = 4'b1000 ; -parameter EQ_ZLD_LANE0 = 4'b1000 ; -parameter EQ_ZLD_LANE1 = 4'b1000 ; -parameter EQ_ZLD_LANE2 = 4'b1000 ; -parameter EQ_ZLD_LANE3 = 4'b1000 ; -parameter EQ_ZLD_LANECK = 4'b1000 ; -parameter HIGH_BW_LANE0 = 1'b1 ; -parameter HIGH_BW_LANE1 = 1'b1 ; -parameter HIGH_BW_LANE2 = 1'b1 ; -parameter HIGH_BW_LANE3 = 1'b1 ; -parameter HIGH_BW_LANECK = 1'b1 ; -parameter HSREG_VREF_CTL = 3'b100 ; -parameter HSREG_VREF_EN = 1'b1 ; -parameter HSRX_DLY_CTL_CK = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; -parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; -parameter HSRX_DLY_SEL_LANECK = 1'b0 ; -parameter HSRX_DUTY_LANE0 = 4'b1000 ; -parameter HSRX_DUTY_LANE1 = 4'b1000 ; -parameter HSRX_DUTY_LANE2 = 4'b1000 ; -parameter HSRX_DUTY_LANE3 = 4'b1000 ; -parameter HSRX_DUTY_LANECK = 4'b1000 ; -parameter HSRX_EQ_EN_LANE0 = 1'b1 ; -parameter HSRX_EQ_EN_LANE1 = 1'b1 ; -parameter HSRX_EQ_EN_LANE2 = 1'b1 ; -parameter HSRX_EQ_EN_LANE3 = 1'b1 ; -parameter HSRX_EQ_EN_LANECK = 1'b1 ; -parameter HSRX_IBIAS = 4'b0011 ; -parameter HSRX_IBIAS_TEST_EN = 1'b0 ; -parameter HSRX_IMARG_EN = 1'b0 ; -parameter HSRX_ODT_EN = 1'b1 ; -parameter HSRX_ODT_TST = 4'b0000 ; -parameter HSRX_ODT_TST_CK = 1'b0 ; -parameter HSRX_SEL = 4'b0000 ; -parameter HSRX_STOP_EN = 1'b0 ; -parameter HSRX_TST = 4'b0000 ; -parameter HSRX_TST_CK = 1'b0 ; -parameter HSRX_WAIT4EDGE = 1'b1 ; -parameter HYST_NCTL = 2'b01 ; -parameter HYST_PCTL = 2'b01 ; -parameter IBIAS_TEST_EN = 1'b0 ; -parameter LB_CH_SEL = 1'b0 ; -parameter LB_EN_LN0 = 1'b0 ; -parameter LB_EN_LN1 = 1'b0 ; -parameter LB_EN_LN2 = 1'b0 ; -parameter LB_EN_LN3 = 1'b0 ; -parameter LB_EN_LNCK = 1'b0 ; -parameter LB_POLAR_LN0 = 1'b0 ; -parameter LB_POLAR_LN1 = 1'b0 ; -parameter LB_POLAR_LN2 = 1'b0 ; -parameter LB_POLAR_LN3 = 1'b0 ; -parameter LB_POLAR_LNCK = 1'b0 ; -parameter LOW_LPRX_VTH = 1'b0 ; -parameter LPBK_DATA2TO1 = 4'b0000; -parameter LPBK_DATA2TO1_CK = 1'b0 ; -parameter LPBK_EN = 1'b0 ; -parameter LPBK_SEL = 4'b0000; -parameter LPBKTST_EN = 4'b0000; -parameter LPBKTST_EN_CK = 1'b0 ; -parameter LPRX_EN = 1'b1 ; -parameter LPRX_TST = 4'b0000; -parameter LPRX_TST_CK = 1'b0 ; -parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; -parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; -parameter LPTX_NIMP_LN0 = 3'b100 ; -parameter LPTX_NIMP_LN1 = 3'b100 ; -parameter LPTX_NIMP_LN2 = 3'b100 ; -parameter LPTX_NIMP_LN3 = 3'b100 ; -parameter LPTX_NIMP_LNCK = 3'b100 ; -parameter LPTX_PIMP_LN0 = 3'b100 ; -parameter LPTX_PIMP_LN1 = 3'b100 ; -parameter LPTX_PIMP_LN2 = 3'b100 ; -parameter LPTX_PIMP_LN3 = 3'b100 ; -parameter LPTX_PIMP_LNCK = 3'b100 ; -parameter MIPI_PMA_DIS_N = 1'b1 ; -parameter PGA_BIAS_LANE0 = 4'b1000 ; -parameter PGA_BIAS_LANE1 = 4'b1000 ; -parameter PGA_BIAS_LANE2 = 4'b1000 ; -parameter PGA_BIAS_LANE3 = 4'b1000 ; -parameter PGA_BIAS_LANECK = 4'b1000 ; -parameter PGA_GAIN_LANE0 = 4'b1000 ; -parameter PGA_GAIN_LANE1 = 4'b1000 ; -parameter PGA_GAIN_LANE2 = 4'b1000 ; -parameter PGA_GAIN_LANE3 = 4'b1000 ; -parameter PGA_GAIN_LANECK = 4'b1000 ; -parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; -parameter RX_ODT_TRIM_LANECK = 4'b1000 ; -parameter SLEWN_CTL_LN0 = 4'b1111 ; -parameter SLEWN_CTL_LN1 = 4'b1111 ; -parameter SLEWN_CTL_LN2 = 4'b1111 ; -parameter SLEWN_CTL_LN3 = 4'b1111 ; -parameter SLEWN_CTL_LNCK = 4'b1111 ; -parameter SLEWP_CTL_LN0 = 4'b1111 ; -parameter SLEWP_CTL_LN1 = 4'b1111 ; -parameter SLEWP_CTL_LN2 = 4'b1111 ; -parameter SLEWP_CTL_LN3 = 4'b1111 ; -parameter SLEWP_CTL_LNCK = 4'b1111 ; -parameter STP_UNIT = 2'b01 ; -parameter TERMN_CTL_LN0 = 4'b1000 ; -parameter TERMN_CTL_LN1 = 4'b1000 ; -parameter TERMN_CTL_LN2 = 4'b1000 ; -parameter TERMN_CTL_LN3 = 4'b1000 ; -parameter TERMN_CTL_LNCK = 4'b1000 ; -parameter TERMP_CTL_LN0 = 4'b1000 ; -parameter TERMP_CTL_LN1 = 4'b1000 ; -parameter TERMP_CTL_LN2 = 4'b1000 ; -parameter TERMP_CTL_LN3 = 4'b1000 ; -parameter TERMP_CTL_LNCK = 4'b1000 ; -parameter TEST_EN_LN0 = 1'b0 ; -parameter TEST_EN_LN1 = 1'b0 ; -parameter TEST_EN_LN2 = 1'b0 ; -parameter TEST_EN_LN3 = 1'b0 ; -parameter TEST_EN_LNCK = 1'b0 ; -parameter TEST_N_IMP_LN0 = 1'b0 ; -parameter TEST_N_IMP_LN1 = 1'b0 ; -parameter TEST_N_IMP_LN2 = 1'b0 ; -parameter TEST_N_IMP_LN3 = 1'b0 ; -parameter TEST_N_IMP_LNCK = 1'b0 ; -parameter TEST_P_IMP_LN0 = 1'b0 ; -parameter TEST_P_IMP_LN1 = 1'b0 ; -parameter TEST_P_IMP_LN2 = 1'b0 ; -parameter TEST_P_IMP_LN3 = 1'b0 ; -parameter TEST_P_IMP_LNCK = 1'b0 ; +parameter CKLN_DELAY_EN = 1'b0; +parameter CKLN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DELAY_EN = 1'b0; +parameter D0LN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DESKEW_BYPASS = 1'b0; +parameter D1LN_DELAY_EN = 1'b0; +parameter D1LN_DELAY_OVR_VAL = 7'b0000000; +parameter D1LN_DESKEW_BYPASS = 1'b0; +parameter D2LN_DELAY_EN = 1'b0; +parameter D2LN_DELAY_OVR_VAL = 7'b0000000; +parameter D2LN_DESKEW_BYPASS = 1'b0; +parameter D3LN_DELAY_EN = 1'b0; +parameter D3LN_DELAY_OVR_VAL = 7'b0000000; +parameter D3LN_DESKEW_BYPASS = 1'b0; +parameter DESKEW_EN_LOW_DELAY = 1'b0; +parameter DESKEW_EN_ONE_EDGE = 1'b0; +parameter DESKEW_FAST_LOOP_TIME = 4'b0000; +parameter DESKEW_FAST_MODE = 1'b0; +parameter DESKEW_HALF_OPENING = 6'b010110; +parameter DESKEW_LSB_MODE = 2'b00; +parameter DESKEW_M = 3'b011; +parameter DESKEW_M_TH = 13'b0000110100110; +parameter DESKEW_MAX_SETTING = 7'b0100001; +parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; +parameter DESKEW_RST_BYPASS = 1'b0 ; +parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; +parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; +parameter RX_INVERT = 1'b0 ; +parameter RX_ONE_BYTE0_MATCH = 1'b0 ; +parameter RX_RD_START_DEPTH = 5'b00001; +parameter RX_SYNC_MODE = 1'b0 ; +parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; +parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter TX_BYPASS_MODE = 1'b0 ; +parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; +parameter TX_OCLK_USE_CIBCLK = 1'b0 ; +parameter TX_RD_START_DEPTH = 5'b00001; +parameter TX_SYNC_MODE = 1'b0 ; +parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter EQ_CS_LANE0 = 3'b100; +parameter EQ_CS_LANE1 = 3'b100; +parameter EQ_CS_LANE2 = 3'b100; +parameter EQ_CS_LANE3 = 3'b100; +parameter EQ_CS_LANECK = 3'b100; +parameter EQ_RS_LANE0 = 3'b100; +parameter EQ_RS_LANE1 = 3'b100; +parameter EQ_RS_LANE2 = 3'b100; +parameter EQ_RS_LANE3 = 3'b100; +parameter EQ_RS_LANECK = 3'b100; +parameter HSCLK_LANE_LN0 = 1'b0; +parameter HSCLK_LANE_LN1 = 1'b0; +parameter HSCLK_LANE_LN2 = 1'b0; +parameter HSCLK_LANE_LN3 = 1'b0; +parameter HSCLK_LANE_LNCK = 1'b1; +parameter ALP_ED_EN_LANE0 = 1'b1 ; +parameter ALP_ED_EN_LANE1 = 1'b1 ; +parameter ALP_ED_EN_LANE2 = 1'b1 ; +parameter ALP_ED_EN_LANE3 = 1'b1 ; +parameter ALP_ED_EN_LANECK = 1'b1 ; +parameter ALP_ED_TST_LANE0 = 1'b0 ; +parameter ALP_ED_TST_LANE1 = 1'b0 ; +parameter ALP_ED_TST_LANE2 = 1'b0 ; +parameter ALP_ED_TST_LANE3 = 1'b0 ; +parameter ALP_ED_TST_LANECK = 1'b0 ; +parameter ALP_EN_LN0 = 1'b0 ; +parameter ALP_EN_LN1 = 1'b0 ; +parameter ALP_EN_LN2 = 1'b0 ; +parameter ALP_EN_LN3 = 1'b0 ; +parameter ALP_EN_LNCK = 1'b0 ; +parameter ALP_HYS_EN_LANE0 = 1'b1 ; +parameter ALP_HYS_EN_LANE1 = 1'b1 ; +parameter ALP_HYS_EN_LANE2 = 1'b1 ; +parameter ALP_HYS_EN_LANE3 = 1'b1 ; +parameter ALP_HYS_EN_LANECK = 1'b1 ; +parameter ALP_TH_LANE0 = 4'b1000 ; +parameter ALP_TH_LANE1 = 4'b1000 ; +parameter ALP_TH_LANE2 = 4'b1000 ; +parameter ALP_TH_LANE3 = 4'b1000 ; +parameter ALP_TH_LANECK = 4'b1000 ; +parameter ANA_BYTECLK_PH = 2'b00 ; +parameter BIT_REVERSE_LN0 = 1'b0 ; +parameter BIT_REVERSE_LN1 = 1'b0 ; +parameter BIT_REVERSE_LN2 = 1'b0 ; +parameter BIT_REVERSE_LN3 = 1'b0 ; +parameter BIT_REVERSE_LNCK = 1'b0 ; +parameter BYPASS_TXHCLKEN = 1'b1 ; +parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; +parameter BYTE_CLK_POLAR = 1'b0 ; +parameter BYTE_REVERSE_LN0 = 1'b0 ; +parameter BYTE_REVERSE_LN1 = 1'b0 ; +parameter BYTE_REVERSE_LN2 = 1'b0 ; +parameter BYTE_REVERSE_LN3 = 1'b0 ; +parameter BYTE_REVERSE_LNCK = 1'b0 ; +parameter EN_CLKB1X = 1'b1 ; +parameter EQ_PBIAS_LANE0 = 4'b1000 ; +parameter EQ_PBIAS_LANE1 = 4'b1000 ; +parameter EQ_PBIAS_LANE2 = 4'b1000 ; +parameter EQ_PBIAS_LANE3 = 4'b1000 ; +parameter EQ_PBIAS_LANECK = 4'b1000 ; +parameter EQ_ZLD_LANE0 = 4'b1000 ; +parameter EQ_ZLD_LANE1 = 4'b1000 ; +parameter EQ_ZLD_LANE2 = 4'b1000 ; +parameter EQ_ZLD_LANE3 = 4'b1000 ; +parameter EQ_ZLD_LANECK = 4'b1000 ; +parameter HIGH_BW_LANE0 = 1'b1 ; +parameter HIGH_BW_LANE1 = 1'b1 ; +parameter HIGH_BW_LANE2 = 1'b1 ; +parameter HIGH_BW_LANE3 = 1'b1 ; +parameter HIGH_BW_LANECK = 1'b1 ; +parameter HSREG_VREF_CTL = 3'b100 ; +parameter HSREG_VREF_EN = 1'b1 ; +parameter HSRX_DLY_CTL_CK = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; +parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; +parameter HSRX_DLY_SEL_LANECK = 1'b0 ; +parameter HSRX_DUTY_LANE0 = 4'b1000 ; +parameter HSRX_DUTY_LANE1 = 4'b1000 ; +parameter HSRX_DUTY_LANE2 = 4'b1000 ; +parameter HSRX_DUTY_LANE3 = 4'b1000 ; +parameter HSRX_DUTY_LANECK = 4'b1000 ; +parameter HSRX_EQ_EN_LANE0 = 1'b1 ; +parameter HSRX_EQ_EN_LANE1 = 1'b1 ; +parameter HSRX_EQ_EN_LANE2 = 1'b1 ; +parameter HSRX_EQ_EN_LANE3 = 1'b1 ; +parameter HSRX_EQ_EN_LANECK = 1'b1 ; +parameter HSRX_IBIAS = 4'b0011 ; +parameter HSRX_IBIAS_TEST_EN = 1'b0 ; +parameter HSRX_IMARG_EN = 1'b0 ; +parameter HSRX_ODT_EN = 1'b1 ; +parameter HSRX_ODT_TST = 4'b0000 ; +parameter HSRX_ODT_TST_CK = 1'b0 ; +parameter HSRX_SEL = 4'b0000 ; +parameter HSRX_STOP_EN = 1'b0 ; +parameter HSRX_TST = 4'b0000 ; +parameter HSRX_TST_CK = 1'b0 ; +parameter HSRX_WAIT4EDGE = 1'b1 ; +parameter HYST_NCTL = 2'b01 ; +parameter HYST_PCTL = 2'b01 ; +parameter IBIAS_TEST_EN = 1'b0 ; +parameter LB_CH_SEL = 1'b0 ; +parameter LB_EN_LN0 = 1'b0 ; +parameter LB_EN_LN1 = 1'b0 ; +parameter LB_EN_LN2 = 1'b0 ; +parameter LB_EN_LN3 = 1'b0 ; +parameter LB_EN_LNCK = 1'b0 ; +parameter LB_POLAR_LN0 = 1'b0 ; +parameter LB_POLAR_LN1 = 1'b0 ; +parameter LB_POLAR_LN2 = 1'b0 ; +parameter LB_POLAR_LN3 = 1'b0 ; +parameter LB_POLAR_LNCK = 1'b0 ; +parameter LOW_LPRX_VTH = 1'b0 ; +parameter LPBK_DATA2TO1 = 4'b0000; +parameter LPBK_DATA2TO1_CK = 1'b0 ; +parameter LPBK_EN = 1'b0 ; +parameter LPBK_SEL = 4'b0000; +parameter LPBKTST_EN = 4'b0000; +parameter LPBKTST_EN_CK = 1'b0 ; +parameter LPRX_EN = 1'b1 ; +parameter LPRX_TST = 4'b0000; +parameter LPRX_TST_CK = 1'b0 ; +parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; +parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; +parameter LPTX_NIMP_LN0 = 3'b100 ; +parameter LPTX_NIMP_LN1 = 3'b100 ; +parameter LPTX_NIMP_LN2 = 3'b100 ; +parameter LPTX_NIMP_LN3 = 3'b100 ; +parameter LPTX_NIMP_LNCK = 3'b100 ; +parameter LPTX_PIMP_LN0 = 3'b100 ; +parameter LPTX_PIMP_LN1 = 3'b100 ; +parameter LPTX_PIMP_LN2 = 3'b100 ; +parameter LPTX_PIMP_LN3 = 3'b100 ; +parameter LPTX_PIMP_LNCK = 3'b100 ; +parameter MIPI_PMA_DIS_N = 1'b1 ; +parameter PGA_BIAS_LANE0 = 4'b1000 ; +parameter PGA_BIAS_LANE1 = 4'b1000 ; +parameter PGA_BIAS_LANE2 = 4'b1000 ; +parameter PGA_BIAS_LANE3 = 4'b1000 ; +parameter PGA_BIAS_LANECK = 4'b1000 ; +parameter PGA_GAIN_LANE0 = 4'b1000 ; +parameter PGA_GAIN_LANE1 = 4'b1000 ; +parameter PGA_GAIN_LANE2 = 4'b1000 ; +parameter PGA_GAIN_LANE3 = 4'b1000 ; +parameter PGA_GAIN_LANECK = 4'b1000 ; +parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; +parameter RX_ODT_TRIM_LANECK = 4'b1000 ; +parameter SLEWN_CTL_LN0 = 4'b1111 ; +parameter SLEWN_CTL_LN1 = 4'b1111 ; +parameter SLEWN_CTL_LN2 = 4'b1111 ; +parameter SLEWN_CTL_LN3 = 4'b1111 ; +parameter SLEWN_CTL_LNCK = 4'b1111 ; +parameter SLEWP_CTL_LN0 = 4'b1111 ; +parameter SLEWP_CTL_LN1 = 4'b1111 ; +parameter SLEWP_CTL_LN2 = 4'b1111 ; +parameter SLEWP_CTL_LN3 = 4'b1111 ; +parameter SLEWP_CTL_LNCK = 4'b1111 ; +parameter STP_UNIT = 2'b01 ; +parameter TERMN_CTL_LN0 = 4'b1000 ; +parameter TERMN_CTL_LN1 = 4'b1000 ; +parameter TERMN_CTL_LN2 = 4'b1000 ; +parameter TERMN_CTL_LN3 = 4'b1000 ; +parameter TERMN_CTL_LNCK = 4'b1000 ; +parameter TERMP_CTL_LN0 = 4'b1000 ; +parameter TERMP_CTL_LN1 = 4'b1000 ; +parameter TERMP_CTL_LN2 = 4'b1000 ; +parameter TERMP_CTL_LN3 = 4'b1000 ; +parameter TERMP_CTL_LNCK = 4'b1000 ; +parameter TEST_EN_LN0 = 1'b0 ; +parameter TEST_EN_LN1 = 1'b0 ; +parameter TEST_EN_LN2 = 1'b0 ; +parameter TEST_EN_LN3 = 1'b0 ; +parameter TEST_EN_LNCK = 1'b0 ; +parameter TEST_N_IMP_LN0 = 1'b0 ; +parameter TEST_N_IMP_LN1 = 1'b0 ; +parameter TEST_N_IMP_LN2 = 1'b0 ; +parameter TEST_N_IMP_LN3 = 1'b0 ; +parameter TEST_N_IMP_LNCK = 1'b0 ; +parameter TEST_P_IMP_LN0 = 1'b0 ; +parameter TEST_P_IMP_LN1 = 1'b0 ; +parameter TEST_P_IMP_LN2 = 1'b0 ; +parameter TEST_P_IMP_LN3 = 1'b0 ; +parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule module MIPI_DPHYA(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N @@ -2066,9 +2066,9 @@ input [15:0] CKLN_HSTXD,D0LN_HSTXD,D1LN_HSTXD,D2LN_HSTXD,D3LN_HSTXD; input HSTXD_VLD; input CK0, CK90, CK180, CK270; input DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P; -input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, +input HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, - LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; + LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; input RX_DRST_N, TX_DRST_N, WALIGN_DVLD; output [7:0] MRDATA; input MA_INC, MCLK; @@ -2083,271 +2083,271 @@ input HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3 input HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK; input HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK; input ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK; -parameter TX_PLLCLK = "NONE"; -parameter RX_ALIGN_BYTE = 8'b10111000 ; -parameter RX_HS_8BIT_MODE = 1'b0 ; -parameter RX_LANE_ALIGN_EN = 1'b0 ; -parameter TX_HS_8BIT_MODE = 1'b0 ; -parameter HSREG_EN_LN0 = 1'b0; -parameter HSREG_EN_LN1 = 1'b0; -parameter HSREG_EN_LN2 = 1'b0; -parameter HSREG_EN_LN3 = 1'b0; -parameter HSREG_EN_LNCK = 1'b0; -parameter LANE_DIV_SEL = 2'b00; -parameter HSRX_EN = 1'b1 ; -parameter HSRX_LANESEL = 4'b1111 ; -parameter HSRX_LANESEL_CK = 1'b1 ; -parameter HSTX_EN_LN0 = 1'b0 ; -parameter HSTX_EN_LN1 = 1'b0 ; -parameter HSTX_EN_LN2 = 1'b0 ; -parameter HSTX_EN_LN3 = 1'b0 ; -parameter HSTX_EN_LNCK = 1'b0 ; -parameter LPTX_EN_LN0 = 1'b1 ; -parameter LPTX_EN_LN1 = 1'b1 ; -parameter LPTX_EN_LN2 = 1'b1 ; -parameter LPTX_EN_LN3 = 1'b1 ; -parameter LPTX_EN_LNCK = 1'b1 ; -parameter TXDP_EN_LN0 = 1'b0 ; -parameter TXDP_EN_LN1 = 1'b0 ; -parameter TXDP_EN_LN2 = 1'b0 ; -parameter TXDP_EN_LN3 = 1'b0 ; +parameter TX_PLLCLK = "NONE"; +parameter RX_ALIGN_BYTE = 8'b10111000 ; +parameter RX_HS_8BIT_MODE = 1'b0 ; +parameter RX_LANE_ALIGN_EN = 1'b0 ; +parameter TX_HS_8BIT_MODE = 1'b0 ; +parameter HSREG_EN_LN0 = 1'b0; +parameter HSREG_EN_LN1 = 1'b0; +parameter HSREG_EN_LN2 = 1'b0; +parameter HSREG_EN_LN3 = 1'b0; +parameter HSREG_EN_LNCK = 1'b0; +parameter LANE_DIV_SEL = 2'b00; +parameter HSRX_EN = 1'b1 ; +parameter HSRX_LANESEL = 4'b1111 ; +parameter HSRX_LANESEL_CK = 1'b1 ; +parameter HSTX_EN_LN0 = 1'b0 ; +parameter HSTX_EN_LN1 = 1'b0 ; +parameter HSTX_EN_LN2 = 1'b0 ; +parameter HSTX_EN_LN3 = 1'b0 ; +parameter HSTX_EN_LNCK = 1'b0 ; +parameter LPTX_EN_LN0 = 1'b1 ; +parameter LPTX_EN_LN1 = 1'b1 ; +parameter LPTX_EN_LN2 = 1'b1 ; +parameter LPTX_EN_LN3 = 1'b1 ; +parameter LPTX_EN_LNCK = 1'b1 ; +parameter TXDP_EN_LN0 = 1'b0 ; +parameter TXDP_EN_LN1 = 1'b0 ; +parameter TXDP_EN_LN2 = 1'b0 ; +parameter TXDP_EN_LN3 = 1'b0 ; parameter TXDP_EN_LNCK = 1'b0 ; parameter SPLL_DIV_SEL = 2'b00; parameter DPHY_CK_SEL = 2'b01; -parameter CKLN_DELAY_EN = 1'b0; -parameter CKLN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DELAY_EN = 1'b0; -parameter D0LN_DELAY_OVR_VAL = 7'b0000000; -parameter D0LN_DESKEW_BYPASS = 1'b0; -parameter D1LN_DELAY_EN = 1'b0; -parameter D1LN_DELAY_OVR_VAL = 7'b0000000; -parameter D1LN_DESKEW_BYPASS = 1'b0; -parameter D2LN_DELAY_EN = 1'b0; -parameter D2LN_DELAY_OVR_VAL = 7'b0000000; -parameter D2LN_DESKEW_BYPASS = 1'b0; -parameter D3LN_DELAY_EN = 1'b0; -parameter D3LN_DELAY_OVR_VAL = 7'b0000000; -parameter D3LN_DESKEW_BYPASS = 1'b0; -parameter DESKEW_EN_LOW_DELAY = 1'b0; -parameter DESKEW_EN_ONE_EDGE = 1'b0; -parameter DESKEW_FAST_LOOP_TIME = 4'b0000; -parameter DESKEW_FAST_MODE = 1'b0; -parameter DESKEW_HALF_OPENING = 6'b010110; -parameter DESKEW_LSB_MODE = 2'b00; -parameter DESKEW_M = 3'b011; -parameter DESKEW_M_TH = 13'b0000110100110; -parameter DESKEW_MAX_SETTING = 7'b0100001; -parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; -parameter DESKEW_RST_BYPASS = 1'b0 ; -parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; -parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; -parameter RX_INVERT = 1'b0 ; -parameter RX_ONE_BYTE0_MATCH = 1'b0 ; -parameter RX_RD_START_DEPTH = 5'b00001; -parameter RX_SYNC_MODE = 1'b0 ; -parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; -parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; -parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter TX_BYPASS_MODE = 1'b0 ; -parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; -parameter TX_OCLK_USE_CIBCLK = 1'b0 ; -parameter TX_RD_START_DEPTH = 5'b00001; -parameter TX_SYNC_MODE = 1'b0 ; -parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; -parameter EQ_CS_LANE0 = 3'b100; -parameter EQ_CS_LANE1 = 3'b100; -parameter EQ_CS_LANE2 = 3'b100; -parameter EQ_CS_LANE3 = 3'b100; -parameter EQ_CS_LANECK = 3'b100; -parameter EQ_RS_LANE0 = 3'b100; -parameter EQ_RS_LANE1 = 3'b100; -parameter EQ_RS_LANE2 = 3'b100; -parameter EQ_RS_LANE3 = 3'b100; -parameter EQ_RS_LANECK = 3'b100; -parameter HSCLK_LANE_LN0 = 1'b0; -parameter HSCLK_LANE_LN1 = 1'b0; -parameter HSCLK_LANE_LN2 = 1'b0; -parameter HSCLK_LANE_LN3 = 1'b0; -parameter HSCLK_LANE_LNCK = 1'b1; -parameter ALP_ED_EN_LANE0 = 1'b1 ; -parameter ALP_ED_EN_LANE1 = 1'b1 ; -parameter ALP_ED_EN_LANE2 = 1'b1 ; -parameter ALP_ED_EN_LANE3 = 1'b1 ; -parameter ALP_ED_EN_LANECK = 1'b1 ; -parameter ALP_ED_TST_LANE0 = 1'b0 ; -parameter ALP_ED_TST_LANE1 = 1'b0 ; -parameter ALP_ED_TST_LANE2 = 1'b0 ; -parameter ALP_ED_TST_LANE3 = 1'b0 ; -parameter ALP_ED_TST_LANECK = 1'b0 ; -parameter ALP_EN_LN0 = 1'b0 ; -parameter ALP_EN_LN1 = 1'b0 ; -parameter ALP_EN_LN2 = 1'b0 ; -parameter ALP_EN_LN3 = 1'b0 ; -parameter ALP_EN_LNCK = 1'b0 ; -parameter ALP_HYS_EN_LANE0 = 1'b1 ; -parameter ALP_HYS_EN_LANE1 = 1'b1 ; -parameter ALP_HYS_EN_LANE2 = 1'b1 ; -parameter ALP_HYS_EN_LANE3 = 1'b1 ; -parameter ALP_HYS_EN_LANECK = 1'b1 ; -parameter ALP_TH_LANE0 = 4'b1000 ; -parameter ALP_TH_LANE1 = 4'b1000 ; -parameter ALP_TH_LANE2 = 4'b1000 ; -parameter ALP_TH_LANE3 = 4'b1000 ; -parameter ALP_TH_LANECK = 4'b1000 ; -parameter ANA_BYTECLK_PH = 2'b00 ; -parameter BIT_REVERSE_LN0 = 1'b0 ; -parameter BIT_REVERSE_LN1 = 1'b0 ; -parameter BIT_REVERSE_LN2 = 1'b0 ; -parameter BIT_REVERSE_LN3 = 1'b0 ; -parameter BIT_REVERSE_LNCK = 1'b0 ; -parameter BYPASS_TXHCLKEN = 1'b1 ; -parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; -parameter BYTE_CLK_POLAR = 1'b0 ; -parameter BYTE_REVERSE_LN0 = 1'b0 ; -parameter BYTE_REVERSE_LN1 = 1'b0 ; -parameter BYTE_REVERSE_LN2 = 1'b0 ; -parameter BYTE_REVERSE_LN3 = 1'b0 ; -parameter BYTE_REVERSE_LNCK = 1'b0 ; -parameter EN_CLKB1X = 1'b1 ; -parameter EQ_PBIAS_LANE0 = 4'b1000 ; -parameter EQ_PBIAS_LANE1 = 4'b1000 ; -parameter EQ_PBIAS_LANE2 = 4'b1000 ; -parameter EQ_PBIAS_LANE3 = 4'b1000 ; -parameter EQ_PBIAS_LANECK = 4'b1000 ; -parameter EQ_ZLD_LANE0 = 4'b1000 ; -parameter EQ_ZLD_LANE1 = 4'b1000 ; -parameter EQ_ZLD_LANE2 = 4'b1000 ; -parameter EQ_ZLD_LANE3 = 4'b1000 ; -parameter EQ_ZLD_LANECK = 4'b1000 ; -parameter HIGH_BW_LANE0 = 1'b1 ; -parameter HIGH_BW_LANE1 = 1'b1 ; -parameter HIGH_BW_LANE2 = 1'b1 ; -parameter HIGH_BW_LANE3 = 1'b1 ; -parameter HIGH_BW_LANECK = 1'b1 ; -parameter HSREG_VREF_CTL = 3'b100 ; -parameter HSREG_VREF_EN = 1'b1 ; -parameter HSRX_DLY_CTL_CK = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; -parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; -parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; -parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; -parameter HSRX_DLY_SEL_LANECK = 1'b0 ; -parameter HSRX_DUTY_LANE0 = 4'b1000 ; -parameter HSRX_DUTY_LANE1 = 4'b1000 ; -parameter HSRX_DUTY_LANE2 = 4'b1000 ; -parameter HSRX_DUTY_LANE3 = 4'b1000 ; -parameter HSRX_DUTY_LANECK = 4'b1000 ; -parameter HSRX_EQ_EN_LANE0 = 1'b1 ; -parameter HSRX_EQ_EN_LANE1 = 1'b1 ; -parameter HSRX_EQ_EN_LANE2 = 1'b1 ; -parameter HSRX_EQ_EN_LANE3 = 1'b1 ; -parameter HSRX_EQ_EN_LANECK = 1'b1 ; -parameter HSRX_IBIAS = 4'b0011 ; -parameter HSRX_IBIAS_TEST_EN = 1'b0 ; -parameter HSRX_IMARG_EN = 1'b0 ; -parameter HSRX_ODT_EN = 1'b1 ; -parameter HSRX_ODT_TST = 4'b0000 ; -parameter HSRX_ODT_TST_CK = 1'b0 ; -parameter HSRX_SEL = 4'b0000 ; -parameter HSRX_STOP_EN = 1'b0 ; -parameter HSRX_TST = 4'b0000 ; -parameter HSRX_TST_CK = 1'b0 ; -parameter HSRX_WAIT4EDGE = 1'b1 ; -parameter HYST_NCTL = 2'b01 ; -parameter HYST_PCTL = 2'b01 ; -parameter IBIAS_TEST_EN = 1'b0 ; -parameter LB_CH_SEL = 1'b0 ; -parameter LB_EN_LN0 = 1'b0 ; -parameter LB_EN_LN1 = 1'b0 ; -parameter LB_EN_LN2 = 1'b0 ; -parameter LB_EN_LN3 = 1'b0 ; -parameter LB_EN_LNCK = 1'b0 ; -parameter LB_POLAR_LN0 = 1'b0 ; -parameter LB_POLAR_LN1 = 1'b0 ; -parameter LB_POLAR_LN2 = 1'b0 ; -parameter LB_POLAR_LN3 = 1'b0 ; -parameter LB_POLAR_LNCK = 1'b0 ; -parameter LOW_LPRX_VTH = 1'b0 ; -parameter LPBK_DATA2TO1 = 4'b0000; -parameter LPBK_DATA2TO1_CK = 1'b0 ; -parameter LPBK_EN = 1'b0 ; -parameter LPBK_SEL = 4'b0000; -parameter LPBKTST_EN = 4'b0000; -parameter LPBKTST_EN_CK = 1'b0 ; -parameter LPRX_EN = 1'b1 ; -parameter LPRX_TST = 4'b0000; -parameter LPRX_TST_CK = 1'b0 ; -parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; -parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; -parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; -parameter LPTX_NIMP_LN0 = 3'b100 ; -parameter LPTX_NIMP_LN1 = 3'b100 ; -parameter LPTX_NIMP_LN2 = 3'b100 ; -parameter LPTX_NIMP_LN3 = 3'b100 ; -parameter LPTX_NIMP_LNCK = 3'b100 ; -parameter LPTX_PIMP_LN0 = 3'b100 ; -parameter LPTX_PIMP_LN1 = 3'b100 ; -parameter LPTX_PIMP_LN2 = 3'b100 ; -parameter LPTX_PIMP_LN3 = 3'b100 ; -parameter LPTX_PIMP_LNCK = 3'b100 ; -parameter MIPI_PMA_DIS_N = 1'b1 ; -parameter PGA_BIAS_LANE0 = 4'b1000 ; -parameter PGA_BIAS_LANE1 = 4'b1000 ; -parameter PGA_BIAS_LANE2 = 4'b1000 ; -parameter PGA_BIAS_LANE3 = 4'b1000 ; -parameter PGA_BIAS_LANECK = 4'b1000 ; -parameter PGA_GAIN_LANE0 = 4'b1000 ; -parameter PGA_GAIN_LANE1 = 4'b1000 ; -parameter PGA_GAIN_LANE2 = 4'b1000 ; -parameter PGA_GAIN_LANE3 = 4'b1000 ; -parameter PGA_GAIN_LANECK = 4'b1000 ; -parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; -parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; -parameter RX_ODT_TRIM_LANECK = 4'b1000 ; -parameter SLEWN_CTL_LN0 = 4'b1111 ; -parameter SLEWN_CTL_LN1 = 4'b1111 ; -parameter SLEWN_CTL_LN2 = 4'b1111 ; -parameter SLEWN_CTL_LN3 = 4'b1111 ; -parameter SLEWN_CTL_LNCK = 4'b1111 ; -parameter SLEWP_CTL_LN0 = 4'b1111 ; -parameter SLEWP_CTL_LN1 = 4'b1111 ; -parameter SLEWP_CTL_LN2 = 4'b1111 ; -parameter SLEWP_CTL_LN3 = 4'b1111 ; -parameter SLEWP_CTL_LNCK = 4'b1111 ; -parameter STP_UNIT = 2'b01 ; -parameter TERMN_CTL_LN0 = 4'b1000 ; -parameter TERMN_CTL_LN1 = 4'b1000 ; -parameter TERMN_CTL_LN2 = 4'b1000 ; -parameter TERMN_CTL_LN3 = 4'b1000 ; -parameter TERMN_CTL_LNCK = 4'b1000 ; -parameter TERMP_CTL_LN0 = 4'b1000 ; -parameter TERMP_CTL_LN1 = 4'b1000 ; -parameter TERMP_CTL_LN2 = 4'b1000 ; -parameter TERMP_CTL_LN3 = 4'b1000 ; -parameter TERMP_CTL_LNCK = 4'b1000 ; -parameter TEST_EN_LN0 = 1'b0 ; -parameter TEST_EN_LN1 = 1'b0 ; -parameter TEST_EN_LN2 = 1'b0 ; -parameter TEST_EN_LN3 = 1'b0 ; -parameter TEST_EN_LNCK = 1'b0 ; -parameter TEST_N_IMP_LN0 = 1'b0 ; -parameter TEST_N_IMP_LN1 = 1'b0 ; -parameter TEST_N_IMP_LN2 = 1'b0 ; -parameter TEST_N_IMP_LN3 = 1'b0 ; -parameter TEST_N_IMP_LNCK = 1'b0 ; -parameter TEST_P_IMP_LN0 = 1'b0 ; -parameter TEST_P_IMP_LN1 = 1'b0 ; -parameter TEST_P_IMP_LN2 = 1'b0 ; -parameter TEST_P_IMP_LN3 = 1'b0 ; -parameter TEST_P_IMP_LNCK = 1'b0 ; +parameter CKLN_DELAY_EN = 1'b0; +parameter CKLN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DELAY_EN = 1'b0; +parameter D0LN_DELAY_OVR_VAL = 7'b0000000; +parameter D0LN_DESKEW_BYPASS = 1'b0; +parameter D1LN_DELAY_EN = 1'b0; +parameter D1LN_DELAY_OVR_VAL = 7'b0000000; +parameter D1LN_DESKEW_BYPASS = 1'b0; +parameter D2LN_DELAY_EN = 1'b0; +parameter D2LN_DELAY_OVR_VAL = 7'b0000000; +parameter D2LN_DESKEW_BYPASS = 1'b0; +parameter D3LN_DELAY_EN = 1'b0; +parameter D3LN_DELAY_OVR_VAL = 7'b0000000; +parameter D3LN_DESKEW_BYPASS = 1'b0; +parameter DESKEW_EN_LOW_DELAY = 1'b0; +parameter DESKEW_EN_ONE_EDGE = 1'b0; +parameter DESKEW_FAST_LOOP_TIME = 4'b0000; +parameter DESKEW_FAST_MODE = 1'b0; +parameter DESKEW_HALF_OPENING = 6'b010110; +parameter DESKEW_LSB_MODE = 2'b00; +parameter DESKEW_M = 3'b011; +parameter DESKEW_M_TH = 13'b0000110100110; +parameter DESKEW_MAX_SETTING = 7'b0100001; +parameter DESKEW_ONE_CLK_EDGE_EN = 1'b0 ; +parameter DESKEW_RST_BYPASS = 1'b0 ; +parameter RX_BYTE_LITTLE_ENDIAN = 1'b1 ; +parameter RX_CLK_1X_SYNC_SEL = 1'b0 ; +parameter RX_INVERT = 1'b0 ; +parameter RX_ONE_BYTE0_MATCH = 1'b0 ; +parameter RX_RD_START_DEPTH = 5'b00001; +parameter RX_SYNC_MODE = 1'b0 ; +parameter RX_WORD_ALIGN_BYPASS = 1'b0 ; +parameter RX_WORD_ALIGN_DATA_VLD_SRC_SEL = 1'b0 ; +parameter RX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter TX_BYPASS_MODE = 1'b0 ; +parameter TX_BYTECLK_SYNC_MODE = 1'b0 ; +parameter TX_OCLK_USE_CIBCLK = 1'b0 ; +parameter TX_RD_START_DEPTH = 5'b00001; +parameter TX_SYNC_MODE = 1'b0 ; +parameter TX_WORD_LITTLE_ENDIAN = 1'b1 ; +parameter EQ_CS_LANE0 = 3'b100; +parameter EQ_CS_LANE1 = 3'b100; +parameter EQ_CS_LANE2 = 3'b100; +parameter EQ_CS_LANE3 = 3'b100; +parameter EQ_CS_LANECK = 3'b100; +parameter EQ_RS_LANE0 = 3'b100; +parameter EQ_RS_LANE1 = 3'b100; +parameter EQ_RS_LANE2 = 3'b100; +parameter EQ_RS_LANE3 = 3'b100; +parameter EQ_RS_LANECK = 3'b100; +parameter HSCLK_LANE_LN0 = 1'b0; +parameter HSCLK_LANE_LN1 = 1'b0; +parameter HSCLK_LANE_LN2 = 1'b0; +parameter HSCLK_LANE_LN3 = 1'b0; +parameter HSCLK_LANE_LNCK = 1'b1; +parameter ALP_ED_EN_LANE0 = 1'b1 ; +parameter ALP_ED_EN_LANE1 = 1'b1 ; +parameter ALP_ED_EN_LANE2 = 1'b1 ; +parameter ALP_ED_EN_LANE3 = 1'b1 ; +parameter ALP_ED_EN_LANECK = 1'b1 ; +parameter ALP_ED_TST_LANE0 = 1'b0 ; +parameter ALP_ED_TST_LANE1 = 1'b0 ; +parameter ALP_ED_TST_LANE2 = 1'b0 ; +parameter ALP_ED_TST_LANE3 = 1'b0 ; +parameter ALP_ED_TST_LANECK = 1'b0 ; +parameter ALP_EN_LN0 = 1'b0 ; +parameter ALP_EN_LN1 = 1'b0 ; +parameter ALP_EN_LN2 = 1'b0 ; +parameter ALP_EN_LN3 = 1'b0 ; +parameter ALP_EN_LNCK = 1'b0 ; +parameter ALP_HYS_EN_LANE0 = 1'b1 ; +parameter ALP_HYS_EN_LANE1 = 1'b1 ; +parameter ALP_HYS_EN_LANE2 = 1'b1 ; +parameter ALP_HYS_EN_LANE3 = 1'b1 ; +parameter ALP_HYS_EN_LANECK = 1'b1 ; +parameter ALP_TH_LANE0 = 4'b1000 ; +parameter ALP_TH_LANE1 = 4'b1000 ; +parameter ALP_TH_LANE2 = 4'b1000 ; +parameter ALP_TH_LANE3 = 4'b1000 ; +parameter ALP_TH_LANECK = 4'b1000 ; +parameter ANA_BYTECLK_PH = 2'b00 ; +parameter BIT_REVERSE_LN0 = 1'b0 ; +parameter BIT_REVERSE_LN1 = 1'b0 ; +parameter BIT_REVERSE_LN2 = 1'b0 ; +parameter BIT_REVERSE_LN3 = 1'b0 ; +parameter BIT_REVERSE_LNCK = 1'b0 ; +parameter BYPASS_TXHCLKEN = 1'b1 ; +parameter BYPASS_TXHCLKEN_SYNC = 1'b0 ; +parameter BYTE_CLK_POLAR = 1'b0 ; +parameter BYTE_REVERSE_LN0 = 1'b0 ; +parameter BYTE_REVERSE_LN1 = 1'b0 ; +parameter BYTE_REVERSE_LN2 = 1'b0 ; +parameter BYTE_REVERSE_LN3 = 1'b0 ; +parameter BYTE_REVERSE_LNCK = 1'b0 ; +parameter EN_CLKB1X = 1'b1 ; +parameter EQ_PBIAS_LANE0 = 4'b1000 ; +parameter EQ_PBIAS_LANE1 = 4'b1000 ; +parameter EQ_PBIAS_LANE2 = 4'b1000 ; +parameter EQ_PBIAS_LANE3 = 4'b1000 ; +parameter EQ_PBIAS_LANECK = 4'b1000 ; +parameter EQ_ZLD_LANE0 = 4'b1000 ; +parameter EQ_ZLD_LANE1 = 4'b1000 ; +parameter EQ_ZLD_LANE2 = 4'b1000 ; +parameter EQ_ZLD_LANE3 = 4'b1000 ; +parameter EQ_ZLD_LANECK = 4'b1000 ; +parameter HIGH_BW_LANE0 = 1'b1 ; +parameter HIGH_BW_LANE1 = 1'b1 ; +parameter HIGH_BW_LANE2 = 1'b1 ; +parameter HIGH_BW_LANE3 = 1'b1 ; +parameter HIGH_BW_LANECK = 1'b1 ; +parameter HSREG_VREF_CTL = 3'b100 ; +parameter HSREG_VREF_EN = 1'b1 ; +parameter HSRX_DLY_CTL_CK = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE0 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE1 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE2 = 7'b0000000 ; +parameter HSRX_DLY_CTL_LANE3 = 7'b0000000 ; +parameter HSRX_DLY_SEL_LANE0 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE1 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE2 = 1'b0 ; +parameter HSRX_DLY_SEL_LANE3 = 1'b0 ; +parameter HSRX_DLY_SEL_LANECK = 1'b0 ; +parameter HSRX_DUTY_LANE0 = 4'b1000 ; +parameter HSRX_DUTY_LANE1 = 4'b1000 ; +parameter HSRX_DUTY_LANE2 = 4'b1000 ; +parameter HSRX_DUTY_LANE3 = 4'b1000 ; +parameter HSRX_DUTY_LANECK = 4'b1000 ; +parameter HSRX_EQ_EN_LANE0 = 1'b1 ; +parameter HSRX_EQ_EN_LANE1 = 1'b1 ; +parameter HSRX_EQ_EN_LANE2 = 1'b1 ; +parameter HSRX_EQ_EN_LANE3 = 1'b1 ; +parameter HSRX_EQ_EN_LANECK = 1'b1 ; +parameter HSRX_IBIAS = 4'b0011 ; +parameter HSRX_IBIAS_TEST_EN = 1'b0 ; +parameter HSRX_IMARG_EN = 1'b0 ; +parameter HSRX_ODT_EN = 1'b1 ; +parameter HSRX_ODT_TST = 4'b0000 ; +parameter HSRX_ODT_TST_CK = 1'b0 ; +parameter HSRX_SEL = 4'b0000 ; +parameter HSRX_STOP_EN = 1'b0 ; +parameter HSRX_TST = 4'b0000 ; +parameter HSRX_TST_CK = 1'b0 ; +parameter HSRX_WAIT4EDGE = 1'b1 ; +parameter HYST_NCTL = 2'b01 ; +parameter HYST_PCTL = 2'b01 ; +parameter IBIAS_TEST_EN = 1'b0 ; +parameter LB_CH_SEL = 1'b0 ; +parameter LB_EN_LN0 = 1'b0 ; +parameter LB_EN_LN1 = 1'b0 ; +parameter LB_EN_LN2 = 1'b0 ; +parameter LB_EN_LN3 = 1'b0 ; +parameter LB_EN_LNCK = 1'b0 ; +parameter LB_POLAR_LN0 = 1'b0 ; +parameter LB_POLAR_LN1 = 1'b0 ; +parameter LB_POLAR_LN2 = 1'b0 ; +parameter LB_POLAR_LN3 = 1'b0 ; +parameter LB_POLAR_LNCK = 1'b0 ; +parameter LOW_LPRX_VTH = 1'b0 ; +parameter LPBK_DATA2TO1 = 4'b0000; +parameter LPBK_DATA2TO1_CK = 1'b0 ; +parameter LPBK_EN = 1'b0 ; +parameter LPBK_SEL = 4'b0000; +parameter LPBKTST_EN = 4'b0000; +parameter LPBKTST_EN_CK = 1'b0 ; +parameter LPRX_EN = 1'b1 ; +parameter LPRX_TST = 4'b0000; +parameter LPRX_TST_CK = 1'b0 ; +parameter LPTX_DAT_POLAR_LN0 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN1 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN2 = 1'b0 ; +parameter LPTX_DAT_POLAR_LN3 = 1'b0 ; +parameter LPTX_DAT_POLAR_LNCK = 1'b0 ; +parameter LPTX_NIMP_LN0 = 3'b100 ; +parameter LPTX_NIMP_LN1 = 3'b100 ; +parameter LPTX_NIMP_LN2 = 3'b100 ; +parameter LPTX_NIMP_LN3 = 3'b100 ; +parameter LPTX_NIMP_LNCK = 3'b100 ; +parameter LPTX_PIMP_LN0 = 3'b100 ; +parameter LPTX_PIMP_LN1 = 3'b100 ; +parameter LPTX_PIMP_LN2 = 3'b100 ; +parameter LPTX_PIMP_LN3 = 3'b100 ; +parameter LPTX_PIMP_LNCK = 3'b100 ; +parameter MIPI_PMA_DIS_N = 1'b1 ; +parameter PGA_BIAS_LANE0 = 4'b1000 ; +parameter PGA_BIAS_LANE1 = 4'b1000 ; +parameter PGA_BIAS_LANE2 = 4'b1000 ; +parameter PGA_BIAS_LANE3 = 4'b1000 ; +parameter PGA_BIAS_LANECK = 4'b1000 ; +parameter PGA_GAIN_LANE0 = 4'b1000 ; +parameter PGA_GAIN_LANE1 = 4'b1000 ; +parameter PGA_GAIN_LANE2 = 4'b1000 ; +parameter PGA_GAIN_LANE3 = 4'b1000 ; +parameter PGA_GAIN_LANECK = 4'b1000 ; +parameter RX_ODT_TRIM_LANE0 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE1 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE2 = 4'b1000 ; +parameter RX_ODT_TRIM_LANE3 = 4'b1000 ; +parameter RX_ODT_TRIM_LANECK = 4'b1000 ; +parameter SLEWN_CTL_LN0 = 4'b1111 ; +parameter SLEWN_CTL_LN1 = 4'b1111 ; +parameter SLEWN_CTL_LN2 = 4'b1111 ; +parameter SLEWN_CTL_LN3 = 4'b1111 ; +parameter SLEWN_CTL_LNCK = 4'b1111 ; +parameter SLEWP_CTL_LN0 = 4'b1111 ; +parameter SLEWP_CTL_LN1 = 4'b1111 ; +parameter SLEWP_CTL_LN2 = 4'b1111 ; +parameter SLEWP_CTL_LN3 = 4'b1111 ; +parameter SLEWP_CTL_LNCK = 4'b1111 ; +parameter STP_UNIT = 2'b01 ; +parameter TERMN_CTL_LN0 = 4'b1000 ; +parameter TERMN_CTL_LN1 = 4'b1000 ; +parameter TERMN_CTL_LN2 = 4'b1000 ; +parameter TERMN_CTL_LN3 = 4'b1000 ; +parameter TERMN_CTL_LNCK = 4'b1000 ; +parameter TERMP_CTL_LN0 = 4'b1000 ; +parameter TERMP_CTL_LN1 = 4'b1000 ; +parameter TERMP_CTL_LN2 = 4'b1000 ; +parameter TERMP_CTL_LN3 = 4'b1000 ; +parameter TERMP_CTL_LNCK = 4'b1000 ; +parameter TEST_EN_LN0 = 1'b0 ; +parameter TEST_EN_LN1 = 1'b0 ; +parameter TEST_EN_LN2 = 1'b0 ; +parameter TEST_EN_LN3 = 1'b0 ; +parameter TEST_EN_LNCK = 1'b0 ; +parameter TEST_N_IMP_LN0 = 1'b0 ; +parameter TEST_N_IMP_LN1 = 1'b0 ; +parameter TEST_N_IMP_LN2 = 1'b0 ; +parameter TEST_N_IMP_LN3 = 1'b0 ; +parameter TEST_N_IMP_LNCK = 1'b0 ; +parameter TEST_P_IMP_LN0 = 1'b0 ; +parameter TEST_P_IMP_LN1 = 1'b0 ; +parameter TEST_P_IMP_LN2 = 1'b0 ; +parameter TEST_P_IMP_LN3 = 1'b0 ; +parameter TEST_P_IMP_LNCK = 1'b0 ; endmodule module MIPI_CPHY(D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD, D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR, D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA, D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O @@ -2361,13 +2361,13 @@ output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD; output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD; output D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR; output [1:0] D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA; -output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; +output D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O; output HSTX_FIFO_AE, HSTX_FIFO_AF; output HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR; output RX_CLK_MUXED; output TX_CLK_1X_O; output DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C; -output [7:0] MDRP_RDATA; +output [7:0] MDRP_RDATA; inout D0A, D0B, D0C, D1A, D1B, D1C, D2A, D2B, D2C; input D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN; input [41:0] D0LN_HSTX_DATA,D1LN_HSTX_DATA, D2LN_HSTX_DATA; @@ -2381,110 +2381,110 @@ input MDRP_A_INC_I; input MDRP_CLK_I; input [1:0] MDRP_OPCODE_I; input PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX; -input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; +input ARST_RXLN0, ARST_RXLN1, ARST_RXLN2; input ARSTN_TX; -input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; +input RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2; input TX_CLK_1X_I; -input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; -input TXHCLK_EN; +input TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2; +input TXHCLK_EN; input DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2; input GPLL_CK0,GPLL_CK90, GPLL_CK180, GPLL_CK270; -input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; +input HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2; input HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2; -input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; +input LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2; input SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP; -parameter TX_PLLCLK = "NONE"; -parameter D0LN_HS_TX_EN = 1'b1; +parameter TX_PLLCLK = "NONE"; +parameter D0LN_HS_TX_EN = 1'b1; parameter D1LN_HS_TX_EN = 1'b1; parameter D2LN_HS_TX_EN = 1'b1; -parameter D0LN_HS_RX_EN = 1'b1; +parameter D0LN_HS_RX_EN = 1'b1; parameter D1LN_HS_RX_EN = 1'b1; parameter D2LN_HS_RX_EN = 1'b1; -parameter TX_HS_21BIT_MODE = 1'b0; -parameter RX_OUTCLK_SEL = 2'b00; -parameter TX_W_LENDIAN = 1'b1; -parameter CLK_SEL = 2'b00; -parameter LNDIV_RATIO = 4'b0000; -parameter LNDIV_EN = 1'b0; -parameter D0LN_TX_REASGN_A = 2'b00; -parameter D0LN_TX_REASGN_B = 2'b01; -parameter D0LN_TX_REASGN_C = 2'b10; -parameter D0LN_RX_HS_21BIT_MODE = 1'b0; -parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; -parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; -parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; -parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; -parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; -parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; -parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; -parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; -parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; -parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; -parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; -parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; -parameter D0LN_RX_W_LENDIAN = 1'b1; -parameter D0LN_RX_REASGN_A = 2'b00; -parameter D0LN_RX_REASGN_B = 2'b01; -parameter D0LN_RX_REASGN_C = 2'b10; -parameter HSRX_LNSEL = 3'b111; -parameter EQ_RS_LN0 = 3'b001; -parameter EQ_CS_LN0 = 3'b101; -parameter PGA_GAIN_LN0 = 4'b0110; -parameter PGA_BIAS_LN0 = 4'b1000; -parameter EQ_PBIAS_LN0 = 4'b0100; -parameter EQ_ZLD_LN0 = 4'b1000; -parameter D1LN_TX_REASGN_A = 2'b00; -parameter D1LN_TX_REASGN_B = 2'b01; -parameter D1LN_TX_REASGN_C = 2'b10; -parameter D1LN_RX_HS_21BIT_MODE = 1'b0; -parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; -parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; -parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; -parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; -parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; -parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; -parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; -parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; -parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; -parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; -parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; -parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; -parameter D1LN_RX_W_LENDIAN = 1'b1; -parameter D1LN_RX_REASGN_A = 2'b00; -parameter D1LN_RX_REASGN_B = 2'b01; -parameter D1LN_RX_REASGN_C = 2'b10; -parameter EQ_RS_LN1 = 3'b001; -parameter EQ_CS_LN1 = 3'b101; -parameter PGA_GAIN_LN1 = 4'b0110; -parameter PGA_BIAS_LN1 = 4'b1000; -parameter EQ_PBIAS_LN1 = 4'b0100; -parameter EQ_ZLD_LN1 = 4'b1000; -parameter D2LN_TX_REASGN_A = 2'b00; -parameter D2LN_TX_REASGN_B = 2'b01; -parameter D2LN_TX_REASGN_C = 2'b10; -parameter D2LN_RX_HS_21BIT_MODE = 1'b0; -parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; -parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; -parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; -parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; -parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; -parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; -parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; -parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; -parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; -parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; -parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; -parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; -parameter D2LN_RX_W_LENDIAN = 1'b1; -parameter D2LN_RX_REASGN_A = 2'b00; -parameter D2LN_RX_REASGN_B = 2'b01; -parameter D2LN_RX_REASGN_C = 2'b10; -parameter EQ_RS_LN2 = 3'b001; -parameter EQ_CS_LN2 = 3'b101; -parameter PGA_GAIN_LN2 = 4'b0110; -parameter PGA_BIAS_LN2 = 4'b1000; -parameter EQ_PBIAS_LN2 = 4'b0100; -parameter EQ_ZLD_LN2 = 4'b1000; +parameter TX_HS_21BIT_MODE = 1'b0; +parameter RX_OUTCLK_SEL = 2'b00; +parameter TX_W_LENDIAN = 1'b1; +parameter CLK_SEL = 2'b00; +parameter LNDIV_RATIO = 4'b0000; +parameter LNDIV_EN = 1'b0; +parameter D0LN_TX_REASGN_A = 2'b00; +parameter D0LN_TX_REASGN_B = 2'b01; +parameter D0LN_TX_REASGN_C = 2'b10; +parameter D0LN_RX_HS_21BIT_MODE = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D0LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D0LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D0LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D0LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D0LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D0LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D0LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D0LN_RX_W_LENDIAN = 1'b1; +parameter D0LN_RX_REASGN_A = 2'b00; +parameter D0LN_RX_REASGN_B = 2'b01; +parameter D0LN_RX_REASGN_C = 2'b10; +parameter HSRX_LNSEL = 3'b111; +parameter EQ_RS_LN0 = 3'b001; +parameter EQ_CS_LN0 = 3'b101; +parameter PGA_GAIN_LN0 = 4'b0110; +parameter PGA_BIAS_LN0 = 4'b1000; +parameter EQ_PBIAS_LN0 = 4'b0100; +parameter EQ_ZLD_LN0 = 4'b1000; +parameter D1LN_TX_REASGN_A = 2'b00; +parameter D1LN_TX_REASGN_B = 2'b01; +parameter D1LN_TX_REASGN_C = 2'b10; +parameter D1LN_RX_HS_21BIT_MODE = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D1LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D1LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D1LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D1LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D1LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D1LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D1LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D1LN_RX_W_LENDIAN = 1'b1; +parameter D1LN_RX_REASGN_A = 2'b00; +parameter D1LN_RX_REASGN_B = 2'b01; +parameter D1LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN1 = 3'b001; +parameter EQ_CS_LN1 = 3'b101; +parameter PGA_GAIN_LN1 = 4'b0110; +parameter PGA_BIAS_LN1 = 4'b1000; +parameter EQ_PBIAS_LN1 = 4'b0100; +parameter EQ_ZLD_LN1 = 4'b1000; +parameter D2LN_TX_REASGN_A = 2'b00; +parameter D2LN_TX_REASGN_B = 2'b01; +parameter D2LN_TX_REASGN_C = 2'b10; +parameter D2LN_RX_HS_21BIT_MODE = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT0_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT0_H = 7'b1001001; +parameter D2LN_RX_WA_SYNC_PAT0_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT1_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT1_H = 7'b0101001; +parameter D2LN_RX_WA_SYNC_PAT1_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT2_EN = 1'b1; +parameter D2LN_RX_WA_SYNC_PAT2_H = 7'b0011001; +parameter D2LN_RX_WA_SYNC_PAT2_L = 8'b00100100; +parameter D2LN_RX_WA_SYNC_PAT3_EN = 1'b0; +parameter D2LN_RX_WA_SYNC_PAT3_H = 7'b0001001; +parameter D2LN_RX_WA_SYNC_PAT3_L = 8'b00100100; +parameter D2LN_RX_W_LENDIAN = 1'b1; +parameter D2LN_RX_REASGN_A = 2'b00; +parameter D2LN_RX_REASGN_B = 2'b01; +parameter D2LN_RX_REASGN_C = 2'b10; +parameter EQ_RS_LN2 = 3'b001; +parameter EQ_CS_LN2 = 3'b101; +parameter PGA_GAIN_LN2 = 4'b0110; +parameter PGA_BIAS_LN2 = 4'b1000; +parameter EQ_PBIAS_LN2 = 4'b0100; +parameter EQ_ZLD_LN2 = 4'b1000; endmodule module GTR12_QUAD(); @@ -2517,13 +2517,13 @@ input [2:0] RCLKSEL; input [7:0] DLLSTEP; input [7:0] WSTEP; input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD; -output DQSR90, DQSW0, DQSW270; +output DQSR90, DQSW0, DQSW270; output [2:0] RPOINT, WPOINT; output RVALID,RBURST, RFLAG, WFLAG; -parameter FIFO_MODE_SEL = 1'b0; -parameter RD_PNTR = 3'b000; -parameter DQS_MODE = "X1"; -parameter HWL = "false"; +parameter FIFO_MODE_SEL = 1'b0; +parameter RD_PNTR = 3'b000; +parameter DQS_MODE = "X1"; +parameter HWL = "false"; endmodule // Added form adc.v diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index 7e4c3ace2..09fee1953 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -33,7 +33,7 @@ code sigA sigB sigH return sig.extract(0, i); }; auto unextend_unsigned = [](const SigSpec &sig) { - int i; + int i; for (i = GetSize(sig)-1; i > 0; i--) if (sig[i] != SigBit(State::S0)) break; @@ -61,7 +61,7 @@ code sigA sigB sigH if (i == 0) reject; - for (int j = 0, wire_width = 0; j <= i; j++) + for (int j = 0, wire_width = 0; j <= i; j++) if (nusers(O[j]) == 0) wire_width++; else { diff --git a/techlibs/intel_alm/common/abc9_map.v b/techlibs/intel_alm/common/abc9_map.v index 9d11bb240..a0969d44d 100644 --- a/techlibs/intel_alm/common/abc9_map.v +++ b/techlibs/intel_alm/common/abc9_map.v @@ -1,5 +1,5 @@ -// This file exists to map purely-synchronous flops to ABC9 flops, while -// mapping flops with asynchronous-clear as boxes, this is because ABC9 +// This file exists to map purely-synchronous flops to ABC9 flops, while +// mapping flops with asynchronous-clear as boxes, this is because ABC9 // doesn't support asynchronous-clear flops in sequential synthesis. module MISTRAL_FF( diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v index d4ed95173..d525cafd9 100644 --- a/techlibs/intel_alm/common/megafunction_bb.v +++ b/techlibs/intel_alm/common/megafunction_bb.v @@ -12,81 +12,81 @@ module altera_pll parameter operation_mode = "internal feedback", parameter deserialization_factor = 4, parameter data_rate = 0, - + parameter sim_additional_refclk_cycles_to_lock = 0, parameter output_clock_frequency0 = "0 ps", parameter phase_shift0 = "0 ps", parameter duty_cycle0 = 50, - + parameter output_clock_frequency1 = "0 ps", parameter phase_shift1 = "0 ps", parameter duty_cycle1 = 50, - + parameter output_clock_frequency2 = "0 ps", parameter phase_shift2 = "0 ps", parameter duty_cycle2 = 50, - + parameter output_clock_frequency3 = "0 ps", parameter phase_shift3 = "0 ps", parameter duty_cycle3 = 50, - + parameter output_clock_frequency4 = "0 ps", parameter phase_shift4 = "0 ps", parameter duty_cycle4 = 50, - + parameter output_clock_frequency5 = "0 ps", parameter phase_shift5 = "0 ps", parameter duty_cycle5 = 50, - + parameter output_clock_frequency6 = "0 ps", parameter phase_shift6 = "0 ps", parameter duty_cycle6 = 50, - + parameter output_clock_frequency7 = "0 ps", parameter phase_shift7 = "0 ps", parameter duty_cycle7 = 50, - + parameter output_clock_frequency8 = "0 ps", parameter phase_shift8 = "0 ps", parameter duty_cycle8 = 50, - + parameter output_clock_frequency9 = "0 ps", parameter phase_shift9 = "0 ps", - parameter duty_cycle9 = 50, + parameter duty_cycle9 = 50, + - parameter output_clock_frequency10 = "0 ps", parameter phase_shift10 = "0 ps", parameter duty_cycle10 = 50, - + parameter output_clock_frequency11 = "0 ps", parameter phase_shift11 = "0 ps", parameter duty_cycle11 = 50, - + parameter output_clock_frequency12 = "0 ps", parameter phase_shift12 = "0 ps", parameter duty_cycle12 = 50, - + parameter output_clock_frequency13 = "0 ps", parameter phase_shift13 = "0 ps", parameter duty_cycle13 = 50, - + parameter output_clock_frequency14 = "0 ps", parameter phase_shift14 = "0 ps", parameter duty_cycle14 = 50, - + parameter output_clock_frequency15 = "0 ps", parameter phase_shift15 = "0 ps", parameter duty_cycle15 = 50, - + parameter output_clock_frequency16 = "0 ps", parameter phase_shift16 = "0 ps", parameter duty_cycle16 = 50, - + parameter output_clock_frequency17 = "0 ps", parameter phase_shift17 = "0 ps", parameter duty_cycle17 = 50, - + parameter clock_name_0 = "", parameter clock_name_1 = "", parameter clock_name_2 = "", @@ -115,126 +115,126 @@ module altera_pll parameter n_cnt_lo_div = 1, parameter n_cnt_bypass_en = "false", parameter n_cnt_odd_div_duty_en = "false", - parameter c_cnt_hi_div0 = 1, + parameter c_cnt_hi_div0 = 1, parameter c_cnt_lo_div0 = 1, parameter c_cnt_bypass_en0 = "false", parameter c_cnt_in_src0 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en0 = "false", parameter c_cnt_prst0 = 1, parameter c_cnt_ph_mux_prst0 = 0, - parameter c_cnt_hi_div1 = 1, + parameter c_cnt_hi_div1 = 1, parameter c_cnt_lo_div1 = 1, parameter c_cnt_bypass_en1 = "false", parameter c_cnt_in_src1 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en1 = "false", parameter c_cnt_prst1 = 1, parameter c_cnt_ph_mux_prst1 = 0, - parameter c_cnt_hi_div2 = 1, + parameter c_cnt_hi_div2 = 1, parameter c_cnt_lo_div2 = 1, parameter c_cnt_bypass_en2 = "false", parameter c_cnt_in_src2 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en2 = "false", parameter c_cnt_prst2 = 1, parameter c_cnt_ph_mux_prst2 = 0, - parameter c_cnt_hi_div3 = 1, + parameter c_cnt_hi_div3 = 1, parameter c_cnt_lo_div3 = 1, parameter c_cnt_bypass_en3 = "false", parameter c_cnt_in_src3 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en3 = "false", parameter c_cnt_prst3 = 1, parameter c_cnt_ph_mux_prst3 = 0, - parameter c_cnt_hi_div4 = 1, + parameter c_cnt_hi_div4 = 1, parameter c_cnt_lo_div4 = 1, parameter c_cnt_bypass_en4 = "false", parameter c_cnt_in_src4 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en4 = "false", parameter c_cnt_prst4 = 1, parameter c_cnt_ph_mux_prst4 = 0, - parameter c_cnt_hi_div5 = 1, + parameter c_cnt_hi_div5 = 1, parameter c_cnt_lo_div5 = 1, parameter c_cnt_bypass_en5 = "false", parameter c_cnt_in_src5 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en5 = "false", parameter c_cnt_prst5 = 1, parameter c_cnt_ph_mux_prst5 = 0, - parameter c_cnt_hi_div6 = 1, + parameter c_cnt_hi_div6 = 1, parameter c_cnt_lo_div6 = 1, parameter c_cnt_bypass_en6 = "false", parameter c_cnt_in_src6 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en6 = "false", parameter c_cnt_prst6 = 1, parameter c_cnt_ph_mux_prst6 = 0, - parameter c_cnt_hi_div7 = 1, + parameter c_cnt_hi_div7 = 1, parameter c_cnt_lo_div7 = 1, parameter c_cnt_bypass_en7 = "false", parameter c_cnt_in_src7 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en7 = "false", parameter c_cnt_prst7 = 1, parameter c_cnt_ph_mux_prst7 = 0, - parameter c_cnt_hi_div8 = 1, + parameter c_cnt_hi_div8 = 1, parameter c_cnt_lo_div8 = 1, parameter c_cnt_bypass_en8 = "false", parameter c_cnt_in_src8 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en8 = "false", parameter c_cnt_prst8 = 1, parameter c_cnt_ph_mux_prst8 = 0, - parameter c_cnt_hi_div9 = 1, + parameter c_cnt_hi_div9 = 1, parameter c_cnt_lo_div9 = 1, parameter c_cnt_bypass_en9 = "false", parameter c_cnt_in_src9 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en9 = "false", parameter c_cnt_prst9 = 1, parameter c_cnt_ph_mux_prst9 = 0, - parameter c_cnt_hi_div10 = 1, + parameter c_cnt_hi_div10 = 1, parameter c_cnt_lo_div10 = 1, parameter c_cnt_bypass_en10 = "false", parameter c_cnt_in_src10 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en10 = "false", parameter c_cnt_prst10 = 1, parameter c_cnt_ph_mux_prst10 = 0, - parameter c_cnt_hi_div11 = 1, + parameter c_cnt_hi_div11 = 1, parameter c_cnt_lo_div11 = 1, parameter c_cnt_bypass_en11 = "false", parameter c_cnt_in_src11 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en11 = "false", parameter c_cnt_prst11 = 1, parameter c_cnt_ph_mux_prst11 = 0, - parameter c_cnt_hi_div12 = 1, + parameter c_cnt_hi_div12 = 1, parameter c_cnt_lo_div12 = 1, parameter c_cnt_bypass_en12 = "false", parameter c_cnt_in_src12 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en12 = "false", parameter c_cnt_prst12 = 1, parameter c_cnt_ph_mux_prst12 = 0, - parameter c_cnt_hi_div13 = 1, + parameter c_cnt_hi_div13 = 1, parameter c_cnt_lo_div13 = 1, parameter c_cnt_bypass_en13 = "false", parameter c_cnt_in_src13 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en13 = "false", parameter c_cnt_prst13 = 1, parameter c_cnt_ph_mux_prst13 = 0, - parameter c_cnt_hi_div14 = 1, + parameter c_cnt_hi_div14 = 1, parameter c_cnt_lo_div14 = 1, parameter c_cnt_bypass_en14 = "false", parameter c_cnt_in_src14 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en14 = "false", parameter c_cnt_prst14 = 1, parameter c_cnt_ph_mux_prst14 = 0, - parameter c_cnt_hi_div15 = 1, + parameter c_cnt_hi_div15 = 1, parameter c_cnt_lo_div15 = 1, parameter c_cnt_bypass_en15 = "false", parameter c_cnt_in_src15 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en15 = "false", parameter c_cnt_prst15 = 1, parameter c_cnt_ph_mux_prst15 = 0, - parameter c_cnt_hi_div16 = 1, + parameter c_cnt_hi_div16 = 1, parameter c_cnt_lo_div16 = 1, parameter c_cnt_bypass_en16 = "false", parameter c_cnt_in_src16 = "ph_mux_clk", parameter c_cnt_odd_div_duty_en16 = "false", parameter c_cnt_prst16 = 1, parameter c_cnt_ph_mux_prst16 = 0, - parameter c_cnt_hi_div17 = 1, + parameter c_cnt_hi_div17 = 1, parameter c_cnt_lo_div17 = 1, parameter c_cnt_bypass_en17 = "false", parameter c_cnt_in_src17 = "ph_mux_clk", @@ -260,9 +260,9 @@ module altera_pll parameter pll_clkin_1_src = "clk_0", parameter pll_clk_loss_sw_en = "false", parameter pll_auto_clk_sw_en = "false", - parameter pll_manu_clk_sw_en = "false", + parameter pll_manu_clk_sw_en = "false", parameter pll_clk_sw_dly = 0, - parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", + parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss" ) ( //input @@ -279,7 +279,7 @@ module altera_pll input extswitch, input adjpllin, input cclk, - + //output output [ number_of_clocks -1 : 0] outclk, output fboutclk, diff --git a/techlibs/lattice/cells_sim_nexus.v b/techlibs/lattice/cells_sim_nexus.v index d1c8bf0d7..49111a7ad 100644 --- a/techlibs/lattice/cells_sim_nexus.v +++ b/techlibs/lattice/cells_sim_nexus.v @@ -446,7 +446,7 @@ module OXIDE_DSP_SIM #( input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT, output wire [Z_WIDTH-1:0] Z ); - + localparam M_WIDTH = (A_WIDTH+B_WIDTH); /******** REGISTERS ********/ @@ -511,7 +511,7 @@ module OXIDE_DSP_SIM #( if (ADDSUB_USED) begin assign pipe_d = mult_m; assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q}; - assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext); + assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext); end else begin assign z_d = mult_m; end diff --git a/techlibs/lattice/dsp_map_nexus.v b/techlibs/lattice/dsp_map_nexus.v index 61d2d96a8..a2ee71a21 100644 --- a/techlibs/lattice/dsp_map_nexus.v +++ b/techlibs/lattice/dsp_map_nexus.v @@ -94,10 +94,10 @@ module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [ .REGINPUTC("BYPASS"), .REGOUTPUT("BYPASS") ) _TECHMAP_REPLACE_ ( - .A(A), - .B(B), + .A(A), + .B(B), .C({6'b0, C}), - .SIGNED(A_SIGNED ? 1'b1 : 1'b0), + .SIGNED(A_SIGNED ? 1'b1 : 1'b0), .ADDSUB(SUBTRACT ? 1'b1 : 1'b0), .Z(Y) ); diff --git a/techlibs/lattice/lattice_dsp_nexus.cc b/techlibs/lattice/lattice_dsp_nexus.cc index 083af2595..442182f22 100644 --- a/techlibs/lattice/lattice_dsp_nexus.cc +++ b/techlibs/lattice/lattice_dsp_nexus.cc @@ -25,8 +25,8 @@ struct LatticeDspNexusPass : public Pass { for (auto module : design->selected_modules()) { lattice_dsp_nexus_pm pm(module, module->cells()); - - pm.run_nexus_mac9_4lane(); + + pm.run_nexus_mac9_4lane(); pm.run_nexus_mac18(); pm.run_nexus_preadd18(); } diff --git a/techlibs/lattice/lattice_dsp_nexus.pmg b/techlibs/lattice/lattice_dsp_nexus.pmg index 8c16891b1..2ad38840b 100644 --- a/techlibs/lattice/lattice_dsp_nexus.pmg +++ b/techlibs/lattice/lattice_dsp_nexus.pmg @@ -38,7 +38,7 @@ code mac->setPort(\B, port(mul, \B)); mac->setPort(\C, port(add, add_C)); mac->setPort(\Y, port(add, \Y)); - mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); + mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED)); mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0); autoremove(mul); @@ -178,9 +178,9 @@ code { Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE"); - - auto ext9 = [&](SigSpec s) { - s.extend_u0(9, is_signed); + + auto ext9 = [&](SigSpec s) { + s.extend_u0(9, is_signed); return s; }; diff --git a/techlibs/lattice/lattice_gsr.cc b/techlibs/lattice/lattice_gsr.cc index a60b54b16..f7d40c056 100644 --- a/techlibs/lattice/lattice_gsr.cc +++ b/techlibs/lattice/lattice_gsr.cc @@ -83,12 +83,12 @@ struct LatticeGsrPass : public Pass { { if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") continue; - + bool gsren = found_gsr; if (cell->get_bool_attribute(ID(nogsr))) gsren = false; cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED")); - + } if (!found_gsr) diff --git a/techlibs/microchip/LSRAM.txt b/techlibs/microchip/LSRAM.txt index 9c22e4f30..3668c1b71 100644 --- a/techlibs/microchip/LSRAM.txt +++ b/techlibs/microchip/LSRAM.txt @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,9 +28,9 @@ ram block $__LSRAM_TDP_ { init any; # port A and port B are allowed to have different widths, but they MUST have - # WIDTH values of the same set. + # WIDTH values of the same set. # Example: Port A has a Data Width of 1. Then Port B's Data Width must be either - # 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set). + # 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set). # WIDTH_1 = {1, 2, 4, 8, 16} # WIDTH_2 = {5, 10, 20} @@ -38,7 +38,7 @@ ram block $__LSRAM_TDP_ { # "byte" must be larger than width, or width must be a multipler of "byte" # if "byte" > WIDTH, a single enable wire is inferred # otherwise, WIDTH/byte number of enable wires are inferred - # + # # WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire # WIDTH = {16, 20} requires 2 enable wire @@ -58,7 +58,7 @@ ram block $__LSRAM_TDP_ { byte 8; } option "WIDTH_CONFIG" "ALIGN" { - + # Data-Width| Address bits # 5 | 12 # 10 | 11 @@ -72,14 +72,14 @@ ram block $__LSRAM_TDP_ { widths 5 10 20 per_port; byte 10; } - - + + port srsw "A" "B" { # read & write width must be same width tied; - + # clock polarity is rising clock posedge; @@ -101,8 +101,8 @@ ram block $__LSRAM_TDP_ { rdwr no_change; # Write transparency: - # For write ports, define behaviour when another synchronous read port - # reads from the same memory cell that said write port is writing to at the same time. + # For write ports, define behaviour when another synchronous read port + # reads from the same memory cell that said write port is writing to at the same time. wrtrans all old; } portoption "WRITE_MODE" "WRITE_FIRST" { @@ -123,9 +123,9 @@ ram block $__LSRAM_TDP_ { # two-port configuration ram block $__LSRAM_SDP_ { - + # since two-port configuration is dedicated for wide-read/write, - # we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs + # we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs # inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should # be less than 2 TDP. cost 129; @@ -147,10 +147,10 @@ ram block $__LSRAM_SDP_ { # width = 32, byte-write size is 8, ignore other widths byte 8; - + } option "WIDTH_CONFIG" "ALIGN" { - + # Data-Width| Address bits # 5 | 12 # 10 | 11 @@ -166,7 +166,7 @@ ram block $__LSRAM_SDP_ { port sw "W" { # only consider wide write - + option "WIDTH_CONFIG" "REGULAR" width 32; option "WIDTH_CONFIG" "ALIGN" width 40; @@ -174,7 +174,7 @@ ram block $__LSRAM_SDP_ { # only simple write supported for two-port mode wrtrans all old; - + optional; } port sr "R" { diff --git a/techlibs/microchip/LSRAM_map.v b/techlibs/microchip/LSRAM_map.v index c84b5dd19..cfe765a1a 100644 --- a/techlibs/microchip/LSRAM_map.v +++ b/techlibs/microchip/LSRAM_map.v @@ -71,7 +71,7 @@ parameter PORT_A_WR_USED = 0; wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000; wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000; -// wires for write data +// wires for write data generate wire [19:0] A_write_data; wire [19:0] B_write_data; @@ -115,9 +115,9 @@ wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 : (PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100; // write modes -wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : +wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10; -wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : +wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 : PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10; RAM1K20 #( @@ -155,7 +155,7 @@ RAM1K20 #( .B_DOUT_ARST_N(1'b1), // Disable ECC for TDP - .ECC_EN(1'b0), + .ECC_EN(1'b0), .ECC_BYPASS(1'b1), .BUSY_FB(1'b0) @@ -212,7 +212,7 @@ generate wire [1:0] A_write_EN; wire [1:0] B_write_EN; - // write port (A provides MSB) + // write port (A provides MSB) if (PORT_W_WIDTH == 32) begin assign B_write_data[3:0] = PORT_W_WR_DATA[3:0]; @@ -232,7 +232,7 @@ generate assign A_write_data[9] = 1'b0; assign A_write_data[14] = 1'b0; assign A_write_data[19] = 1'b0; - + end else if (PORT_W_WIDTH == 40) begin assign B_write_data = PORT_W_WR_DATA[19:0]; assign A_write_data = PORT_W_WR_DATA[39:20]; @@ -265,7 +265,7 @@ endgenerate wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 : (PORT_R_WIDTH == 2) ? 3'b001 : (PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 : - (PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : + (PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 : (PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101; wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 : (PORT_W_WIDTH == 2) ? 3'b001 : @@ -311,7 +311,7 @@ RAM1K20 #( .B_DOUT_ARST_N(1'b1), // Disable ECC for SDP - .ECC_EN(1'b0), + .ECC_EN(1'b0), .ECC_BYPASS(1'b1), .BUSY_FB(1'b0) ); diff --git a/techlibs/microchip/arith_map.v b/techlibs/microchip/arith_map.v index 3eb2e2f2c..7e77de218 100644 --- a/techlibs/microchip/arith_map.v +++ b/techlibs/microchip/arith_map.v @@ -48,7 +48,7 @@ module \$__microchip_XOR8_ (A, Y); XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y)); - + endmodule (* techmap_celltype = "$alu" *) diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v index 6fc3094b2..6d5e09be4 100644 --- a/techlibs/microchip/cells_sim.v +++ b/techlibs/microchip/cells_sim.v @@ -155,7 +155,7 @@ endmodule // sequential elements -// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow +// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow // see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html (* abc9_flop, lib_whitebox *) @@ -196,7 +196,7 @@ module MICROCHIP_SYNC_RESET_DFF( always @(posedge CLK) begin if (En == 1) begin - if (Reset == 0) + if (Reset == 0) Q <= 0; else Q <= D; @@ -258,7 +258,7 @@ module ARI1 ( (* abc9_carry *) output FCO, - input A, B, C, D, + input A, B, C, D, output Y, S ); parameter [19:0] INIT = 20'h0; @@ -271,9 +271,9 @@ module ARI1 ( wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17]; wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0); assign FCO = P ? FCI : G; - + specify - //pin to pin path delay + //pin to pin path delay (A => Y ) = 472; (B => Y ) = 407; (C => Y ) = 238; @@ -647,7 +647,7 @@ module RAM1K20 ( input B_DOUT_EN, input B_DOUT_SRST_N, input B_DOUT_ARST_N, - input ECC_EN, + input ECC_EN, input ECC_BYPASS, output SB_CORRECT, output DB_DETECT, @@ -684,7 +684,7 @@ module RAM64x12 ( input R_ADDR_EN, input R_ADDR_SL_N, input R_ADDR_SD, - input R_ADDR_AL_N, + input R_ADDR_AL_N, input R_ADDR_AD_N, input BLK_EN, output [11:0] R_DATA, diff --git a/techlibs/microchip/microchip_dsp.pmg b/techlibs/microchip/microchip_dsp.pmg index 2573135ee..4141d9961 100644 --- a/techlibs/microchip/microchip_dsp.pmg +++ b/techlibs/microchip/microchip_dsp.pmg @@ -1,7 +1,7 @@ // ISC License -// +// // Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. @@ -16,12 +16,12 @@ // This file describes the main pattern matcher setup (of three total) that -// forms the `microchip_dsp` pass described in microchip_dsp.cc +// forms the `microchip_dsp` pass described in microchip_dsp.cc // At a high level, it works as follows: // ( 1) Starting from a DSP cell. Capture DSP configurations as states // ( 2) Match for pre-adder // ( 3) Match for post-adder -// ( 4) Match register 'A', 'B', 'D', 'P' +// ( 4) Match register 'A', 'B', 'D', 'P' // ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder. // This indicates an accumulator situation like the ASCII diagram below: // +--------------------------------+ @@ -110,21 +110,21 @@ code bypassA bypassB bypassC bypassD bypassPASUB bypassP endcode // (2) Match for pre-adder -// +// code sigA sigB sigD preAdderStatic moveBtoA subpattern(preAddMatching); preAdderStatic = u_preAdderStatic; moveBtoA = false; if (preAdderStatic) { - + if (port(preAdderStatic, \Y) == sigA) { //used for packing moveBtoA = true; - // sigA should be the input to the multiplier without the preAdd. sigB and sigD should be - //the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then + // sigA should be the input to the multiplier without the preAdd. sigB and sigD should be + //the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then // we basically swap it. sigA = sigB; } @@ -144,7 +144,7 @@ code postAdderStatic sigP sigC if (postAdderStatic) { //sigC will be whichever input to the postAdder that is NOT from the multiplier - // u_postAddAB is the input to the postAdder from the multiplier + // u_postAddAB is the input to the postAdder from the multiplier sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A); sigP = port(postAdderStatic, \Y); } @@ -269,7 +269,7 @@ code if (postAdd) { if (postAdd->type.in($sub) && postAddAB == \A) { - // if $sub, the multiplier output must match to $sub.B, otherwise no match + // if $sub, the multiplier output must match to $sub.B, otherwise no match } else { u_postAddAB = postAddAB; u_postAdderStatic = postAdd; @@ -286,11 +286,11 @@ endcode subpattern preAddMatching arg sigA sigB sigD bypassB bypassD bypassPASUB -code +code u_preAdderStatic = nullptr; // Ensure that preAdder not already used - // Assume we can inspect port D to see if its all zeros. + // Assume we can inspect port D to see if its all zeros. if (!(sigD.empty() || sigD.is_fully_zero())) reject; if (!bypassB.is_fully_ones()) reject; if (!bypassD.is_fully_ones()) reject; diff --git a/techlibs/microchip/microchip_dsp_CREG.pmg b/techlibs/microchip/microchip_dsp_CREG.pmg index d1b15d460..a89c0a858 100644 --- a/techlibs/microchip/microchip_dsp_CREG.pmg +++ b/techlibs/microchip/microchip_dsp_CREG.pmg @@ -1,7 +1,7 @@ // ISC License -// +// // Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. @@ -164,5 +164,5 @@ code argQ argQ = Q; dffD.replace(argQ, D); } - + endcode diff --git a/techlibs/microchip/microchip_dsp_cascade.pmg b/techlibs/microchip/microchip_dsp_cascade.pmg index d26fdf784..b3d8ea7dc 100644 --- a/techlibs/microchip/microchip_dsp_cascade.pmg +++ b/techlibs/microchip/microchip_dsp_cascade.pmg @@ -1,7 +1,7 @@ // ISC License -// +// // Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -// +// // Permission to use, copy, modify, and/or distribute this software for any // purpose with or without fee is hereby granted, provided that the above // copyright notice and this permission notice appear in all copies. @@ -18,10 +18,10 @@ // This file describes the third of three pattern matcher setups that // forms the `microchip_dsp` pass described in microchip_dsp.cc // At a high level, it works as follows: -// (1) Starting from a DSP cell that +// (1) Starting from a DSP cell that // (a) CDIN_FDBK_SEL is set to default "00" // (b) doesn't already use the 'PCOUT' port -// (2) Match another DSP cell that +// (2) Match another DSP cell that // (a) does not have the CREG enabled, // (b) 'C' port is driven by the 'P' output of the previous DSP cell // (c) has its 'PCIN' port unused @@ -72,7 +72,7 @@ code }; endcode -// (1) Starting from a DSP cell that +// (1) Starting from a DSP cell that // (a) CDIN_FDBK_SEL is set to default "00" // (b) doesn't already use the 'PCOUT' port match first @@ -133,7 +133,7 @@ finally { dsp_pcin->setPort(\ARSHFT17, State::S1); } - + log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin); @@ -154,7 +154,7 @@ subpattern tail arg first arg next -// (2) Match another DSP cell that +// (2) Match another DSP cell that // (a) does not have the CREG enabled, // (b) 'C' port is driven by the 'P' output of the previous DSP cell // (c) has its 'PCIN' port unused @@ -213,7 +213,7 @@ code chain.emplace_back(next, shift); visited.insert(next); - + SigSpec sigC = unextend(port(next, \C)); // Make sure driverDSP.P === DSP.C @@ -231,6 +231,6 @@ finally visited.erase(next); chain.pop_back(); } - + endcode diff --git a/techlibs/microchip/polarfire_dsp_map.v b/techlibs/microchip/polarfire_dsp_map.v index b416841fb..b0cb50d07 100644 --- a/techlibs/microchip/polarfire_dsp_map.v +++ b/techlibs/microchip/polarfire_dsp_map.v @@ -27,9 +27,9 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); // For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide: // https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf MACC_PA _TECHMAP_REPLACE_ ( - .DOTP(1'b0), - .SIMD(1'b0), - .OVFL_CARRYOUT_SEL(1'b0), + .DOTP(1'b0), + .SIMD(1'b0), + .OVFL_CARRYOUT_SEL(1'b0), .AL_N(1'b1), .A(A), @@ -47,7 +47,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .D_ARST_N(1'b1), .D_SRST_N(1'b1), .D_EN(1'b1), - + .CARRYIN(1'b0), .C(48'b0), .C_BYPASS(1'b1), @@ -55,7 +55,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); .C_SRST_N(1'b1), .C_EN(1'b1), - + .P(P_48), .P_BYPASS(1'b1), diff --git a/techlibs/microchip/uSRAM.txt b/techlibs/microchip/uSRAM.txt index 10f9a1435..8da9c52ed 100644 --- a/techlibs/microchip/uSRAM.txt +++ b/techlibs/microchip/uSRAM.txt @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -30,10 +30,10 @@ ram block $__uSRAM_AR_ { port sw "W" { clock posedge; - # collision not supported, but write takes precedence and read data is invalid while writing to + # collision not supported, but write takes precedence and read data is invalid while writing to # the same address wrtrans all new; - + optional; } port ar "R" { @@ -57,7 +57,7 @@ widths 12 per_port; # collision not supported wrtrans all new; - + optional; } port sr "R" { diff --git a/techlibs/microchip/uSRAM_map.v b/techlibs/microchip/uSRAM_map.v index 81c76f0f1..8fafb1ece 100644 --- a/techlibs/microchip/uSRAM_map.v +++ b/techlibs/microchip/uSRAM_map.v @@ -48,7 +48,7 @@ RAM64x12 #( .R_ADDR_EN(1'b0), .R_ADDR_SL_N(1'b1), .R_ADDR_SD(1'b0), - .R_ADDR_AL_N(1'b1), + .R_ADDR_AL_N(1'b1), .R_ADDR_AD_N(1'b0), .BLK_EN(PORT_R_USED ? 1'b1 : 1'b0), .R_DATA(PORT_R_RD_DATA), @@ -103,7 +103,7 @@ RAM64x12 #( .R_ADDR_EN(PORT_R_RD_EN), .R_ADDR_SL_N(1'b1), .R_ADDR_SD(1'b0), - .R_ADDR_AL_N(1'b1), + .R_ADDR_AL_N(1'b1), .R_ADDR_AD_N(1'b0), .BLK_EN(PORT_R_USED ? 1'b1 : 1'b0), .R_DATA(PORT_R_RD_DATA), diff --git a/techlibs/nanoxplore/brams_init.vh b/techlibs/nanoxplore/brams_init.vh index b93839c5a..8df808d88 100644 --- a/techlibs/nanoxplore/brams_init.vh +++ b/techlibs/nanoxplore/brams_init.vh @@ -3,7 +3,7 @@ function [409600-1:0] bram_init_to_string; input integer blocks; input integer width; reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas - reg [24-1:0] temp2; + reg [24-1:0] temp2; integer i; integer j; begin diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index e11aaabee..1c83fb2c0 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -172,15 +172,15 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 end wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; - wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, - O27, O26, O25, O24, O23, O22, O21, O20, O19, + wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28, + O27, O26, O25, O24, O23, O22, O21, O20, O19, O18, O17, O16, O15, O14, O13, O12, O11, O10, O9, O8, O7, O6, O5, O4, O3, O2, O1 }; wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28, I27, I26, I25, I24, I23, I22, I21, I20, I19, I18, I17, I16, I15, I14, I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1 }; - generate + generate if (mode==0) begin assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }]; end @@ -196,7 +196,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 else if (mode==4) begin assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] }; end - else + else $error("Unknown NX_RFB_U mode"); endgenerate diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc index 6e6a96035..cb0405052 100644 --- a/techlibs/nanoxplore/nx_carry.cc +++ b/techlibs/nanoxplore/nx_carry.cc @@ -52,7 +52,7 @@ static void nx_carry_chain(Module *module) { if (cell->type == ID(NX_CY_1BIT)) { if (cell->getParam(ID(first)).as_int() == 0) continue; - + vector chain; Cell *current = cell; chain.push_back(current); @@ -124,8 +124,8 @@ static void nx_carry_chain(Module *module) } cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A)))); cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B)))); - - if (c.second.at(i)->hasPort(ID(S))) + + if (c.second.at(i)->hasPort(ID(S))) cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S))); j = (j + 1) % 4; @@ -148,7 +148,7 @@ struct NXCarryPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing NX_CARRY pass.\n"); - + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/techlibs/nanoxplore/rf_rams_map_l.v b/techlibs/nanoxplore/rf_rams_map_l.v index e529ce1e1..d712a8572 100644 --- a/techlibs/nanoxplore/rf_rams_map_l.v +++ b/techlibs/nanoxplore/rf_rams_map_l.v @@ -2,7 +2,7 @@ module $__NX_RFB_L_ ( input PORT_W_CLK, input PORT_W_WR_EN, input [5:0] PORT_W_ADDR, - input [15:0] PORT_W_WR_DATA, + input [15:0] PORT_W_WR_DATA, input PORT_R_CLK, input PORT_R_RD_EN, input [5:0] PORT_R_ADDR, diff --git a/techlibs/nanoxplore/rf_rams_map_m.v b/techlibs/nanoxplore/rf_rams_map_m.v index a64dc3388..053797a43 100644 --- a/techlibs/nanoxplore/rf_rams_map_m.v +++ b/techlibs/nanoxplore/rf_rams_map_m.v @@ -2,7 +2,7 @@ module $__NX_RFB_M_ ( input PORT_W_CLK, input PORT_W_WR_EN, input [5:0] PORT_W_ADDR, - input [15:0] PORT_W_WR_DATA, + input [15:0] PORT_W_WR_DATA, input PORT_R_CLK, input PORT_R_RD_EN, input [5:0] PORT_R_ADDR, diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 0b87c98c7..525985677 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -1,8 +1,8 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2024 Hannah Ravensloft - * Copyright (C) 2024 Miodrag Milanovic + * Copyright (C) 2024 Hannah Ravensloft + * Copyright (C) 2024 Miodrag Milanovic * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -217,7 +217,7 @@ struct SynthNanoXplorePass : public ScriptPass postfix = "_m"; } else if (family == "large") { postfix = "_l"; - } else + } else log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family); if (!design->full_selection()) diff --git a/techlibs/quicklogic/pp3/abc9_map.v b/techlibs/quicklogic/pp3/abc9_map.v index 46c11d675..42434a3af 100644 --- a/techlibs/quicklogic/pp3/abc9_map.v +++ b/techlibs/quicklogic/pp3/abc9_map.v @@ -1,5 +1,5 @@ -// This file exists to map purely-synchronous flops to ABC9 flops, while -// mapping flops with asynchronous-set/clear as boxes, this is because ABC9 +// This file exists to map purely-synchronous flops to ABC9 flops, while +// mapping flops with asynchronous-set/clear as boxes, this is because ABC9 // doesn't support asynchronous-set/clear flops in sequential synthesis. module dffepc ( diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc index eeb06060e..c2fbed4fd 100644 --- a/techlibs/quicklogic/ql_bram_merge.cc +++ b/techlibs/quicklogic/ql_bram_merge.cc @@ -180,7 +180,7 @@ struct QlBramMergeWorker { }; struct QlBramMergePass : public Pass { - + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} void help() override diff --git a/techlibs/quicklogic/ql_bram_types.cc b/techlibs/quicklogic/ql_bram_types.cc index 5e423b18d..fda90b203 100644 --- a/techlibs/quicklogic/ql_bram_types.cc +++ b/techlibs/quicklogic/ql_bram_types.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct QlBramTypesPass : public Pass { - + QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {} void help() override @@ -81,7 +81,7 @@ struct QlBramTypesPass : public Pass { { if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS))) continue; - + RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS)); bool split = mode_bits.extract(80).as_bool(); @@ -139,7 +139,7 @@ struct QlBramTypesPass : public Pass { type += "SYNC_"; else type += "ASYNC_"; - } else + } else type += "_BRAM_"; if (split) { diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index 0035deccf..f2b8113d1 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -15,7 +15,7 @@ // SPDX-License-Identifier: Apache-2.0 module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA, - PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); + PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); parameter INIT = 0; diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index e65be1c58..23997fc02 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -342,7 +342,7 @@ struct SynthQuickLogicPass : public ScriptPass { run("clean"); run("opt_lut"); } - + if (check_label("iomap", "(for qlf_k6n10f, skip if -noioff)") && (family == "qlf_k6n10f" || help_mode)) { if (ioff || help_mode) { run("ql_ioff"); diff --git a/techlibs/sf2/NOTES.txt b/techlibs/sf2/NOTES.txt index 6204d8fee..0e4fdb16b 100644 --- a/techlibs/sf2/NOTES.txt +++ b/techlibs/sf2/NOTES.txt @@ -51,8 +51,8 @@ Then you can use the normal flow. This is done by the run_yosys.tcl: ----------- run_yosys.tcl -------------- open_project -file {./top.prjx} -run_tool -name {PLACEROUTE} -run_tool -name {PROGRAMDEVICE} +run_tool -name {PLACEROUTE} +run_tool -name {PROGRAMDEVICE} ----------------------------------------- diff --git a/techlibs/xilinx/tests/test_dsp_model.v b/techlibs/xilinx/tests/test_dsp_model.v index db012f169..0bf4ea18c 100644 --- a/techlibs/xilinx/tests/test_dsp_model.v +++ b/techlibs/xilinx/tests/test_dsp_model.v @@ -178,7 +178,7 @@ module testbench; {RSTA, RSTALLCARRYIN, RSTALUMODE, RSTB, RSTC, RSTCTRL, RSTD, RSTINMODE, RSTM, RSTP} = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; {ALUMODE, INMODE} = $urandom; CARRYINSEL = $urandom & $urandom & $urandom; - OPMODE = $urandom; + OPMODE = $urandom; if ($urandom & 1'b1) OPMODE[3:0] = 4'b0101; // test multiply more than other modes {CARRYCASCIN, CARRYIN, MULTSIGNIN} = $urandom; diff --git a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v index 853ba6254..a584766b8 100644 --- a/tests/arch/analogdevices/asym_ram_sdp_read_wider.v +++ b/tests/arch/analogdevices/asym_ram_sdp_read_wider.v @@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, parameter WIDTHA = 4; parameter SIZEA = 1024; parameter ADDRWIDTHA = 10; - + parameter WIDTHB = 16; parameter SIZEB = 256; parameter ADDRWIDTHB = 8; diff --git a/tests/arch/analogdevices/attributes_test.ys b/tests/arch/analogdevices/attributes_test.ys index 03d6decff..a6b2242ff 100644 --- a/tests/arch/analogdevices/attributes_test.ys +++ b/tests/arch/analogdevices/attributes_test.ys @@ -4,7 +4,7 @@ hierarchy -top block_ram synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module # select -assert-count 1 t:RBRAM2 # This currently infers LUTRAM because BRAM is expensive. - + # Check that distributed memory without parameters is not modified design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -13,7 +13,7 @@ synth_analogdevices -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module select -assert-count 8 t:RAMS64X1 select -assert-count 8 t:FFRE - + # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -22,7 +22,7 @@ synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 64 t:RAMS64X1 select -assert-count 4 t:FFRE - + # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -30,7 +30,7 @@ setattr -set logic_block 1 block_ram/m:* synth_analogdevices -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RBRAM2 - + # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v diff --git a/tests/arch/analogdevices/blockram.ys b/tests/arch/analogdevices/blockram.ys index f6efa5ba8..fb829abaa 100644 --- a/tests/arch/analogdevices/blockram.ys +++ b/tests/arch/analogdevices/blockram.ys @@ -54,7 +54,7 @@ select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp @@ -62,7 +62,7 @@ select -assert-count 1 t:RBRAM2 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_analogdevices -top sync_ram_sdp -noiopad cd sync_ram_sdp diff --git a/tests/arch/analogdevices/bug1598.ys b/tests/arch/analogdevices/bug1598.ys index a4884510d..1397b7506 100644 --- a/tests/arch/analogdevices/bug1598.ys +++ b/tests/arch/analogdevices/bug1598.ys @@ -3,14 +3,14 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc -equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices +equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices diff --git a/tests/arch/analogdevices/dsp_abc9.ys b/tests/arch/analogdevices/dsp_abc9.ys index ad27a9d6e..99a057fe4 100644 --- a/tests/arch/analogdevices/dsp_abc9.ys +++ b/tests/arch/analogdevices/dsp_abc9.ys @@ -17,7 +17,7 @@ module top(input signed [24:0] A, input signed [17:0] B, output [47:0] P); assign P = A * B; endmodule EOT -synth_analogdevices +synth_analogdevices techmap -autoproc -wb -map +/analogdevices/cells_sim.v opt -full -fine select -assert-count 2 t:$mul @@ -34,7 +34,7 @@ EOT async2sync techmap -map +/analogdevices/dsp_map.v verilog_defaults -add -D ALLOW_WHITEBOX_DSP48E1 -synth_analogdevices +synth_analogdevices techmap -autoproc -wb -map +/analogdevices/cells_sim.v opt -full -fine select -assert-count 0 t:* t:$assert %d diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 2f37ff944..c00dc6d96 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -233,7 +233,7 @@ endmodule // double_sync_ram_sdp module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) - (input wire clk_a, clk_b, + (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, input wire read_enable_a, read_enable_b, input wire [DATA_WIDTH-1:0] write_data_a, write_data_b, diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index cf1c21a58..3d96674c7 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -19,7 +19,7 @@ state <= #1 IDLE; gnt_0 <= 0; gnt_1 <= 0; - end + end else case(state) IDLE : if (req_0 == 1'b1) begin diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index 06e63c9af..589e2d29f 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -13,5 +13,5 @@ module top(out, clk, in); begin out <= out >> 1; out[7] <= in; - end + end endmodule diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys index 1d1682fcd..d997bc7c9 100644 --- a/tests/arch/ecp5/bug1598.ys +++ b/tests/arch/ecp5/bug1598.ys @@ -3,13 +3,13 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys index f075182c8..cca5a7648 100644 --- a/tests/arch/ecp5/memories.ys +++ b/tests/arch/ecp5/memories.ys @@ -268,5 +268,5 @@ design -reset; read_verilog -defer ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp hierarchy -top sync_ram_tdp synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp -select -assert-count 1 t:DP16KD +select -assert-count 1 t:DP16KD select -assert-none t:LUT4 diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys index 3f0079f4a..e39a4fcbc 100644 --- a/tests/arch/ecp5/shifter.ys +++ b/tests/arch/ecp5/shifter.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - + select -assert-count 8 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys index 8438cb979..6ea04b6fd 100644 --- a/tests/arch/ice40/bug1598.ys +++ b/tests/arch/ice40/bug1598.ys @@ -3,13 +3,13 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys index 16f8283a0..92ce8eec9 100644 --- a/tests/arch/ice40/bug1626.ys +++ b/tests/arch/ice40/bug1626.ys @@ -182,20 +182,20 @@ module \ahb_async_sram_halfwidth attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:72" switch $logic_not$../hdl/mem/ahb_async_sram_halfwidth.v:72$2437_Y case 1'1 - case + case attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:78" switch \ahbls_hready case 1'1 attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:79" switch \ahbls_htrans [1] case 1'1 - case + case end - case + case attribute \src "../hdl/mem/ahb_async_sram_halfwidth.v:91" switch $logic_and$../hdl/mem/ahb_async_sram_halfwidth.v:91$2441_Y case 1'1 - case + case end end end diff --git a/tests/arch/ice40/ice40_dsp_const.ys b/tests/arch/ice40/ice40_dsp_const.ys index 735f945a1..893f681ed 100644 --- a/tests/arch/ice40/ice40_dsp_const.ys +++ b/tests/arch/ice40/ice40_dsp_const.ys @@ -75,7 +75,7 @@ EOT techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v async2sync -equiv_make top ref equiv -select -assert-any -module equiv t:$equiv -equiv_induct +equiv_make top ref equiv +select -assert-any -module equiv t:$equiv +equiv_induct equiv_status -assert diff --git a/tests/arch/ice40/spram.v b/tests/arch/ice40/spram.v index 4e1aef2c6..fb55aa7d9 100644 --- a/tests/arch/ice40/spram.v +++ b/tests/arch/ice40/spram.v @@ -6,7 +6,7 @@ parameter SKIP_RDEN = 1; input clk; input write_enable, read_enable; input [DATA_WIDTH - 1 : 0] write_data; -input [ADDR_WIDTH - 1 : 0] addr; +input [ADDR_WIDTH - 1 : 0] addr; output [DATA_WIDTH - 1 : 0] read_data; (* ram_style = "huge" *) diff --git a/tests/arch/microchip/dff.ys b/tests/arch/microchip/dff.ys index 04fdcfc92..9b6e03f5a 100644 --- a/tests/arch/microchip/dff.ys +++ b/tests/arch/microchip/dff.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/dff_opt.ys b/tests/arch/microchip/dff_opt.ys index 52e96935d..d12bed1d4 100644 --- a/tests/arch/microchip/dff_opt.ys +++ b/tests/arch/microchip/dff_opt.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/dsp.ys b/tests/arch/microchip/dsp.ys index b02ad624a..a616851cd 100644 --- a/tests/arch/microchip/dsp.ys +++ b/tests/arch/microchip/dsp.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -120,7 +120,7 @@ output reg cout; input [n:0] a; input [n:0] b; input [n-1:0] c; - always @(*) + always @(*) begin {cout,out} = a * b + c; end diff --git a/tests/arch/microchip/mult.ys b/tests/arch/microchip/mult.ys index 7a82e52ec..36164fd58 100644 --- a/tests/arch/microchip/mult.ys +++ b/tests/arch/microchip/mult.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/ram_SDP.ys b/tests/arch/microchip/ram_SDP.ys index 1b8bffc36..3ba49f0dd 100644 --- a/tests/arch/microchip/ram_SDP.ys +++ b/tests/arch/microchip/ram_SDP.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -27,7 +27,7 @@ output reg [d_width-1:0] q; reg [d_width-1:0] mem [mem_depth-1:0]; always @(posedge clk) begin - if (we) begin + if (we) begin mem[waddr] <= data; end else begin q <= mem[waddr]; diff --git a/tests/arch/microchip/ram_TDP.ys b/tests/arch/microchip/ram_TDP.ys index 79db0456c..21e72ed9b 100644 --- a/tests/arch/microchip/ram_TDP.ys +++ b/tests/arch/microchip/ram_TDP.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,7 +28,7 @@ reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0]; always @ (posedge clka) begin addra_reg <= addra; - + if(wea) begin mem[addra] <= dataina; qa <= dataina; diff --git a/tests/arch/microchip/reduce.ys b/tests/arch/microchip/reduce.ys index 07f25a3d1..45ca72eaa 100644 --- a/tests/arch/microchip/reduce.ys +++ b/tests/arch/microchip/reduce.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/simple_ram.ys b/tests/arch/microchip/simple_ram.ys index 22e3b9317..7bb6318f0 100644 --- a/tests/arch/microchip/simple_ram.ys +++ b/tests/arch/microchip/simple_ram.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/microchip/uram_ar.ys b/tests/arch/microchip/uram_ar.ys index 95c3fbf41..208714824 100644 --- a/tests/arch/microchip/uram_ar.ys +++ b/tests/arch/microchip/uram_ar.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -28,7 +28,7 @@ reg [d_width-1:0] mem [mem_depth-1:0]; assign q = mem[waddr]; always @(posedge clk) begin - if (we) + if (we) mem[waddr] <= data; end diff --git a/tests/arch/microchip/uram_sr.ys b/tests/arch/microchip/uram_sr.ys index 338ce5ecc..a3ddb1835 100644 --- a/tests/arch/microchip/uram_sr.ys +++ b/tests/arch/microchip/uram_sr.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -32,7 +32,7 @@ module uram_sr(clk, wr, raddr, din, waddr, dout); end always@(posedge clk) begin - raddr_reg <= raddr; + raddr_reg <= raddr; if(wr) mem[waddr]<= din; end diff --git a/tests/arch/microchip/widemux.ys b/tests/arch/microchip/widemux.ys index b066dd540..78d6860d0 100644 --- a/tests/arch/microchip/widemux.ys +++ b/tests/arch/microchip/widemux.ys @@ -1,11 +1,11 @@ # ISC License -# +# # Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries -# +# # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above # copyright notice and this permission notice appear in all copies. -# +# # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR diff --git a/tests/arch/nanoxplore/meminit.v b/tests/arch/nanoxplore/meminit.v index 24d5a57f7..c0896523c 100644 --- a/tests/arch/nanoxplore/meminit.v +++ b/tests/arch/nanoxplore/meminit.v @@ -31,7 +31,7 @@ always @(posedge clk) begin read_addr <= counter; read_val <= mem[counter]; end else begin - did_read <= 1'b0; + did_read <= 1'b0; end if (!done) diff --git a/tests/arch/nanoxplore/meminit.ys b/tests/arch/nanoxplore/meminit.ys index ca93e6500..1209b0d6c 100644 --- a/tests/arch/nanoxplore/meminit.ys +++ b/tests/arch/nanoxplore/meminit.ys @@ -3,7 +3,7 @@ chparam -set DEPTH_LOG2 5 -set WIDTH 36 prep opt_dff prep -rdff -synth_nanoxplore +synth_nanoxplore clean_zerowidth select -assert-none t:$mem_v2 t:$mem read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v @@ -18,7 +18,7 @@ chparam -set DEPTH_LOG2 6 -set WIDTH 18 prep opt_dff prep -rdff -synth_nanoxplore +synth_nanoxplore clean_zerowidth select -assert-none t:$mem_v2 t:$mem read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v @@ -34,7 +34,7 @@ chparam -set DEPTH_LOG2 8 -set WIDTH 18 prep opt_dff prep -rdff -synth_nanoxplore +synth_nanoxplore clean_zerowidth select -assert-none t:$mem_v2 t:$mem read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v diff --git a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys index e12963ae6..78bd221cc 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -9,7 +9,7 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dff # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre -select -assert-none t:sdffsre %% t:* %D +select -assert-none t:sdffsre %% t:* %D design -load read hierarchy -top my_dffe @@ -18,4 +18,4 @@ equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/qu design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dffe # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre -select -assert-none t:sdffsre %% t:* %D +select -assert-none t:sdffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index a0d15bd62..988aceaca 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -46,7 +46,7 @@ initial begin end `MEM_TEST_VECTOR - + end @@ -73,7 +73,7 @@ wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i]; always @(posedge clk) begin if (i < VECTORLEN-1) begin if (i > 0) begin - if($past(rce_a)) + if($past(rce_a)) assert(rq_a == rq_a_e); if($past(rce_b)) assert(rq_b == rq_b_e); diff --git a/tests/arch/quicklogic/qlf_k6n10f/meminit.v b/tests/arch/quicklogic/qlf_k6n10f/meminit.v index 46a7dcac7..afc525656 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/meminit.v +++ b/tests/arch/quicklogic/qlf_k6n10f/meminit.v @@ -31,7 +31,7 @@ always @(posedge clk) begin read_addr <= counter; read_val <= mem[counter]; end else begin - did_read <= 1'b0; + did_read <= 1'b0; end if (!done) diff --git a/tests/arch/xilinx/asym_ram_sdp_read_wider.v b/tests/arch/xilinx/asym_ram_sdp_read_wider.v index 49080c836..fec464e48 100644 --- a/tests/arch/xilinx/asym_ram_sdp_read_wider.v +++ b/tests/arch/xilinx/asym_ram_sdp_read_wider.v @@ -5,7 +5,7 @@ module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, parameter WIDTHA = 4; parameter SIZEA = 1024; parameter ADDRWIDTHA = 10; - + parameter WIDTHB = 16; parameter SIZEB = 256; parameter ADDRWIDTHB = 8; diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys index 74861850f..16dad6dbf 100644 --- a/tests/arch/xilinx/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -4,7 +4,7 @@ hierarchy -top block_ram synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 - + # Check that distributed memory without parameters is not modified design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -12,7 +12,7 @@ hierarchy -top distributed_ram synth_xilinx -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module select -assert-count 1 t:RAM32M - + # Set ram_style distributed to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -20,7 +20,7 @@ setattr -set ram_style "distributed" block_ram/m:* synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 16 t:RAM256X1S - + # Set synthesis, logic_block to blockram memory; will be implemented as distributed design -reset read_verilog ../common/memory_attributes/attributes_test.v @@ -28,7 +28,7 @@ setattr -set logic_block 1 block_ram/m:* synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RAMB18E1 - + # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index c2b7aede7..96da72eaa 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp @@ -58,7 +58,7 @@ select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v -hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp diff --git a/tests/arch/xilinx/bug1598.ys b/tests/arch/xilinx/bug1598.ys index 1175380b1..f495b9b78 100644 --- a/tests/arch/xilinx/bug1598.ys +++ b/tests/arch/xilinx/bug1598.ys @@ -3,13 +3,13 @@ module led_blink ( input clk, output ledc ); - + reg [6:0] led_counter = 0; always @( posedge clk ) begin led_counter <= led_counter + 1; end assign ledc = !led_counter[ 6:3 ]; - + endmodule EOT proc diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v index 29920da41..059109275 100644 --- a/tests/arch/xilinx/xilinx_srl.v +++ b/tests/arch/xilinx/xilinx_srl.v @@ -34,7 +34,7 @@ parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; reg [DEPTH-1:0] r = INIT; wire clk = C ^ CLKPOL; always @(posedge C) - if (E) + if (E) r <= { r[DEPTH-2:0], D }; assign Q = r[L]; endmodule diff --git a/tests/asicworld/code_hdl_models_GrayCounter.v b/tests/asicworld/code_hdl_models_GrayCounter.v index 23f0da04b..88e2972a4 100644 --- a/tests/asicworld/code_hdl_models_GrayCounter.v +++ b/tests/asicworld/code_hdl_models_GrayCounter.v @@ -6,19 +6,19 @@ module GrayCounter #(parameter COUNTER_WIDTH = 4) - + (output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output. - + input wire Enable_in, //Count enable. input wire Clear_in, //Count reset. - + input wire Clk); /////////Internal connections & variables/////// reg [COUNTER_WIDTH-1:0] BinaryCount; /////////Code/////////////////////// - + always @ (posedge Clk) if (Clear_in) begin BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' with @@ -29,5 +29,5 @@ module GrayCounter GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1], BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]}; end - + endmodule diff --git a/tests/asicworld/code_hdl_models_arbiter.v b/tests/asicworld/code_hdl_models_arbiter.v index d3e3a66f1..3119f0580 100644 --- a/tests/asicworld/code_hdl_models_arbiter.v +++ b/tests/asicworld/code_hdl_models_arbiter.v @@ -3,32 +3,32 @@ // orginally coded by WD Peterson in VHDL. //---------------------------------------------------- module arbiter ( - clk, - rst, - req3, - req2, - req1, - req0, - gnt3, - gnt2, - gnt1, - gnt0 + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 ); -// --------------Port Declaration----------------------- -input clk; -input rst; -input req3; -input req2; -input req1; -input req0; -output gnt3; -output gnt2; -output gnt1; -output gnt0; +// --------------Port Declaration----------------------- +input clk; +input rst; +input req3; +input req2; +input req1; +input req0; +output gnt3; +output gnt2; +output gnt1; +output gnt0; //--------------Internal Registers---------------------- -wire [1:0] gnt ; -wire comreq ; +wire [1:0] gnt ; +wire comreq ; wire beg ; wire [1:0] lgnt ; wire lcomreq ; @@ -41,14 +41,14 @@ reg lmask0 ; reg lmask1 ; reg ledge ; -//--------------Code Starts Here----------------------- +//--------------Code Starts Here----------------------- always @ (posedge clk) if (rst) begin lgnt0 <= 0; lgnt1 <= 0; lgnt2 <= 0; lgnt3 <= 0; -end else begin +end else begin lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0) | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0) | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0) @@ -69,18 +69,18 @@ end else begin | (~lcomreq & lmask1 & ~lmask0 & req3) | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0) | ( lcomreq & lgnt3); -end +end //---------------------------------------------------- // lasmask state machine. //---------------------------------------------------- assign beg = (req3 | req2 | req1 | req0) & ~lcomreq; always @ (posedge clk) -begin +begin lasmask <= (beg & ~ledge & ~lasmask); - ledge <= (beg & ~ledge & lasmask) + ledge <= (beg & ~ledge & lasmask) | (beg & ledge & ~lasmask); -end +end //---------------------------------------------------- // comreq logic. @@ -108,7 +108,7 @@ end else if(lasmask) begin end else begin lmask1 <= lmask1; lmask0 <= lmask0; -end +end assign comreq = lcomreq; assign gnt = lgnt; diff --git a/tests/asicworld/code_hdl_models_arbiter_tb.v b/tests/asicworld/code_hdl_models_arbiter_tb.v index 78d1168e6..6d28ea23b 100644 --- a/tests/asicworld/code_hdl_models_arbiter_tb.v +++ b/tests/asicworld/code_hdl_models_arbiter_tb.v @@ -6,10 +6,10 @@ reg req3 = 0; reg req2 = 0; reg req1 = 0; reg req0 = 0; -wire gnt3; -wire gnt2; -wire gnt1; -wire gnt0; +wire gnt3; +wire gnt2; +wire gnt1; +wire gnt0; // Clock generator always #1 clk = ~clk; @@ -41,20 +41,20 @@ initial begin req0 <= 0; repeat (1) @ (posedge clk); #10 $finish; -end +end // Connect the DUT arbiter U ( - clk, - rst, - req3, - req2, - req1, - req0, - gnt3, - gnt2, - gnt1, - gnt0 + clk, + rst, + req3, + req2, + req1, + req0, + gnt3, + gnt2, + gnt1, + gnt0 ); endmodule diff --git a/tests/asicworld/code_hdl_models_cam.v b/tests/asicworld/code_hdl_models_cam.v index 0cebc07cc..781ccdf98 100644 --- a/tests/asicworld/code_hdl_models_cam.v +++ b/tests/asicworld/code_hdl_models_cam.v @@ -9,18 +9,18 @@ clk , // Cam clock cam_enable , // Cam enable cam_data_in , // Cam data to match cam_hit_out , // Cam match has happened -cam_addr_out // Cam output address +cam_addr_out // Cam output address ); parameter ADDR_WIDTH = 8; parameter DEPTH = 1 << ADDR_WIDTH; //------------Input Ports-------------- -input clk; -input cam_enable; -input [DEPTH-1:0] cam_data_in; +input clk; +input cam_enable; +input [DEPTH-1:0] cam_data_in; //----------Output Ports-------------- -output cam_hit_out; -output [ADDR_WIDTH-1:0] cam_addr_out; +output cam_hit_out; +output [ADDR_WIDTH-1:0] cam_addr_out; //------------Internal Variables-------- reg [ADDR_WIDTH-1:0] cam_addr_out; reg cam_hit_out; @@ -46,7 +46,7 @@ always @(cam_data_in) begin end end -// Register the outputs +// Register the outputs always @(posedge clk) begin if (cam_enable) begin cam_hit_out <= cam_hit_combo; @@ -57,4 +57,4 @@ always @(posedge clk) begin end end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_clk_div.v b/tests/asicworld/code_hdl_models_clk_div.v index c48ab0dd0..ae4e7edfb 100644 --- a/tests/asicworld/code_hdl_models_clk_div.v +++ b/tests/asicworld/code_hdl_models_clk_div.v @@ -6,7 +6,7 @@ //----------------------------------------------------- module clk_div (clk_in, enable,reset, clk_out); - // --------------Port Declaration----------------------- + // --------------Port Declaration----------------------- input clk_in ; input reset ; input enable ; @@ -16,12 +16,12 @@ module clk_div (clk_in, enable,reset, clk_out); wire enable ; //--------------Internal Registers---------------------- reg clk_out ; -//--------------Code Starts Here----------------------- -always @ (posedge clk_in) -if (reset) begin +//--------------Code Starts Here----------------------- +always @ (posedge clk_in) +if (reset) begin clk_out <= 1'b0; end else if (enable) begin - clk_out <= !clk_out ; + clk_out <= !clk_out ; end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_clk_div_45.v b/tests/asicworld/code_hdl_models_clk_div_45.v index d9d289673..e40820c52 100644 --- a/tests/asicworld/code_hdl_models_clk_div_45.v +++ b/tests/asicworld/code_hdl_models_clk_div_45.v @@ -28,7 +28,7 @@ reg toggle2 ; //--------------Code Starts Here----------------------- always @ (posedge clk_in) -if (enable == 1'b0) begin +if (enable == 1'b0) begin counter1 <= 4'b0; toggle1 <= 0; end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin @@ -37,7 +37,7 @@ end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin end else begin counter1 <= counter1 + 1; end - + always @ (negedge clk_in) if (enable == 1'b0) begin counter2 <= 4'b0; diff --git a/tests/asicworld/code_hdl_models_decoder_using_assign.v b/tests/asicworld/code_hdl_models_decoder_using_assign.v index ec0dc95b2..69a8e1aec 100644 --- a/tests/asicworld/code_hdl_models_decoder_using_assign.v +++ b/tests/asicworld/code_hdl_models_decoder_using_assign.v @@ -6,14 +6,14 @@ //----------------------------------------------------- module decoder_using_assign ( binary_in , // 4 bit binary input -decoder_out , // 16-bit out +decoder_out , // 16-bit out enable // Enable for the decoder ); input [3:0] binary_in ; -input enable ; -output [15:0] decoder_out ; - -wire [15:0] decoder_out ; +input enable ; +output [15:0] decoder_out ; + +wire [15:0] decoder_out ; assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ; diff --git a/tests/asicworld/code_hdl_models_dff_async_reset.v b/tests/asicworld/code_hdl_models_dff_async_reset.v index a156082f4..cfda75a8a 100644 --- a/tests/asicworld/code_hdl_models_dff_async_reset.v +++ b/tests/asicworld/code_hdl_models_dff_async_reset.v @@ -7,11 +7,11 @@ module dff_async_reset ( data , // Data Input clk , // Clock Input -reset , // Reset input +reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; diff --git a/tests/asicworld/code_hdl_models_dff_sync_reset.v b/tests/asicworld/code_hdl_models_dff_sync_reset.v index 7ef404548..0efb4c840 100644 --- a/tests/asicworld/code_hdl_models_dff_sync_reset.v +++ b/tests/asicworld/code_hdl_models_dff_sync_reset.v @@ -11,7 +11,7 @@ reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; diff --git a/tests/asicworld/code_hdl_models_encoder_using_case.v b/tests/asicworld/code_hdl_models_encoder_using_case.v index 32e1b720f..91bafb99c 100644 --- a/tests/asicworld/code_hdl_models_encoder_using_case.v +++ b/tests/asicworld/code_hdl_models_encoder_using_case.v @@ -10,31 +10,31 @@ encoder_in , // 16-bit Input enable // Enable for the encoder ); output [3:0] binary_out ; -input enable ; -input [15:0] encoder_in ; - +input enable ; +input [15:0] encoder_in ; + reg [3:0] binary_out ; - + always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin - case (encoder_in) - 16'h0002 : binary_out = 1; - 16'h0004 : binary_out = 2; - 16'h0008 : binary_out = 3; + case (encoder_in) + 16'h0002 : binary_out = 1; + 16'h0004 : binary_out = 2; + 16'h0008 : binary_out = 3; 16'h0010 : binary_out = 4; - 16'h0020 : binary_out = 5; - 16'h0040 : binary_out = 6; - 16'h0080 : binary_out = 7; + 16'h0020 : binary_out = 5; + 16'h0040 : binary_out = 6; + 16'h0080 : binary_out = 7; 16'h0100 : binary_out = 8; 16'h0200 : binary_out = 9; - 16'h0400 : binary_out = 10; - 16'h0800 : binary_out = 11; - 16'h1000 : binary_out = 12; - 16'h2000 : binary_out = 13; - 16'h4000 : binary_out = 14; - 16'h8000 : binary_out = 15; + 16'h0400 : binary_out = 10; + 16'h0800 : binary_out = 11; + 16'h1000 : binary_out = 12; + 16'h2000 : binary_out = 13; + 16'h4000 : binary_out = 14; + 16'h8000 : binary_out = 15; endcase end end diff --git a/tests/asicworld/code_hdl_models_encoder_using_if.v b/tests/asicworld/code_hdl_models_encoder_using_if.v index 2c97ddba6..3f559b60e 100644 --- a/tests/asicworld/code_hdl_models_encoder_using_if.v +++ b/tests/asicworld/code_hdl_models_encoder_using_if.v @@ -8,51 +8,51 @@ module encoder_using_if( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder -); +); //-----------Output Ports--------------- output [3:0] binary_out ; //-----------Input Ports--------------- -input enable ; -input [15:0] encoder_in ; +input enable ; +input [15:0] encoder_in ; //------------Internal Variables-------- -reg [3:0] binary_out ; +reg [3:0] binary_out ; //-------------Code Start----------------- always @ (enable or encoder_in) - begin - binary_out = 0; + begin + binary_out = 0; if (enable) begin if (encoder_in == 16'h0002) begin binary_out = 1; - end if (encoder_in == 16'h0004) begin - binary_out = 2; - end if (encoder_in == 16'h0008) begin - binary_out = 3; - end if (encoder_in == 16'h0010) begin - binary_out = 4; - end if (encoder_in == 16'h0020) begin - binary_out = 5; - end if (encoder_in == 16'h0040) begin - binary_out = 6; - end if (encoder_in == 16'h0080) begin - binary_out = 7; - end if (encoder_in == 16'h0100) begin - binary_out = 8; - end if (encoder_in == 16'h0200) begin - binary_out = 9; - end if (encoder_in == 16'h0400) begin - binary_out = 10; - end if (encoder_in == 16'h0800) begin - binary_out = 11; + end if (encoder_in == 16'h0004) begin + binary_out = 2; + end if (encoder_in == 16'h0008) begin + binary_out = 3; + end if (encoder_in == 16'h0010) begin + binary_out = 4; + end if (encoder_in == 16'h0020) begin + binary_out = 5; + end if (encoder_in == 16'h0040) begin + binary_out = 6; + end if (encoder_in == 16'h0080) begin + binary_out = 7; + end if (encoder_in == 16'h0100) begin + binary_out = 8; + end if (encoder_in == 16'h0200) begin + binary_out = 9; + end if (encoder_in == 16'h0400) begin + binary_out = 10; + end if (encoder_in == 16'h0800) begin + binary_out = 11; end if (encoder_in == 16'h1000) begin - binary_out = 12; - end if (encoder_in == 16'h2000) begin + binary_out = 12; + end if (encoder_in == 16'h2000) begin binary_out = 13; - end if (encoder_in == 16'h4000) begin - binary_out = 14; - end if (encoder_in == 16'h8000) begin - binary_out = 15; + end if (encoder_in == 16'h4000) begin + binary_out = 14; + end if (encoder_in == 16'h8000) begin + binary_out = 15; end end end - + endmodule diff --git a/tests/asicworld/code_hdl_models_gray_counter.v b/tests/asicworld/code_hdl_models_gray_counter.v index bc1e740ab..2b9bdb65f 100644 --- a/tests/asicworld/code_hdl_models_gray_counter.v +++ b/tests/asicworld/code_hdl_models_gray_counter.v @@ -10,24 +10,24 @@ module gray_counter ( clk , // clock rst // active hight reset ); - + //------------Input Ports-------------- - input clk, rst, enable; + input clk, rst, enable; //----------Output Ports---------------- output [ 7:0] out; //------------Internal Variables-------- wire [7:0] out; reg [7:0] count; //-------------Code Starts Here--------- - always @ (posedge clk) - if (rst) - count <= 0; - else if (enable) - count <= count + 1; - - assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ - count[5]),(count[5] ^ count[4]), (count[4] ^ - count[3]),(count[3] ^ count[2]), (count[2] ^ + always @ (posedge clk) + if (rst) + count <= 0; + else if (enable) + count <= count + 1; + + assign out = { count[7], (count[7] ^ count[6]),(count[6] ^ + count[5]),(count[5] ^ count[4]), (count[4] ^ + count[3]),(count[3] ^ count[2]), (count[2] ^ count[1]),(count[1] ^ count[0]) }; - -endmodule + +endmodule diff --git a/tests/asicworld/code_hdl_models_lfsr.v b/tests/asicworld/code_hdl_models_lfsr.v index 639780832..b0902e630 100644 --- a/tests/asicworld/code_hdl_models_lfsr.v +++ b/tests/asicworld/code_hdl_models_lfsr.v @@ -30,6 +30,6 @@ end else if (enable) begin out[4],out[3], out[2],out[1], out[0], linear_feedback}; -end +end endmodule // End Of Module counter diff --git a/tests/asicworld/code_hdl_models_lfsr_updown.v b/tests/asicworld/code_hdl_models_lfsr_updown.v index 0bd29b835..d40a586ef 100644 --- a/tests/asicworld/code_hdl_models_lfsr_updown.v +++ b/tests/asicworld/code_hdl_models_lfsr_updown.v @@ -1,4 +1,4 @@ -`define WIDTH 8 +`define WIDTH 8 module lfsr_updown ( clk , // Clock input reset , // Reset input @@ -10,7 +10,7 @@ overflow // Overflow output input clk; input reset; - input enable; + input enable; input up_down; output [`WIDTH-1 : 0] count; @@ -18,11 +18,11 @@ overflow // Overflow output reg [`WIDTH-1 : 0] count; - assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : + assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : (count == {1'b1, {`WIDTH-1{1'b0}}}) ; always @(posedge clk) - if (reset) + if (reset) count <= {`WIDTH{1'b0}}; else if (enable) begin if (up_down) begin diff --git a/tests/asicworld/code_hdl_models_mux_using_case.v b/tests/asicworld/code_hdl_models_mux_using_case.v index 123da4483..8d60c6662 100644 --- a/tests/asicworld/code_hdl_models_mux_using_case.v +++ b/tests/asicworld/code_hdl_models_mux_using_case.v @@ -19,10 +19,10 @@ reg mux_out; //-------------Code Starts Here--------- always @ (sel or din_0 or din_1) begin : MUX - case(sel ) + case(sel ) 1'b0 : mux_out = din_0; 1'b1 : mux_out = din_1; - endcase + endcase end endmodule //End Of Module mux diff --git a/tests/asicworld/code_hdl_models_one_hot_cnt.v b/tests/asicworld/code_hdl_models_one_hot_cnt.v index f6b84c6e5..e4d50b585 100644 --- a/tests/asicworld/code_hdl_models_one_hot_cnt.v +++ b/tests/asicworld/code_hdl_models_one_hot_cnt.v @@ -17,7 +17,7 @@ output [7:0] out; input enable, clk, reset; //------------Internal Variables-------- -reg [7:0] out; +reg [7:0] out; //-------------Code Starts Here------- always @ (posedge clk) @@ -28,4 +28,4 @@ end else if (enable) begin out[2],out[1],out[0],out[7]}; end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_parallel_crc.v b/tests/asicworld/code_hdl_models_parallel_crc.v index d8d0bf1c6..8e9aad27f 100644 --- a/tests/asicworld/code_hdl_models_parallel_crc.v +++ b/tests/asicworld/code_hdl_models_parallel_crc.v @@ -8,8 +8,8 @@ module parallel_crc_ccitt ( clk , reset , enable , -init , -data_in , +init , +data_in , crc_out ); //-----------Input Ports--------------- diff --git a/tests/asicworld/code_hdl_models_parity_using_assign.v b/tests/asicworld/code_hdl_models_parity_using_assign.v index b0282e8d7..e676a8f49 100644 --- a/tests/asicworld/code_hdl_models_parity_using_assign.v +++ b/tests/asicworld/code_hdl_models_parity_using_assign.v @@ -9,13 +9,13 @@ data_in , // 8 bit data in parity_out // 1 bit parity out ); output parity_out ; -input [7:0] data_in ; - +input [7:0] data_in ; + wire parity_out ; - -assign parity_out = (data_in[0] ^ data_in[1]) ^ - (data_in[2] ^ data_in[3]) ^ - (data_in[4] ^ data_in[5]) ^ + +assign parity_out = (data_in[0] ^ data_in[1]) ^ + (data_in[2] ^ data_in[3]) ^ + (data_in[4] ^ data_in[5]) ^ (data_in[6] ^ data_in[7]); -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_parity_using_bitwise.v b/tests/asicworld/code_hdl_models_parity_using_bitwise.v index 0046fb143..36e8931b8 100644 --- a/tests/asicworld/code_hdl_models_parity_using_bitwise.v +++ b/tests/asicworld/code_hdl_models_parity_using_bitwise.v @@ -9,8 +9,8 @@ data_in , // 8 bit data in parity_out // 1 bit parity out ); output parity_out ; -input [7:0] data_in ; - -assign parity_out = ^data_in; +input [7:0] data_in ; + +assign parity_out = ^data_in; endmodule diff --git a/tests/asicworld/code_hdl_models_parity_using_function.v b/tests/asicworld/code_hdl_models_parity_using_function.v index 0d07aaebe..531c973e8 100644 --- a/tests/asicworld/code_hdl_models_parity_using_function.v +++ b/tests/asicworld/code_hdl_models_parity_using_function.v @@ -9,21 +9,21 @@ data_in , // 8 bit data in parity_out // 1 bit parity out ); output parity_out ; -input [7:0] data_in ; - -wire parity_out ; +input [7:0] data_in ; + +wire parity_out ; function parity; - input [31:0] data; + input [31:0] data; begin - parity = (data_in[0] ^ data_in[1]) ^ - (data_in[2] ^ data_in[3]) ^ - (data_in[4] ^ data_in[5]) ^ + parity = (data_in[0] ^ data_in[1]) ^ + (data_in[2] ^ data_in[3]) ^ + (data_in[4] ^ data_in[5]) ^ (data_in[6] ^ data_in[7]); - end -endfunction - - + end +endfunction + + assign parity_out = parity(data_in); endmodule diff --git a/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v b/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v index c1ce960c4..5c3784e9b 100644 --- a/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v +++ b/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v @@ -6,31 +6,31 @@ //----------------------------------------------------- module pri_encoder_using_assign ( binary_out , // 4 bit binary output -encoder_in , // 16-bit input +encoder_in , // 16-bit input enable // Enable for the encoder ); output [3:0] binary_out ; -input enable ; -input [15:0] encoder_in ; +input enable ; +input [15:0] encoder_in ; wire [3:0] binary_out ; - -assign binary_out = (!enable) ? 0 : ( - (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : - (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : - (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : - (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : - (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : - (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : - (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : - (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : - (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : - (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : - (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : - (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : - (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : - (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : - (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15); -endmodule +assign binary_out = (!enable) ? 0 : ( + (encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 : + (encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 : + (encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 : + (encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 : + (encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 : + (encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 : + (encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 : + (encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 : + (encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 : + (encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 : + (encoder_in == 16'bxxxx_x100_0000_0000) ? 10 : + (encoder_in == 16'bxxxx_1000_0000_0000) ? 11 : + (encoder_in == 16'bxxx1_0000_0000_0000) ? 12 : + (encoder_in == 16'bxx10_0000_0000_0000) ? 13 : + (encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15); + +endmodule diff --git a/tests/asicworld/code_hdl_models_rom_using_case.v b/tests/asicworld/code_hdl_models_rom_using_case.v index 6b700993b..1a0ee7949 100644 --- a/tests/asicworld/code_hdl_models_rom_using_case.v +++ b/tests/asicworld/code_hdl_models_rom_using_case.v @@ -7,7 +7,7 @@ module rom_using_case ( address , // Address input data , // Data output -read_en , // Read Enable +read_en , // Read Enable ce // Chip Enable ); input [3:0] address; @@ -16,7 +16,7 @@ input read_en; input ce; reg [7:0] data ; - + always @ (ce or read_en or address) begin case (address) diff --git a/tests/asicworld/code_hdl_models_serial_crc.v b/tests/asicworld/code_hdl_models_serial_crc.v index a4a63a26f..de4424e8c 100644 --- a/tests/asicworld/code_hdl_models_serial_crc.v +++ b/tests/asicworld/code_hdl_models_serial_crc.v @@ -8,8 +8,8 @@ module serial_crc_ccitt ( clk , reset , enable , -init , -data_in , +init , +data_in , crc_out ); //-----------Input Ports--------------- @@ -49,6 +49,6 @@ end else if (enable) begin lfsr[14] <= lfsr[13]; lfsr[15] <= lfsr[14]; end -end +end endmodule diff --git a/tests/asicworld/code_hdl_models_tff_async_reset.v b/tests/asicworld/code_hdl_models_tff_async_reset.v index 4c5a1fa9c..d45fcc330 100644 --- a/tests/asicworld/code_hdl_models_tff_async_reset.v +++ b/tests/asicworld/code_hdl_models_tff_async_reset.v @@ -11,7 +11,7 @@ reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- diff --git a/tests/asicworld/code_hdl_models_tff_sync_reset.v b/tests/asicworld/code_hdl_models_tff_sync_reset.v index a962d53d8..f9ecd3ae8 100644 --- a/tests/asicworld/code_hdl_models_tff_sync_reset.v +++ b/tests/asicworld/code_hdl_models_tff_sync_reset.v @@ -11,7 +11,7 @@ reset , // Reset input q // Q output ); //-----------Input Ports--------------- -input data, clk, reset ; +input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- diff --git a/tests/asicworld/code_hdl_models_uart.v b/tests/asicworld/code_hdl_models_uart.v index 40205250a..f8a5afaed 100644 --- a/tests/asicworld/code_hdl_models_uart.v +++ b/tests/asicworld/code_hdl_models_uart.v @@ -1,5 +1,5 @@ //----------------------------------------------------- -// Design Name : uart +// Design Name : uart // File Name : uart.v // Function : Simple UART // Coder : Deepak Kumar Tala @@ -34,7 +34,7 @@ input rx_enable ; input rx_in ; output rx_empty ; -// Internal Variables +// Internal Variables reg [7:0] tx_reg ; reg tx_empty ; reg tx_over_run ; @@ -43,7 +43,7 @@ reg tx_out ; reg [7:0] rx_reg ; reg [7:0] rx_data ; reg [3:0] rx_sample_cnt ; -reg [3:0] rx_cnt ; +reg [3:0] rx_cnt ; reg rx_frame_err ; reg rx_over_run ; reg rx_empty ; @@ -54,7 +54,7 @@ reg rx_busy ; // UART RX Logic always @ (posedge rxclk or posedge reset) if (reset) begin - rx_reg <= 0; + rx_reg <= 0; rx_data <= 0; rx_sample_cnt <= 0; rx_cnt <= 0; @@ -89,7 +89,7 @@ end else begin if ((rx_d2 == 1) && (rx_cnt == 0)) begin rx_busy <= 0; end else begin - rx_cnt <= rx_cnt + 1; + rx_cnt <= rx_cnt + 1; // Start storing the rx data if (rx_cnt > 0 && rx_cnt < 9) begin rx_reg[rx_cnt - 1] <= rx_d2; @@ -107,8 +107,8 @@ end else begin end end end - end - end + end + end end if (!rx_enable) begin rx_busy <= 0; diff --git a/tests/asicworld/code_hdl_models_up_counter.v b/tests/asicworld/code_hdl_models_up_counter.v index 45dd08f16..4ebd58b21 100644 --- a/tests/asicworld/code_hdl_models_up_counter.v +++ b/tests/asicworld/code_hdl_models_up_counter.v @@ -25,4 +25,4 @@ end else if (enable) begin end -endmodule +endmodule diff --git a/tests/asicworld/code_hdl_models_up_counter_load.v b/tests/asicworld/code_hdl_models_up_counter_load.v index 92ad895aa..89645db58 100644 --- a/tests/asicworld/code_hdl_models_up_counter_load.v +++ b/tests/asicworld/code_hdl_models_up_counter_load.v @@ -14,7 +14,7 @@ reset // reset input ); //----------Output Ports-------------- output [7:0] out; -//------------Input Ports-------------- +//------------Input Ports-------------- input [7:0] data; input load, enable, clk, reset; //------------Internal Variables-------- @@ -28,5 +28,5 @@ end else if (load) begin end else if (enable) begin out <= out + 1; end - -endmodule + +endmodule diff --git a/tests/asicworld/code_hdl_models_up_down_counter.v b/tests/asicworld/code_hdl_models_up_down_counter.v index fff2982af..9a634edeb 100644 --- a/tests/asicworld/code_hdl_models_up_down_counter.v +++ b/tests/asicworld/code_hdl_models_up_down_counter.v @@ -12,7 +12,7 @@ reset // reset input ); //----------Output Ports-------------- output [7:0] out; -//------------Input Ports-------------- +//------------Input Ports-------------- input up_down, clk, reset; //------------Internal Variables-------- reg [7:0] out; @@ -26,4 +26,4 @@ end else begin out <= out - 1; end -endmodule +endmodule diff --git a/tests/asicworld/code_specman_switch_fabric.v b/tests/asicworld/code_specman_switch_fabric.v index 1ac7ee701..adf973798 100644 --- a/tests/asicworld/code_specman_switch_fabric.v +++ b/tests/asicworld/code_specman_switch_fabric.v @@ -22,28 +22,28 @@ output [7:0] data_out_ack3, data_out_ack4, data_out_ack5; (* gentb_clock *) wire clk; -switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0), - .data_in_valid(data_in_valid0), .data_out(data_out0), +switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0), + .data_in_valid(data_in_valid0), .data_out(data_out0), .data_out_ack(data_out_ack0)); -switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1), - .data_in_valid(data_in_valid1), .data_out(data_out1), +switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1), + .data_in_valid(data_in_valid1), .data_out(data_out1), .data_out_ack(data_out_ack1)); -switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2), +switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2), .data_in_valid(data_in_valid2), .data_out(data_out2), . data_out_ack(data_out_ack2)); -switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3), - .data_in_valid(data_in_valid3), .data_out(data_out3), +switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3), + .data_in_valid(data_in_valid3), .data_out(data_out3), .data_out_ack(data_out_ack3)); -switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4), - .data_in_valid(data_in_valid4), .data_out(data_out4), +switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4), + .data_in_valid(data_in_valid4), .data_out(data_out4), .data_out_ack(data_out_ack4)); -switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5), - .data_in_valid(data_in_valid5), .data_out(data_out5), +switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5), + .data_in_valid(data_in_valid5), .data_out(data_out5), .data_out_ack(data_out_ack5)); endmodule diff --git a/tests/asicworld/code_tidbits_asyn_reset.v b/tests/asicworld/code_tidbits_asyn_reset.v index 58e47c567..85bd71004 100644 --- a/tests/asicworld/code_tidbits_asyn_reset.v +++ b/tests/asicworld/code_tidbits_asyn_reset.v @@ -2,13 +2,13 @@ module asyn_reset(clk,reset,a,c); input clk; input reset; input a; - output c; + output c; wire clk; - wire reset; - wire a; + wire reset; + wire a; reg c; - + always @ (posedge clk or posedge reset) if ( reset == 1'b1) begin c <= 0; diff --git a/tests/asicworld/code_tidbits_blocking.v b/tests/asicworld/code_tidbits_blocking.v index e13b72cc7..79d67d937 100644 --- a/tests/asicworld/code_tidbits_blocking.v +++ b/tests/asicworld/code_tidbits_blocking.v @@ -2,16 +2,16 @@ module blocking (clk,a,c); input clk; input a; output c; - + wire clk; wire a; reg c; reg b; - + always @ (posedge clk ) begin b = a; c = b; end - + endmodule diff --git a/tests/asicworld/code_tidbits_fsm_using_always.v b/tests/asicworld/code_tidbits_fsm_using_always.v index 8a8775b95..7162bfa61 100644 --- a/tests/asicworld/code_tidbits_fsm_using_always.v +++ b/tests/asicworld/code_tidbits_fsm_using_always.v @@ -9,7 +9,7 @@ reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 -gnt_1 +gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; diff --git a/tests/asicworld/code_tidbits_fsm_using_function.v b/tests/asicworld/code_tidbits_fsm_using_function.v index 404498a01..f97cd8521 100644 --- a/tests/asicworld/code_tidbits_fsm_using_function.v +++ b/tests/asicworld/code_tidbits_fsm_using_function.v @@ -9,7 +9,7 @@ reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 -gnt_1 +gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; @@ -29,7 +29,7 @@ wire [SIZE-1:0] next_state ;// combo part of FSM assign next_state = fsm_function(state, req_0, req_1); //----------Function for Combo Logic----------------- function [SIZE-1:0] fsm_function; - input [SIZE-1:0] state ; + input [SIZE-1:0] state ; input req_0 ; input req_1 ; case(state) diff --git a/tests/asicworld/code_tidbits_fsm_using_single_always.v b/tests/asicworld/code_tidbits_fsm_using_single_always.v index 67cc08841..dc06154d3 100644 --- a/tests/asicworld/code_tidbits_fsm_using_single_always.v +++ b/tests/asicworld/code_tidbits_fsm_using_single_always.v @@ -10,7 +10,7 @@ reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 -gnt_1 +gnt_1 ); //=============Input Ports============================= input clock,reset,req_0,req_1; diff --git a/tests/asicworld/code_tidbits_nonblocking.v b/tests/asicworld/code_tidbits_nonblocking.v index 4a0d365e0..fd0e4ca74 100644 --- a/tests/asicworld/code_tidbits_nonblocking.v +++ b/tests/asicworld/code_tidbits_nonblocking.v @@ -2,16 +2,16 @@ module nonblocking (clk,a,c); input clk; input a; output c; - + wire clk; wire a; reg c; reg b; - + always @ (posedge clk ) begin b <= a; c <= b; end - + endmodule diff --git a/tests/asicworld/code_tidbits_reg_combo_example.v b/tests/asicworld/code_tidbits_reg_combo_example.v index 9689788c4..17765025a 100644 --- a/tests/asicworld/code_tidbits_reg_combo_example.v +++ b/tests/asicworld/code_tidbits_reg_combo_example.v @@ -6,7 +6,7 @@ reg y; wire a, b; always @ ( a or b) -begin +begin y = a & b; end diff --git a/tests/asicworld/code_tidbits_reg_seq_example.v b/tests/asicworld/code_tidbits_reg_seq_example.v index 458c87927..9627b9e04 100644 --- a/tests/asicworld/code_tidbits_reg_seq_example.v +++ b/tests/asicworld/code_tidbits_reg_seq_example.v @@ -1,7 +1,7 @@ module reg_seq_example( clk, reset, d, q); input clk, reset, d; output q; - + reg q; wire clk, reset, d; diff --git a/tests/asicworld/code_tidbits_syn_reset.v b/tests/asicworld/code_tidbits_syn_reset.v index 994771b16..37120eeee 100644 --- a/tests/asicworld/code_tidbits_syn_reset.v +++ b/tests/asicworld/code_tidbits_syn_reset.v @@ -1,19 +1,19 @@ module syn_reset (clk,reset,a,c); input clk; input reset; - input a; - output c; + input a; + output c; wire clk; - wire reset; - wire a; + wire reset; + wire a; reg c; - + always @ (posedge clk ) if ( reset == 1'b1) begin c <= 0; end else begin c <= a; end - -endmodule + +endmodule diff --git a/tests/asicworld/code_verilog_tutorial_always_example.v b/tests/asicworld/code_verilog_tutorial_always_example.v index 8b0fc2067..16174a17f 100644 --- a/tests/asicworld/code_verilog_tutorial_always_example.v +++ b/tests/asicworld/code_verilog_tutorial_always_example.v @@ -4,7 +4,7 @@ reg clk,reset,enable,q_in,data; always @ (posedge clk) if (reset) begin data <= 0; -end else if (enable) begin +end else if (enable) begin data <= q_in; end diff --git a/tests/asicworld/code_verilog_tutorial_bus_con.v b/tests/asicworld/code_verilog_tutorial_bus_con.v index b100c8136..7815f0469 100644 --- a/tests/asicworld/code_verilog_tutorial_bus_con.v +++ b/tests/asicworld/code_verilog_tutorial_bus_con.v @@ -2,7 +2,7 @@ module bus_con (a,b, y); input [3:0] a, b; output [7:0] y; wire [7:0] y; - + assign y = {a,b}; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_comment.v b/tests/asicworld/code_verilog_tutorial_comment.v index 1cc0eb424..62d5875c5 100644 --- a/tests/asicworld/code_verilog_tutorial_comment.v +++ b/tests/asicworld/code_verilog_tutorial_comment.v @@ -15,11 +15,11 @@ input ci; // Output ports output sum; output co; -// Data Types +// Data Types wire a; wire b; wire ci; wire sum; -wire co; +wire co; endmodule diff --git a/tests/asicworld/code_verilog_tutorial_counter.v b/tests/asicworld/code_verilog_tutorial_counter.v index 10ca00df4..6018d07f7 100644 --- a/tests/asicworld/code_verilog_tutorial_counter.v +++ b/tests/asicworld/code_verilog_tutorial_counter.v @@ -7,7 +7,7 @@ module counter (clk, reset, enable, count); input clk, reset, enable; output [3:0] count; -reg [3:0] count; +reg [3:0] count; always @ (posedge clk) if (reset == 1'b1) begin @@ -16,4 +16,4 @@ end else if ( enable == 1'b1) begin count <= count + 1; end -endmodule +endmodule diff --git a/tests/asicworld/code_verilog_tutorial_d_ff.v b/tests/asicworld/code_verilog_tutorial_d_ff.v index 7a4083605..ba18b708a 100644 --- a/tests/asicworld/code_verilog_tutorial_d_ff.v +++ b/tests/asicworld/code_verilog_tutorial_d_ff.v @@ -4,7 +4,7 @@ input d ,clk; output q, q_bar; wire d ,clk; reg q, q_bar; - + always @ (posedge clk) begin q <= d; diff --git a/tests/asicworld/code_verilog_tutorial_decoder.v b/tests/asicworld/code_verilog_tutorial_decoder.v index 5efdbd7e7..6cb4c7999 100644 --- a/tests/asicworld/code_verilog_tutorial_decoder.v +++ b/tests/asicworld/code_verilog_tutorial_decoder.v @@ -2,13 +2,13 @@ module decoder (in,out); input [2:0] in; output [7:0] out; wire [7:0] out; -assign out = (in == 3'b000 ) ? 8'b0000_0001 : -(in == 3'b001 ) ? 8'b0000_0010 : -(in == 3'b010 ) ? 8'b0000_0100 : -(in == 3'b011 ) ? 8'b0000_1000 : -(in == 3'b100 ) ? 8'b0001_0000 : -(in == 3'b101 ) ? 8'b0010_0000 : -(in == 3'b110 ) ? 8'b0100_0000 : +assign out = (in == 3'b000 ) ? 8'b0000_0001 : +(in == 3'b001 ) ? 8'b0000_0010 : +(in == 3'b010 ) ? 8'b0000_0100 : +(in == 3'b011 ) ? 8'b0000_1000 : +(in == 3'b100 ) ? 8'b0001_0000 : +(in == 3'b101 ) ? 8'b0010_0000 : +(in == 3'b110 ) ? 8'b0100_0000 : (in == 3'b111 ) ? 8'b1000_0000 : 8'h00; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_decoder_always.v b/tests/asicworld/code_verilog_tutorial_decoder_always.v index 4418ec700..5b31a2414 100644 --- a/tests/asicworld/code_verilog_tutorial_decoder_always.v +++ b/tests/asicworld/code_verilog_tutorial_decoder_always.v @@ -2,7 +2,7 @@ module decoder_always (in,out); input [2:0] in; output [7:0] out; reg [7:0] out; - + always @ (in) begin out = 0; @@ -16,5 +16,5 @@ begin 3'b111 : out = 8'b1000_0000; endcase end - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_escape_id.v b/tests/asicworld/code_verilog_tutorial_escape_id.v index 6c33da174..54eab1141 100644 --- a/tests/asicworld/code_verilog_tutorial_escape_id.v +++ b/tests/asicworld/code_verilog_tutorial_escape_id.v @@ -9,6 +9,6 @@ cl$k, // CLOCK input ); input d, cl$k, \reset* ; -output q, \q~ ; +output q, \q~ ; endmodule diff --git a/tests/asicworld/code_verilog_tutorial_explicit.v b/tests/asicworld/code_verilog_tutorial_explicit.v index 88427ff08..267db56ed 100644 --- a/tests/asicworld/code_verilog_tutorial_explicit.v +++ b/tests/asicworld/code_verilog_tutorial_explicit.v @@ -4,7 +4,7 @@ wire q; // Here q_bar is not connected // We can connect ports in any order -dff u0 ( +dff u0 ( .q (q), .d (d), .clk (clk), diff --git a/tests/asicworld/code_verilog_tutorial_first_counter.v b/tests/asicworld/code_verilog_tutorial_first_counter.v index d35d4aacc..c257bae64 100644 --- a/tests/asicworld/code_verilog_tutorial_first_counter.v +++ b/tests/asicworld/code_verilog_tutorial_first_counter.v @@ -19,7 +19,7 @@ input enable ; //-------------Output Ports---------------------------- output [3:0] counter_out ; //-------------Input ports Data Type------------------- -// By rule all the input ports should be wires +// By rule all the input ports should be wires wire clock ; wire reset ; wire enable ; diff --git a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v index 806e17736..bdca371e5 100644 --- a/tests/asicworld/code_verilog_tutorial_first_counter_tb.v +++ b/tests/asicworld/code_verilog_tutorial_first_counter_tb.v @@ -5,9 +5,9 @@ wire [3:0] counter_out; integer file; // Initialize all variables -initial begin +initial begin file = $fopen(`outfile); - $fdisplay (file, "time\t clk reset enable counter"); + $fdisplay (file, "time\t clk reset enable counter"); #5 reset = 1; // Assert the reset #10 reset = 0; // De-assert the reset #10 enable = 1; // Assert enable @@ -16,8 +16,8 @@ initial begin end always @(negedge clock) - $fdisplay (file, "%g\t %b %b %b %b", - $time, clock, reset, enable, counter_out); + $fdisplay (file, "%g\t %b %b %b %b", + $time, clock, reset, enable, counter_out); // Clock generator initial begin diff --git a/tests/asicworld/code_verilog_tutorial_flip_flop.v b/tests/asicworld/code_verilog_tutorial_flip_flop.v index ed2e88c2e..aeb784423 100644 --- a/tests/asicworld/code_verilog_tutorial_flip_flop.v +++ b/tests/asicworld/code_verilog_tutorial_flip_flop.v @@ -2,7 +2,7 @@ module flif_flop (clk,reset, q, d); input clk, reset, d; output q; reg q; - + always @ (posedge clk ) begin if (reset == 1) begin @@ -11,5 +11,5 @@ begin q <= d; end end - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full.v b/tests/asicworld/code_verilog_tutorial_fsm_full.v index fd2d559bb..0be754c97 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full.v @@ -20,13 +20,13 @@ input req_3 ; // Active high request from agent 3 output gnt_0 ; // Active high grant to agent 0 output gnt_1 ; // Active high grant to agent 1 output gnt_2 ; // Active high grant to agent 2 -output gnt_3 ; // Active high grant to agent +output gnt_3 ; // Active high grant to agent // Internal Variables reg gnt_0 ; // Active high grant to agent 0 reg gnt_1 ; // Active high grant to agent 1 reg gnt_2 ; // Active high grant to agent 2 -reg gnt_3 ; // Active high grant to agent +reg gnt_3 ; // Active high grant to agent parameter [2:0] IDLE = 3'b000; parameter [2:0] GNT0 = 3'b001; @@ -37,7 +37,7 @@ parameter [2:0] GNT3 = 3'b100; reg [2:0] state, next_state; always @ (state or req_0 or req_1 or req_2 or req_3) -begin +begin next_state = 0; case(state) IDLE : if (req_0 == 1'b1) begin @@ -50,7 +50,7 @@ begin next_state= GNT3; end else begin next_state = IDLE; - end + end GNT0 : if (req_0 == 1'b0) begin next_state = IDLE; end else begin diff --git a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v index a8e15568b..7c0e2d570 100644 --- a/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v +++ b/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v @@ -1,6 +1,6 @@ module testbench(); reg clock = 0 , reset ; -reg req_0 , req_1 , req_2 , req_3; +reg req_0 , req_1 , req_2 , req_3; wire gnt_0 , gnt_1 , gnt_2 , gnt_3 ; integer file; @@ -29,7 +29,7 @@ initial begin end always @(negedge clock) - $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", + $fdisplay(file, "%g\t %b %b %b %b %b %b %b %b", $time, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); initial begin diff --git a/tests/asicworld/code_verilog_tutorial_multiply.v b/tests/asicworld/code_verilog_tutorial_multiply.v index 1912e1e26..bcab608cb 100644 --- a/tests/asicworld/code_verilog_tutorial_multiply.v +++ b/tests/asicworld/code_verilog_tutorial_multiply.v @@ -2,7 +2,7 @@ module muliply (a,product); input [3:0] a; output [4:0] product; wire [4:0] product; - + assign product = a << 1; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_mux_21.v b/tests/asicworld/code_verilog_tutorial_mux_21.v index a6a0d35eb..70f57205b 100644 --- a/tests/asicworld/code_verilog_tutorial_mux_21.v +++ b/tests/asicworld/code_verilog_tutorial_mux_21.v @@ -3,7 +3,7 @@ module mux_21 (a,b,sel,y); output y; input sel; wire y; - + assign y = (sel) ? b : a; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_n_out_primitive.v b/tests/asicworld/code_verilog_tutorial_n_out_primitive.v index 814385a45..b85738417 100644 --- a/tests/asicworld/code_verilog_tutorial_n_out_primitive.v +++ b/tests/asicworld/code_verilog_tutorial_n_out_primitive.v @@ -5,9 +5,9 @@ wire in; // one output Buffer gate buf u_buf0 (out,in); -// four output Buffer gate +// four output Buffer gate buf u_buf1 (out_0, out_1, out_2, out_3, in); -// three output Invertor gate +// three output Invertor gate not u_not0 (out_a, out_b, out_c, in); - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_parallel_if.v b/tests/asicworld/code_verilog_tutorial_parallel_if.v index 1dbe737eb..1cf8658b0 100644 --- a/tests/asicworld/code_verilog_tutorial_parallel_if.v +++ b/tests/asicworld/code_verilog_tutorial_parallel_if.v @@ -6,7 +6,7 @@ wire clk,reset,enable, up_en, down_en; always @ (posedge clk) // If reset is asserted if (reset == 1'b0) begin - counter <= 4'b0000; + counter <= 4'b0000; end else begin // If counter is enable and up count is mode if (enable == 1'b1 && up_en == 1'b1) begin @@ -15,7 +15,7 @@ end else begin // If counter is enable and down count is mode if (enable == 1'b1 && down_en == 1'b1) begin counter <= counter - 1'b1; - end -end + end +end endmodule diff --git a/tests/asicworld/code_verilog_tutorial_parity.v b/tests/asicworld/code_verilog_tutorial_parity.v index 764396c2f..27941f309 100644 --- a/tests/asicworld/code_verilog_tutorial_parity.v +++ b/tests/asicworld/code_verilog_tutorial_parity.v @@ -8,7 +8,7 @@ //----------------------------------------------------- module parity ( a , // First input -b , // Second input +b , // Second input c , // Third Input d , // Fourth Input y // Parity output @@ -38,4 +38,4 @@ xor u1 (out_1,c,d); xor u2 (y,out_0,out_1); -endmodule // End Of Module parity +endmodule // End Of Module parity diff --git a/tests/asicworld/code_verilog_tutorial_simple_if.v b/tests/asicworld/code_verilog_tutorial_simple_if.v index a68cc4a87..67fa8bcb1 100644 --- a/tests/asicworld/code_verilog_tutorial_simple_if.v +++ b/tests/asicworld/code_verilog_tutorial_simple_if.v @@ -6,6 +6,6 @@ wire enable,din; always @ (enable or din) if (enable) begin latch <= din; -end +end endmodule diff --git a/tests/asicworld/code_verilog_tutorial_tri_buf.v b/tests/asicworld/code_verilog_tutorial_tri_buf.v index a55b29caa..3df0d7009 100644 --- a/tests/asicworld/code_verilog_tutorial_tri_buf.v +++ b/tests/asicworld/code_verilog_tutorial_tri_buf.v @@ -3,7 +3,7 @@ module tri_buf (a,b,enable); output b; input enable; wire b; - + assign b = (enable) ? a : 1'bz; - + endmodule diff --git a/tests/asicworld/code_verilog_tutorial_which_clock.v b/tests/asicworld/code_verilog_tutorial_which_clock.v index 418a2cfac..934015ac0 100644 --- a/tests/asicworld/code_verilog_tutorial_which_clock.v +++ b/tests/asicworld/code_verilog_tutorial_which_clock.v @@ -4,7 +4,7 @@ output q; reg q; always @ (posedge x or posedge y) - if (x) + if (x) q <= 1'b0; else q <= d; diff --git a/tests/bugpoint/procs.il b/tests/bugpoint/procs.il index cb9f7c8dd..e780dc7cd 100644 --- a/tests/bugpoint/procs.il +++ b/tests/bugpoint/procs.il @@ -13,11 +13,11 @@ module \ff_with_en_and_sync_reset switch \reset case 1'1 assign $0\q[0:0] 1'0 - case + case switch \enable case 1'1 assign $0\q[0:0] \d [0] - case + case end end sync posedge \clock @@ -29,11 +29,11 @@ module \ff_with_en_and_sync_reset switch \reset case 1'1 assign $0\q[1:1] 1'0 - case + case switch \enable case 1'1 assign $0\q[1:1] \d [1] - case + case end end sync posedge \clock diff --git a/tests/cxxrtl/test_value_fuzz.cc b/tests/cxxrtl/test_value_fuzz.cc index a77120136..500f48a7a 100644 --- a/tests/cxxrtl/test_value_fuzz.cc +++ b/tests/cxxrtl/test_value_fuzz.cc @@ -88,7 +88,7 @@ void test_binary_operation(Operation &op) } template -struct UnaryOperationWrapper : BinaryOperationBase +struct UnaryOperationWrapper : BinaryOperationBase { Operation &op; @@ -113,7 +113,7 @@ void test_unary_operation(Operation &op) test_binary_operation(wrapped); } -struct ShlTest : BinaryOperationBase +struct ShlTest : BinaryOperationBase { ShlTest() { @@ -138,7 +138,7 @@ struct ShlTest : BinaryOperationBase } } shl; -struct ShrTest : BinaryOperationBase +struct ShrTest : BinaryOperationBase { ShrTest() { @@ -163,7 +163,7 @@ struct ShrTest : BinaryOperationBase } } shr; -struct SshrTest : BinaryOperationBase +struct SshrTest : BinaryOperationBase { SshrTest() { @@ -189,7 +189,7 @@ struct SshrTest : BinaryOperationBase } } sshr; -struct AddTest : BinaryOperationBase +struct AddTest : BinaryOperationBase { AddTest() { @@ -209,7 +209,7 @@ struct AddTest : BinaryOperationBase } } add; -struct SubTest : BinaryOperationBase +struct SubTest : BinaryOperationBase { SubTest() { diff --git a/tests/functional/README.md b/tests/functional/README.md index 1459c3198..12f975929 100644 --- a/tests/functional/README.md +++ b/tests/functional/README.md @@ -6,12 +6,12 @@ Pytest options you might want: - `-v`: More progress indication. -- `--basetemp tmp`: Store test files (including vcd results) in tmp. +- `--basetemp tmp`: Store test files (including vcd results) in tmp. CAREFUL: contents of tmp will be deleted - `-k `: Run only tests that contain the pattern, e.g. `-k cxx` or `-k smt` or `-k demux` or `-k 'cxx[demux` - + - `-s`: Don't hide stdout/stderr from the test code. Custom options for functional backend tests: diff --git a/tests/functional/rkt_vcd.py b/tests/functional/rkt_vcd.py index 548a4ba74..8ce73273f 100644 --- a/tests/functional/rkt_vcd.py +++ b/tests/functional/rkt_vcd.py @@ -15,7 +15,7 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to # Write the header f.write(f"$date\n {date}\n$end\n") f.write(f"$timescale {timescale} $end\n") - + # Declare signals f.write("$scope module gold $end\n") for signal_name, changes in signals.items(): @@ -23,17 +23,17 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") f.write("$upscope $end\n") f.write("$enddefinitions $end\n") - + # Collect all unique timestamps timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) - + # Write initial values f.write("#0\n") for signal_name, changes in signals.items(): for time, value in changes: if time == 0: f.write(f"{value} {signal_name}\n") - + # Write value changes for time in timestamps: if time != 0: diff --git a/tests/functional/smt_vcd.py b/tests/functional/smt_vcd.py index 73e28b2b2..162ddf094 100644 --- a/tests/functional/smt_vcd.py +++ b/tests/functional/smt_vcd.py @@ -77,14 +77,14 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): smt_io.write(smt_io.unparse(expr)) if expr[0] == "declare-datatype": handle_datatype(expr) - + parser.finish() assert smt_io.check_sat() == 'sat' def set_step(inputs, step): # This function assumes 'inputs' is a dictionary like {"A": 5, "B": 4} # and 'input_values' is a dictionary like {"A": 5, "B": 13} specifying the concrete values for each input. - + mk_inputs_parts = [] for input_name, width in inputs.items(): value = rnd.getrandbits(width) # Generate a random number up to the maximum value for the bit size @@ -125,7 +125,7 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): for input_name, width in inputs.items(): value = smt_io.get(f'(gold_Inputs_{input_name} test_inputs_step_n{step})') value = hex_to_bin(value[1:]) - print(f" {input_name}: {value}") + print(f" {input_name}: {value}") signals[input_name].append((step, value)) for output_name, width in outputs.items(): value = smt_io.get(f'(gold_Outputs_{output_name} test_outputs_step_n{step})') @@ -145,7 +145,7 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): # Write the header f.write(f"$date\n {date}\n$end\n") f.write(f"$timescale {timescale} $end\n") - + # Declare signals f.write("$scope module gold $end\n") for signal_name, changes in signals.items(): @@ -153,17 +153,17 @@ def simulate_smt_with_smtio(smt_file_path, vcd_path, smt_io, num_steps, rnd): f.write(f"$var wire {signal_size - 1} {signal_name} {signal_name} $end\n") f.write("$upscope $end\n") f.write("$enddefinitions $end\n") - + # Collect all unique timestamps timestamps = sorted(set(time for changes in signals.values() for time, _ in changes)) - + # Write initial values f.write("#0\n") for signal_name, changes in signals.items(): for time, value in changes: if time == 0: f.write(f"{value} {signal_name}\n") - + # Write value changes for time in timestamps: if time != 0: diff --git a/tests/hana/hana_vlib.v b/tests/hana/hana_vlib.v index a8921bcfd..1b3d18191 100644 --- a/tests/hana/hana_vlib.v +++ b/tests/hana/hana_vlib.v @@ -1,4 +1,4 @@ -/* +/* Copyright (C) 2009-2010 Parvez Ahmad Written by Parvez Ahmad . @@ -45,7 +45,7 @@ module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ∈ endmodule - + module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ∈ @@ -63,7 +63,7 @@ module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = |in; endmodule - + module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = |in; @@ -82,7 +82,7 @@ module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~∈ endmodule - + module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~∈ @@ -100,7 +100,7 @@ module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~|in; endmodule - + module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~|in; @@ -119,7 +119,7 @@ module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ^in; endmodule - + module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ^in; @@ -138,7 +138,7 @@ module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out); assign out = ~^in; endmodule - + module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out); assign out = ~^in; @@ -156,7 +156,7 @@ always @(in or enable) 1'b1 : out = 2'b10; endcase end -endmodule +endmodule module DEC2 (input [1:0] in, input enable, output reg [3:0] out); @@ -171,7 +171,7 @@ always @(in or enable) 2'b11 : out = 4'b1000; endcase end -endmodule +endmodule module DEC3 (input [2:0] in, input enable, output reg [7:0] out); @@ -190,7 +190,7 @@ always @(in or enable) 3'b111 : out = 8'b10000000; endcase end -endmodule +endmodule module DEC4 (input [3:0] in, input enable, output reg [15:0] out); @@ -217,7 +217,7 @@ always @(in or enable) 4'b1111 : out = 16'b1000000000000000; endcase end -endmodule +endmodule module DEC5 (input [4:0] in, input enable, output reg [31:0] out); always @(in or enable) @@ -259,7 +259,7 @@ always @(in or enable) 5'b11111 : out = 32'b10000000000000000000000000000000; endcase end -endmodule +endmodule module DEC6 (input [5:0] in, input enable, output reg [63:0] out); @@ -335,7 +335,7 @@ always @(in or enable) 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase end -endmodule +endmodule module MUX2(input [1:0] in, input select, output reg out); @@ -345,7 +345,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule module MUX4(input [3:0] in, input [1:0] select, output reg out); @@ -357,7 +357,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule module MUX8(input [7:0] in, input [2:0] select, output reg out); @@ -373,7 +373,7 @@ always @( in or select) 6: out = in[6]; 7: out = in[7]; endcase -endmodule +endmodule module MUX16(input [15:0] in, input [3:0] select, output reg out); @@ -396,7 +396,7 @@ always @( in or select) 14: out = in[14]; 15: out = in[15]; endcase -endmodule +endmodule module MUX32(input [31:0] in, input [4:0] select, output reg out); @@ -435,7 +435,7 @@ always @( in or select) 30: out = in[30]; 31: out = in[31]; endcase -endmodule +endmodule module MUX64(input [63:0] in, input [5:0] select, output reg out); @@ -506,7 +506,7 @@ always @( in or select) 62: out = in[62]; 63: out = in[63]; endcase -endmodule +endmodule module ADD1(input in1, in2, cin, output out, cout); @@ -514,41 +514,41 @@ assign {cout, out} = in1 + in2 + cin; endmodule -module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; endmodule -module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 + in2 + cin; @@ -561,41 +561,41 @@ assign {cout, out} = in1 - in2 - cin; endmodule -module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; endmodule -module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, input cin, output [SIZE-1:0] out, output cout); assign {cout, out} = in1 - in2 - cin; @@ -651,7 +651,7 @@ assign rem = in1%in2; endmodule -module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, +module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -659,7 +659,7 @@ assign rem = in1%in2; endmodule -module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, +module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -667,7 +667,7 @@ assign rem = in1%in2; endmodule -module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, +module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -675,7 +675,7 @@ assign rem = in1%in2; endmodule -module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, +module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -683,7 +683,7 @@ assign rem = in1%in2; endmodule -module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, +module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -691,7 +691,7 @@ assign rem = in1%in2; endmodule -module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, +module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, output [SIZE-1:0] out, rem); assign out = in1/in2; @@ -711,7 +711,7 @@ always @(posedge clk or posedge reset) q <= 0; else q <= d; -endmodule +endmodule module SFF(input d, clk, set, output reg q); always @(posedge clk or posedge set) @@ -719,7 +719,7 @@ always @(posedge clk or posedge set) q <= 1; else q <= d; -endmodule +endmodule module RSFF(input d, clk, set, reset, output reg q); always @(posedge clk or posedge reset or posedge set) @@ -745,30 +745,30 @@ module LATCH(input d, enable, output reg q); always @( d or enable) if(enable) q <= d; -endmodule +endmodule module RLATCH(input d, reset, enable, output reg q); always @( d or enable or reset) if(enable) if(reset) q <= 0; - else + else q <= d; -endmodule +endmodule module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out); always @ (in, shift, val) begin if(shift) out = val; - else + else out = in; end endmodule -module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, +module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, input [SIZE-1:0] shift, input val, output reg [SIZE-1:0] out); @@ -776,58 +776,58 @@ always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, +module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, input [2:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, +module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, input [3:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, +module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, input [4:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, +module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, input [5:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule -module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, +module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, input [6:0] shift, input val, output reg [SIZE-1:0] out); always @(in or shift or val) begin out = in << shift; if(val) out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift)); -end +end endmodule module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out); @@ -841,7 +841,7 @@ end endmodule -module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, +module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, input [SIZE-1:0] shift, input val, output reg [SIZE-1:0] out); @@ -849,12 +849,12 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, +module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, input [2:0] shift, input val, output reg [SIZE-1:0] out); @@ -862,10 +862,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, +module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, input [3:0] shift, input val, output reg [SIZE-1:0] out); @@ -873,11 +873,11 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, +module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, input [4:0] shift, input val, output reg [SIZE-1:0] out); @@ -885,11 +885,11 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, +module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, input [5:0] shift, input val, output reg [SIZE-1:0] out); @@ -897,10 +897,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, +module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, input [6:0] shift, input val, output reg [SIZE-1:0] out); @@ -908,10 +908,10 @@ always @(in or shift or val) begin out = in >> shift; if(val) out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift)); -end +end endmodule -module CMP1 #(parameter SIZE = 1) (input in1, in2, +module CMP1 #(parameter SIZE = 1) (input in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -920,7 +920,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -928,17 +928,17 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, +module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -947,7 +947,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -955,16 +955,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, +module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -973,7 +973,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -981,16 +981,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, +module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -999,7 +999,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1007,16 +1007,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, +module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1025,7 +1025,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1033,16 +1033,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, +module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1051,7 +1051,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1059,16 +1059,16 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule -module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, +module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, output reg equal, unequal, greater, lesser); always @ (in1 or in2) begin @@ -1077,7 +1077,7 @@ always @ (in1 or in2) begin unequal = 0; greater = 0; lesser = 0; - end + end else begin equal = 0; unequal = 1; @@ -1085,12 +1085,12 @@ always @ (in1 or in2) begin if(in1 < in2) begin greater = 0; lesser = 1; - end + end else begin greater = 1; lesser = 0; - end - end + end + end end endmodule diff --git a/tests/hana/test_intermout.v b/tests/hana/test_intermout.v index 88b91ee4d..649f78a0d 100644 --- a/tests/hana/test_intermout.v +++ b/tests/hana/test_intermout.v @@ -10,7 +10,7 @@ begin temp1 = a ^ b; temp2 = c ^ d; z = temp1 ^ temp2; -end +end endmodule @@ -24,7 +24,7 @@ always @ ( in1 or in2) out = in1; else out = in2; -endmodule +endmodule // test_intermout_always_comb_4_test.v module f3_test(a, b, c); @@ -46,9 +46,9 @@ output reg out; always @ (ctrl or in1 or in2) if(ctrl) out = in1 & in2; - else + else out = in1 | in2; -endmodule +endmodule // test_intermout_always_ff_3_test.v module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim); @@ -78,7 +78,7 @@ always @(posedge clk) is <= cs; assign ns = is; -endmodule +endmodule // test_intermout_always_ff_5_test.v module f7_FlipFlop(clock, cs, ns); @@ -91,9 +91,9 @@ always @(posedge clock) begin temp = cs; ns = temp; -end +end -endmodule +endmodule // test_intermout_always_ff_6_test.v module f8_inc(clock, counter); @@ -102,7 +102,7 @@ input clock; output reg [3:0] counter; always @(posedge clock) counter <= counter + 1; -endmodule +endmodule // test_intermout_always_ff_8_test.v module f9_NegEdgeClock(q, d, clk, reset); @@ -112,7 +112,7 @@ output reg q; always @(negedge clk or negedge reset) if(!reset) q <= 1'b0; - else + else q <= d; endmodule @@ -131,7 +131,7 @@ always @(posedge clock) counter <= counter + 1; else counter <= counter - 1; -endmodule +endmodule // test_intermout_always_latch_1_test.v module f11_test(en, in, out); @@ -142,7 +142,7 @@ output reg [2:0] out; always @ (en or in) if(en) out = in + 1; -endmodule +endmodule // test_intermout_bufrm_1_test.v module f12_test(input in, output out); @@ -364,20 +364,20 @@ endmodule // test_intermout_exprs_redop_test.v module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6); -input [1:0] A1; -input [1:0] A2; -input [1:0] A3; -input [1:0] A4; -input [1:0] A5; -input [1:0] A6; -output Y1, Y2, Y3, Y4, Y5, Y6; -//reg Y1, Y2, Y3, Y4, Y5, Y6; -assign Y1=&A1; //reduction AND -assign Y2=|A2; //reduction OR -assign Y3=~&A3; //reduction NAND -assign Y4=~|A4; //reduction NOR -assign Y5=^A5; //reduction XOR -assign Y6=~^A6; //reduction XNOR +input [1:0] A1; +input [1:0] A2; +input [1:0] A3; +input [1:0] A4; +input [1:0] A5; +input [1:0] A6; +output Y1, Y2, Y3, Y4, Y5, Y6; +//reg Y1, Y2, Y3, Y4, Y5, Y6; +assign Y1=&A1; //reduction AND +assign Y2=|A2; //reduction OR +assign Y3=~&A3; //reduction NAND +assign Y4=~|A4; //reduction NOR +assign Y5=^A5; //reduction XOR +assign Y6=~^A6; //reduction XNOR endmodule // test_intermout_exprs_sub_test.v diff --git a/tests/hana/test_parse2synthtrans.v b/tests/hana/test_parse2synthtrans.v index 19943ffb5..7185065fb 100644 --- a/tests/hana/test_parse2synthtrans.v +++ b/tests/hana/test_parse2synthtrans.v @@ -18,7 +18,7 @@ always @(clk or reset) begin d = d*d; if(b) e = d*d; - else + else e = d + d; end endmodule diff --git a/tests/hana/test_simulation_always.v b/tests/hana/test_simulation_always.v index 3ee75313a..0da8e43bd 100644 --- a/tests/hana/test_simulation_always.v +++ b/tests/hana/test_simulation_always.v @@ -4,7 +4,7 @@ module f1_test(input [1:0] in, output reg [1:0] out); always @(in) out = in; -endmodule +endmodule // test_simulation_always_17_test.v module f2_test(a, b, c, d, z); @@ -17,7 +17,7 @@ begin temp1 = a ^ b; temp2 = c ^ d; z = temp1 ^ temp2; -end +end endmodule @@ -31,7 +31,7 @@ always @ ( in1 or in2) out = in1; else out = in2; -endmodule +endmodule // test_simulation_always_19_test.v module f4_test(ctrl, in1, in2, out); @@ -42,16 +42,16 @@ output reg out; always @ (ctrl or in1 or in2) if(ctrl) out = in1 & in2; - else + else out = in1 | in2; -endmodule +endmodule // test_simulation_always_1_test.v module f5_test(input in, output reg out); always @(in) out = in; -endmodule +endmodule // test_simulation_always_20_test.v module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim); @@ -81,7 +81,7 @@ always @(posedge clk) is <= cs; assign ns = is; -endmodule +endmodule // test_simulation_always_22_test.v module f8_inc(clock, counter); @@ -90,7 +90,7 @@ input clock; output reg [7:0] counter; always @(posedge clock) counter <= counter + 1; -endmodule +endmodule // test_simulation_always_23_test.v module f9_MyCounter (clock, preset, updown, presetdata, counter); @@ -106,7 +106,7 @@ always @(posedge clock) counter <= counter + 1; else counter <= counter - 1; -endmodule +endmodule // test_simulation_always_27_test.v module f10_FlipFlop(clock, cs, ns); @@ -119,9 +119,9 @@ always @(posedge clock) begin temp <= cs; ns <= temp; -end +end -endmodule +endmodule // test_simulation_always_29_test.v module f11_test(input in, output reg [1:0] out); diff --git a/tests/hana/test_simulation_decoder.v b/tests/hana/test_simulation_decoder.v index 2a102a903..311d425c8 100644 --- a/tests/hana/test_simulation_decoder.v +++ b/tests/hana/test_simulation_decoder.v @@ -45,7 +45,7 @@ always @(in ) 3'b110 : out = 8'b01000000; 3'b111 : out = 8'b10000000; endcase -endmodule +endmodule // test_simulation_decoder_5_test.v module f4_test (input [2:0] in, input enable, output reg [7:0] out); @@ -53,7 +53,7 @@ module f4_test (input [2:0] in, input enable, output reg [7:0] out); always @(in or enable ) if(!enable) out = 8'b00000000; - else + else case (in) 3'b000 : out = 8'b00000001; 3'b001 : out = 8'b00000010; @@ -64,7 +64,7 @@ always @(in or enable ) 3'b110 : out = 8'b01000000; 3'b111 : out = 8'b10000000; endcase -endmodule +endmodule // test_simulation_decoder_6_test.v module f5_test (input [3:0] in, input enable, output reg [15:0] out); @@ -92,7 +92,7 @@ always @(in or enable) 4'b1111 : out = 16'b1000000000000000; endcase end -endmodule +endmodule // test_simulation_decoder_7_test.v @@ -137,7 +137,7 @@ always @(in or enable) 5'b11111 : out = 32'b10000000000000000000000000000000; endcase end -endmodule +endmodule // test_simulation_decoder_8_test.v @@ -215,4 +215,4 @@ always @(in or enable) 6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase end -endmodule +endmodule diff --git a/tests/hana/test_simulation_mux.v b/tests/hana/test_simulation_mux.v index 085387eff..6fc912893 100644 --- a/tests/hana/test_simulation_mux.v +++ b/tests/hana/test_simulation_mux.v @@ -31,7 +31,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule // test_simulation_mux_32_test.v module f3_test(input [31:0] in, input [4:0] select, output reg out); @@ -71,7 +71,7 @@ always @( in or select) 30: out = in[30]; 31: out = in[31]; endcase -endmodule +endmodule // test_simulation_mux_4_test.v @@ -84,7 +84,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule // test_simulation_mux_64_test.v module f5_test(input [63:0] in, input [5:0] select, output reg out); @@ -156,7 +156,7 @@ always @( in or select) 62: out = in[62]; 63: out = in[63]; endcase -endmodule +endmodule // test_simulation_mux_8_test.v diff --git a/tests/hana/test_simulation_seq.v b/tests/hana/test_simulation_seq.v index eba4e88ea..d5069bb76 100644 --- a/tests/hana/test_simulation_seq.v +++ b/tests/hana/test_simulation_seq.v @@ -3,10 +3,10 @@ module f1_test(input in, input clk, output reg out); always @(posedge clk) out <= in; -endmodule +endmodule // test_simulation_seq_ff_2_test.v module f2_test(input in, input clk, output reg out); always @(negedge clk) out <= in; -endmodule +endmodule diff --git a/tests/hana/test_simulation_sop.v b/tests/hana/test_simulation_sop.v index 79870cf0c..9373ea085 100644 --- a/tests/hana/test_simulation_sop.v +++ b/tests/hana/test_simulation_sop.v @@ -7,7 +7,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule // test_simulation_sop_basic_11_test.v module f2_test(input [3:0] in, input [1:0] select, output reg out); @@ -19,7 +19,7 @@ always @( in or select) 2: out = in[2]; 3: out = in[3]; endcase -endmodule +endmodule // test_simulation_sop_basic_12_test.v module f3_test(input [7:0] in, input [2:0] select, output reg out); diff --git a/tests/hana/test_simulation_techmap.v b/tests/hana/test_simulation_techmap.v index 88e24d0e7..65dd88d86 100644 --- a/tests/hana/test_simulation_techmap.v +++ b/tests/hana/test_simulation_techmap.v @@ -17,7 +17,7 @@ always @( in or select) 0: out = in[0]; 1: out = in[1]; endcase -endmodule +endmodule // test_simulation_techmap_mux_128_test.v module f4_test(input [127:0] in, input [6:0] select, output reg out); diff --git a/tests/hana/test_simulation_vlib.v b/tests/hana/test_simulation_vlib.v index cdf3c56db..49f612b80 100644 --- a/tests/hana/test_simulation_vlib.v +++ b/tests/hana/test_simulation_vlib.v @@ -44,14 +44,14 @@ AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out( AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out( synth_net_11)); BUF synth_BUF(.in(synth_net), .out(synth_net_0)); -BUF +BUF synth_BUF_0(.in(data), .out(synth_net_3)); BUF synth_BUF_1(.in(synth_net_8) , .out(tmp)); BUF synth_BUF_2(.in(tmp), .out(synth_net_9)); MUX2 synth_MUX(. in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6)); -MUX2 +MUX2 synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7 )); FF synth_FF(.d(synth_net_11), .clk(clk), .q(data)); diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib index b5e3d50b9..10c45cd99 100644 --- a/tests/liberty/busdef.lib +++ b/tests/liberty/busdef.lib @@ -15,14 +15,14 @@ library(supergate) { technology (cmos); revision : 1.0; - + time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; - + current_unit : "1uA"; + capacitive_load_unit(1,ff); - + default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; @@ -35,9 +35,9 @@ library(supergate) { nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; - + delay_model : generic_cmos; - + type( IO_bus_3_to_0 ) { base_type : array ; data_type : bit ; diff --git a/tests/liberty/dff.lib b/tests/liberty/dff.lib index b5df36587..0f725fd9d 100644 --- a/tests/liberty/dff.lib +++ b/tests/liberty/dff.lib @@ -6,7 +6,7 @@ library(dff) { ff("IQ", "IQN") { next_state : "(D)"; clocked_on : (CLK); - } + } pin(D) { direction : input; } @@ -15,7 +15,7 @@ library(dff) { } pin(Q) { direction: output; - function : IQ; + function : IQ; } } diff --git a/tests/liberty/issue3498_bad.lib b/tests/liberty/issue3498_bad.lib index f85c4e19b..9f2a90295 100644 --- a/tests/liberty/issue3498_bad.lib +++ b/tests/liberty/issue3498_bad.lib @@ -1,8 +1,8 @@ -library(fake) { - cell(bugbad) { - bundle(X) { +library(fake) { + cell(bugbad) { + bundle(X) { members(x1, x2); - power_down_function : !a+b ; + power_down_function : !a+b ; } } } diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib index 4621194dd..d8cc1d91b 100644 --- a/tests/liberty/normal.lib +++ b/tests/liberty/normal.lib @@ -15,14 +15,14 @@ library(supergate) { technology (cmos); revision : 1.0; - + time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; - + current_unit : "1uA"; + capacitive_load_unit(1,ff); - + default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; @@ -35,27 +35,27 @@ library(supergate) { nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; - + delay_model : generic_cmos; - + /* Inverter */ cell (inv) { area : 1; pin(A) { direction : input; } - + pin(Y) { direction : output; function : "A'"; } } - + /* tri-state inverter */ cell (tri_inv) { area : 4; pin(A) { - direction : input; + direction : input; } pin(S) { direction : input; @@ -66,7 +66,7 @@ library(supergate) { three_State : "S'"; } } - + cell (buffer) { area : 5; pin(A) { @@ -76,8 +76,8 @@ library(supergate) { direction : output; function : "A"; } - } - + } + /* 2-input NAND gate */ cell (nand2) { area : 3; @@ -92,7 +92,7 @@ library(supergate) { function : "(A * B)'"; } } - + /* 2-input NOR gate */ cell (nor2) { area : 3; @@ -107,7 +107,7 @@ library(supergate) { function : "(A + B)'"; } } - + /* 2-input XOR */ cell (xor2) { area : 6; @@ -122,7 +122,7 @@ library(supergate) { function : "(A *B') + (A' * B)"; } } - + /* 2-input inverting MUX */ cell (imux2) { area : 5; @@ -134,13 +134,13 @@ library(supergate) { } pin(S) { direction : input; - } + } pin(Y) { direction: output; function : "( (A * S) + (B * S') )'"; } } - + /* D-type flip-flop with asynchronous reset and preset */ cell (dff) { area : 6; @@ -151,7 +151,7 @@ library(supergate) { preset : "PRESET"; clear_preset_var1 : L; clear_preset_var2 : L; - } + } pin(D) { direction : input; } @@ -172,7 +172,7 @@ library(supergate) { intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; - fall_resistance : 0; + fall_resistance : 0; related_pin : "CLK"; } timing () { @@ -186,7 +186,7 @@ library(supergate) { timing_sense : negative_unate; intrinsic_rise : 75; related_pin : "PRESET"; - } + } } pin(QN) { direction: output; @@ -196,7 +196,7 @@ library(supergate) { intrinsic_rise : 65; intrinsic_fall : 65; rise_resistance : 0; - fall_resistance : 0; + fall_resistance : 0; related_pin : "CLK"; } timing () { @@ -210,8 +210,8 @@ library(supergate) { timing_sense : positive_unate; intrinsic_fall : 75; related_pin : "PRESET"; - } - } + } + } } /* Latch */ @@ -228,12 +228,12 @@ library(supergate) { pin(G) { direction : input; } - + pin(Q) { direction : output; function : "IQ"; internal_node : "Q"; - + timing() { timing_type : rising_edge; intrinsic_rise : 65; @@ -242,7 +242,7 @@ library(supergate) { fall_resistance : 0; related_pin : "G"; } - + timing() { timing_sense : positive_unate; intrinsic_rise : 65; @@ -252,12 +252,12 @@ library(supergate) { related_pin : "D"; } } - + pin(QN) { direction : output; function : "IQN"; internal_node : "QN"; - + timing() { timing_type : rising_edge; intrinsic_rise : 65; @@ -266,7 +266,7 @@ library(supergate) { fall_resistance : 0; related_pin : "G"; } - + timing() { timing_sense : negative_unate; intrinsic_rise : 65; @@ -289,7 +289,7 @@ library(supergate) { } pin(C) { direction : input; - } + } pin(Y) { direction: output; function : "((A * B) + C)'"; @@ -308,7 +308,7 @@ library(supergate) { } pin(C) { direction : input; - } + } pin(Y) { direction: output; function : "((A + B) * C)'"; @@ -327,11 +327,11 @@ library(supergate) { pin(C) { direction : output; function : "(A * B)"; - } + } pin(Y) { direction: output; function : "(A *B') + (A' * B)"; - } + } } /* full adder */ @@ -345,7 +345,7 @@ library(supergate) { } pin(CI) { direction : input; - } + } pin(CO) { direction : output; function : "(((A * B)+(B * CI))+(CI * A))"; @@ -353,7 +353,7 @@ library(supergate) { pin(Y) { direction: output; function : "((A^B)^CI)"; - } + } } } /* end */ diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib index 37a6bbaf8..209ee148c 100644 --- a/tests/liberty/processdefs.lib +++ b/tests/liberty/processdefs.lib @@ -17,9 +17,9 @@ library(processdefs) { revision : 1.0; time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; + current_unit : "1uA"; capacitive_load_unit(1,ff); @@ -37,7 +37,7 @@ library(processdefs) { nom_voltage : 1.2; delay_model : generic_cmos; - + define_cell_area(bond_pads,pad_slots) input_voltage(cmos) { vil : 0.3 * VDD ; diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib index 6a7fa77cc..49b33d918 100644 --- a/tests/liberty/semicolextra.lib +++ b/tests/liberty/semicolextra.lib @@ -26,7 +26,7 @@ library(supergate) { "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \ "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); }; } - } + } pin(CK) { direction : input; diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib index a58bb7fe1..b18f14d9a 100644 --- a/tests/liberty/semicolmissing.lib +++ b/tests/liberty/semicolmissing.lib @@ -14,7 +14,7 @@ /* */ /********************************************/ -/* +/* semi colon is missing in full-adder specification some TSMC liberty files are formatted this way.. */ @@ -22,14 +22,14 @@ library(supergate) { technology (cmos); revision : 1.0; - + time_unit : "1ps"; - pulling_resistance_unit : "1kohm"; + pulling_resistance_unit : "1kohm"; voltage_unit : "1V"; - current_unit : "1uA"; - + current_unit : "1uA"; + capacitive_load_unit(1,ff); - + default_inout_pin_cap : 7.0; default_input_pin_cap : 7.0; default_output_pin_cap : 0.0; @@ -42,9 +42,9 @@ library(supergate) { nom_process : 1.0; nom_temperature : 25.0; nom_voltage : 1.2; - + delay_model : generic_cmos; - + /* full adder */ cell (fulladder) { area : 8 @@ -56,7 +56,7 @@ library(supergate) { } pin(CI) { direction : input - } + } pin(CO) { direction : output function : "(((A * B)+(B * CI))+(CI * A))" @@ -64,7 +64,7 @@ library(supergate) { pin(Y) { direction: output function : "((A^B)^CI)" - } + } } } /* end */ diff --git a/tests/liberty/small.v b/tests/liberty/small.v index bd94be4fc..89774881c 100644 --- a/tests/liberty/small.v +++ b/tests/liberty/small.v @@ -8,7 +8,7 @@ module small initial count = 0; -always @ (posedge clk) +always @ (posedge clk) begin count <= count + 1'b1; end diff --git a/tests/memlib/memlib_9b1B.txt b/tests/memlib/memlib_9b1B.txt index 4917aaf8b..53eed3250 100644 --- a/tests/memlib/memlib_9b1B.txt +++ b/tests/memlib/memlib_9b1B.txt @@ -3,7 +3,7 @@ ram block \RAM_9b1B { abits 7; widths 1 2 4 9 18 per_port; byte 9; - + ifdef INIT_NONE { option "INIT" "NONE" { init none; diff --git a/tests/memlib/memlib_9b1B.v b/tests/memlib/memlib_9b1B.v index 9a8246c9f..618e3a516 100644 --- a/tests/memlib/memlib_9b1B.v +++ b/tests/memlib/memlib_9b1B.v @@ -1,4 +1,4 @@ -module RAM_9b1B +module RAM_9b1B #( parameter INIT = 0, parameter OPTION_INIT = "UNDEFINED", diff --git a/tests/memlib/memlib_block_sp.v b/tests/memlib/memlib_block_sp.v index 1f7830137..63325604f 100644 --- a/tests/memlib/memlib_block_sp.v +++ b/tests/memlib/memlib_block_sp.v @@ -27,13 +27,13 @@ initial else if (OPTION_RDINIT == "ANY") PORT_A_RD_DATA = PORT_A_RD_INIT_VALUE; -localparam ARST_VALUE = +localparam ARST_VALUE = (OPTION_RDARST == "ZERO") ? 16'h0000 : (OPTION_RDARST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDARST == "ANY") ? PORT_A_RD_ARST_VALUE : 16'hxxxx; -localparam SRST_VALUE = +localparam SRST_VALUE = (OPTION_RDSRST == "ZERO") ? 16'h0000 : (OPTION_RDSRST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDSRST == "ANY") ? PORT_A_RD_SRST_VALUE : diff --git a/tests/memlib/memlib_block_sp_full.v b/tests/memlib/memlib_block_sp_full.v index 8ba32b9ed..c78c36990 100644 --- a/tests/memlib/memlib_block_sp_full.v +++ b/tests/memlib/memlib_block_sp_full.v @@ -28,13 +28,13 @@ initial else if (OPTION_RDINIT == "ANY") PORT_A_RD_DATA = PORT_A_RD_INIT_VALUE; -localparam ARST_VALUE = +localparam ARST_VALUE = (OPTION_RDARST == "ZERO") ? 16'h0000 : (OPTION_RDARST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDARST == "ANY") ? PORT_A_RD_ARST_VALUE : 16'hxxxx; -localparam SRST_VALUE = +localparam SRST_VALUE = (OPTION_RDSRST == "ZERO") ? 16'h0000 : (OPTION_RDSRST == "INIT") ? PORT_A_RD_INIT_VALUE : (OPTION_RDSRST == "ANY") ? PORT_A_RD_SRST_VALUE : diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v index 305339dd9..f134262f2 100644 --- a/tests/memories/issue00335.v +++ b/tests/memories/issue00335.v @@ -6,11 +6,11 @@ module ram2 #( parameter SIZE = 5 // Address size ) (input clk, input sel, - input we, - input [SIZE-1:0] adr, - input [63:0] dat_i, + input we, + input [SIZE-1:0] adr, + input [63:0] dat_i, output reg [63:0] dat_o); - + reg [63:0] mem [0:(1 << SIZE)-1]; integer i; @@ -19,7 +19,7 @@ module ram2 #( for (i = 0; i < (1<signed - + // Combine with unsigned offset assign result = sum_full + $signed({6'b0, unsigned_offset}); endmodule @@ -1218,17 +1218,17 @@ module top ( ); wire signed [5:0] extended_base; wire signed [6:0] offset_sum; - + // Conditional sign extension based on input - assign extended_base = extend_sign ? + assign extended_base = extend_sign ? {{1{base_val[4]}}, base_val} : // Sign extend {1'b0, base_val}; // Zero extend - + // Mix of signed and unsigned offsets - assign offset_sum = $signed({2'b0, pos_offset1}) + - $signed({2'b0, pos_offset2}) + + assign offset_sum = $signed({2'b0, pos_offset1}) + + $signed({2'b0, pos_offset2}) + {{2{signed_offset[3]}}, signed_offset}; - + assign result = extended_base + offset_sum; endmodule EOF diff --git a/tests/pass-fuzzing.md b/tests/pass-fuzzing.md index 993f36078..99bf51c08 100644 --- a/tests/pass-fuzzing.md +++ b/tests/pass-fuzzing.md @@ -53,7 +53,7 @@ index 9c361294d..c9a98f74c 100644 +++ b/Makefile @@ -238,7 +238,7 @@ LTOFLAGS := $(GCC_LTO) - + ifeq ($(CONFIG),clang) -CXX = clang++ +CXX = $(HOME)/AFLplusplus/afl-c++ @@ -76,7 +76,7 @@ Generate some initial testcases using Grammar-Mutator: (cd $HOME/Grammar-Mutator; rm -rf seeds trees; ./grammar_generator-rtlil 100 1000 ./seeds ./trees) ``` -Now run AFL++. +Now run AFL++. ``` (cd $HOME/Grammar-Mutator; \ AFL_CUSTOM_MUTATOR_LIBRARY=./libgrammarmutator-rtlil.so \ diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys index da0f3b620..b86822b30 100644 --- a/tests/sat/grom.ys +++ b/tests/sat/grom.ys @@ -1,5 +1,5 @@ read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v; -prep -top grom_computer; +prep -top grom_computer; sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80 sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp diff --git a/tests/sat/grom_cpu.v b/tests/sat/grom_cpu.v index 914c0f56c..0a29ffdb6 100644 --- a/tests/sat/grom_cpu.v +++ b/tests/sat/grom_cpu.v @@ -173,12 +173,12 @@ module grom_cpu( 3'b011 : begin RESULT_REG <= IR[1:0]; // result in REG - // CMP and TEST are not storing result + // CMP and TEST are not storing result state <= IR[3] ? STATE_FETCH_PREP : STATE_ALU_RESULT_WAIT; // CMP and TEST are having first input R0, for INC and DEC is REG - alu_a <= IR[3] ? R[0] : R[IR[1:0]]; + alu_a <= IR[3] ? R[0] : R[IR[1:0]]; // CMP and TEST are having second input REG, for INC and DEC is 1 - alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001; + alu_b <= IR[3] ? R[IR[1:0]] : 8'b00000001; case(IR[3:2]) 2'b00 : begin diff --git a/tests/sdc/alu_sub.sdc b/tests/sdc/alu_sub.sdc index f298d20bc..e50f572a5 100644 --- a/tests/sdc/alu_sub.sdc +++ b/tests/sdc/alu_sub.sdc @@ -7,7 +7,7 @@ current_design wrapper # Timing Constraints ############################################################################### create_clock -name this_clk -period 1.0000 [get_ports {clk}] -create_clock -name that_clk -period 2.0000 +create_clock -name that_clk -period 2.0000 create_clock -name another_clk -period 2.0000 \ [list [get_ports {A[0]}]\ [get_ports {A[1]}]\ diff --git a/tests/sim/generate_mk.py b/tests/sim/generate_mk.py index 57138762d..47b22971a 100644 --- a/tests/sim/generate_mk.py +++ b/tests/sim/generate_mk.py @@ -11,7 +11,7 @@ from pathlib import Path print("Generate FST for sim models") for name in Path("tb").rglob("tb*.v"): - test_name = name.stem + test_name = name.stem print(f"Test {test_name}") verilog_name = f"{test_name[3:]}.v" diff --git a/tests/sim/tb/tb_adff.v b/tests/sim/tb/tb_adff.v index f1bc3547e..e6a9294e2 100644 --- a/tests/sim/tb/tb_adff.v +++ b/tests/sim/tb/tb_adff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_adff(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_adffe.v b/tests/sim/tb/tb_adffe.v index bb23f963d..f1874e07d 100644 --- a/tests/sim/tb/tb_adffe.v +++ b/tests/sim/tb/tb_adffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_adffe(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_adlatch.v b/tests/sim/tb/tb_adlatch.v index 59dd498d2..a98d3ff52 100644 --- a/tests/sim/tb/tb_adlatch.v +++ b/tests/sim/tb/tb_adlatch.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_adlatch(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_aldff.v b/tests/sim/tb/tb_aldff.v index 0591c8b3c..f8bc6521e 100644 --- a/tests/sim/tb/tb_aldff.v +++ b/tests/sim/tb/tb_aldff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_aldff(); reg clk = 0; reg aload = 0; diff --git a/tests/sim/tb/tb_aldffe.v b/tests/sim/tb/tb_aldffe.v index c3cb57f4e..d3caa4e4f 100644 --- a/tests/sim/tb/tb_aldffe.v +++ b/tests/sim/tb/tb_aldffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_aldffe(); reg clk = 0; reg aload = 0; diff --git a/tests/sim/tb/tb_dff.v b/tests/sim/tb/tb_dff.v index aa41d1c6c..129b1da38 100644 --- a/tests/sim/tb/tb_dff.v +++ b/tests/sim/tb/tb_dff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dff(); reg clk = 0; reg d = 0; diff --git a/tests/sim/tb/tb_dffe.v b/tests/sim/tb/tb_dffe.v index 4e262b928..8357cdf8b 100644 --- a/tests/sim/tb/tb_dffe.v +++ b/tests/sim/tb/tb_dffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dffe(); reg clk = 0; reg en = 0; diff --git a/tests/sim/tb/tb_dffsr.v b/tests/sim/tb/tb_dffsr.v index 6ecb85d67..0199a894a 100644 --- a/tests/sim/tb/tb_dffsr.v +++ b/tests/sim/tb/tb_dffsr.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dffsr(); reg clk = 0; reg d = 0; diff --git a/tests/sim/tb/tb_dlatch.v b/tests/sim/tb/tb_dlatch.v index aea6cb0a3..ebb4ca36a 100644 --- a/tests/sim/tb/tb_dlatch.v +++ b/tests/sim/tb/tb_dlatch.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dlatch(); reg clk = 0; reg en = 0; diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v index 0105d3288..b48b09b60 100644 --- a/tests/sim/tb/tb_dlatchsr.v +++ b/tests/sim/tb/tb_dlatchsr.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_dlatchsr(); reg d = 0; reg set = 0; diff --git a/tests/sim/tb/tb_sdff.v b/tests/sim/tb/tb_sdff.v index f8e2a1c9d..de668b362 100644 --- a/tests/sim/tb/tb_sdff.v +++ b/tests/sim/tb/tb_sdff.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_sdff(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_sdffce.v b/tests/sim/tb/tb_sdffce.v index 1c9952806..8bfd35d94 100644 --- a/tests/sim/tb/tb_sdffce.v +++ b/tests/sim/tb/tb_sdffce.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_sdffce(); reg clk = 0; reg rst = 0; diff --git a/tests/sim/tb/tb_sdffe.v b/tests/sim/tb/tb_sdffe.v index 36072f93d..869028c2b 100644 --- a/tests/sim/tb/tb_sdffe.v +++ b/tests/sim/tb/tb_sdffe.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ns +`timescale 1ns/1ns module tb_sdffe(); reg clk = 0; reg rst = 0; diff --git a/tests/svtypes/struct_simple.sv b/tests/svtypes/struct_simple.sv index c74289cc3..c9a833549 100644 --- a/tests/svtypes/struct_simple.sv +++ b/tests/svtypes/struct_simple.sv @@ -8,7 +8,7 @@ module top; logic x, y; } s; - struct packed signed { + struct packed signed { integer a; logic[15:0] b; logic[7:0] c; diff --git a/tests/techmap/dfflibmap_dffn_dffe.lib b/tests/techmap/dfflibmap_dffn_dffe.lib index 832edee67..2d79373a2 100644 --- a/tests/techmap/dfflibmap_dffn_dffe.lib +++ b/tests/techmap/dfflibmap_dffn_dffe.lib @@ -4,7 +4,7 @@ library(test) { ff("IQ", "IQN") { next_state : "D"; clocked_on : "!CLK"; - } + } pin(D) { direction : input; } @@ -18,7 +18,7 @@ library(test) { pin(QN) { direction: output; function : "IQN"; - } + } } cell (dffe) { area : 6; diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys index 542223030..f91ba1dee 100644 --- a/tests/various/bug1531.ys +++ b/tests/various/bug1531.ys @@ -6,7 +6,7 @@ module top (y, clk, w); always @(posedge clk) // If the constant below is set to 2'b00, the correct output is generated. // vvvv - for (i = 1'b0; i < 2'b01; i = i + 2'b01) + for (i = 1'b0; i < 2'b01; i = i + 2'b01) y <= w || i[1:1]; endmodule EOT diff --git a/tests/various/bug1745.ys b/tests/various/bug1745.ys index 2e5b8c2d4..b2aa610f1 100644 --- a/tests/various/bug1745.ys +++ b/tests/various/bug1745.ys @@ -3,6 +3,6 @@ read_verilog < Date: Tue, 23 Jun 2026 07:26:12 +0200 Subject: [PATCH 050/101] Remaining fix --- docs/source/code_examples/macro_commands/synth_ice40.ys | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index fbdd763fc..fab96707f 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -88,4 +88,3 @@ check: stat check -noinit blackbox =A:whitebox - From 43d8a84bdc1a3fa71f077d8ef31d39254158bc43 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 23 Jun 2026 07:30:54 +0200 Subject: [PATCH 051/101] Add pre-commit config file --- .pre-commit-config.yaml | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 .pre-commit-config.yaml diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml new file mode 100644 index 000000000..9aab6c2a8 --- /dev/null +++ b/.pre-commit-config.yaml @@ -0,0 +1,30 @@ +# To use: +# +# pre-commit run -a +# +# Or: +# +# pre-commit install # (runs every time you commit in git) +# +# To update this file: +# +# pre-commit autoupdate +# +# See https://github.com/pre-commit/pre-commit + +exclude: ^libs/ + +repos: +- repo: https://github.com/pre-commit/pre-commit-hooks + rev: v6.0.0 + hooks: + - id: check-case-conflict + - id: check-executables-have-shebangs + - id: check-illegal-windows-names + - id: check-yaml + args: [--allow-multiple-documents] + - id: end-of-file-fixer + - id: fix-byte-order-marker + - id: mixed-line-ending + args: [--fix,lf] + - id: trailing-whitespace From fd3ec580551e60f160175e60bab2dbcc5b456475 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 24 Jun 2026 07:49:42 +0200 Subject: [PATCH 052/101] Remove leftover use of log_id --- passes/cmds/check.cc | 8 ++++---- passes/sat/sim.cc | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index d219f8da3..c7b97544f 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -502,12 +502,12 @@ struct CheckMemPass : public Pass { for (auto &init : mem.inits) { int start = init.addr.as_int(); if (start < min_addr) { - log_warning("Mem %s.%s starts at %d but initializes address %d.\n", log_id(module), log_id(mem.mem), min_addr, start); + log_warning("Mem %s.%s starts at %d but initializes address %d.\n", module, mem.mem, min_addr, start); counter++; } int end = start + (GetSize(init.data) / mem.width) - 1; if (end > max_addr) { - log_warning("Mem %s.%s ends at %d but initializes address %d.\n", log_id(module), log_id(mem.mem), max_addr, end); + log_warning("Mem %s.%s ends at %d but initializes address %d.\n", module, mem.mem, max_addr, end); counter++; } } @@ -516,7 +516,7 @@ struct CheckMemPass : public Pass { if (addr_sig.is_fully_const()) { auto addr = addr_sig.as_int(); if (addr < min_addr || addr > max_addr) { - log_warning("Mem %s.%s contains entries for addresses %d..%d but %s address %d.\n", log_id(module), log_id(mem.mem), min_addr, max_addr, access, addr); + log_warning("Mem %s.%s contains entries for addresses %d..%d but %s address %d.\n", module, mem.mem, min_addr, max_addr, access, addr); counter++; } } else if (nonconst_mode) { @@ -525,7 +525,7 @@ struct CheckMemPass : public Pass { int addr_sig_min = 0; int addr_sig_max = (1 << addr_sig.size()) - 1; if (min_addr > addr_sig_min || max_addr < addr_sig_max) { - log_warning("Mem %s.%s contains entries for addresses %d..%d but has a potentially dangerous non-const input %s\n", log_id(module), log_id(mem.mem), min_addr, max_addr, log_signal(addr_sig)); + log_warning("Mem %s.%s contains entries for addresses %d..%d but has a potentially dangerous non-const input %s\n", module, mem.mem, min_addr, max_addr, log_signal(addr_sig)); counter++; } } diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index bbddb2c16..973dafd28 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -1326,7 +1326,7 @@ struct SimInstance if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X for(int i=0;isim_mode == SimulationMode::gold && !sim_val.is_fully_def()) { // sim data contains X for(int i=0;i Date: Thu, 25 Jun 2026 11:14:46 +0200 Subject: [PATCH 053/101] Tighten sig2bits. --- kernel/bitpattern.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index e2071436c..76c008b89 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -102,11 +102,19 @@ struct BitPatternPool bits_t bits; bits.bitdata = sig.as_const().to_bits(); for (auto &b : bits.bitdata) - if (b > RTLIL::State::S1) + if (b > RTLIL::State::S1 && b != RTLIL::State::Sx && b != RTLIL::State::Sz) b = RTLIL::State::Sa; return bits; } + static bool covers_nothing(const bits_t &bits) + { + for (auto &b : bits.bitdata) + if (b == RTLIL::State::Sx || b == RTLIL::State::Sz) + return true; + return false; + } + /** * Two cubes match if their intersection is non-empty. */ @@ -132,6 +140,8 @@ struct BitPatternPool bool has_any(RTLIL::SigSpec sig) { bits_t bits = sig2bits(sig); + if (covers_nothing(bits)) + return false; for (auto &it : database) if (match(it, bits)) return true; @@ -150,6 +160,8 @@ struct BitPatternPool bool has_all(RTLIL::SigSpec sig) { bits_t bits = sig2bits(sig); + if (covers_nothing(bits)) + return true; for (auto &it : database) if (match(it, bits)) { for (int i = 0; i < width; i++) @@ -171,6 +183,8 @@ struct BitPatternPool { bool status = false; bits_t bits = sig2bits(sig); + if (covers_nothing(bits)) + return false; for (auto it = database.begin(); it != database.end();) if (match(*it, bits)) { for (int i = 0; i < width; i++) { From 6a45e7b29086f9c285f17a1248fa4ee5e410c953 Mon Sep 17 00:00:00 2001 From: nella Date: Thu, 25 Jun 2026 11:14:54 +0200 Subject: [PATCH 054/101] Add tests. --- tests/proc/rmdead_case_x.ys | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 tests/proc/rmdead_case_x.ys diff --git a/tests/proc/rmdead_case_x.ys b/tests/proc/rmdead_case_x.ys new file mode 100644 index 000000000..6a44ec462 --- /dev/null +++ b/tests/proc/rmdead_case_x.ys @@ -0,0 +1,40 @@ +# https://github.com/YosysHQ/yosys/issues/5979 + +read_verilog -sv << EOF +module top ( + input wire [1:0] sel, + input wire [3:0] a, + input wire [3:0] b, + output reg [3:0] y +); + always @* begin + case (sel) + 2'b1x: y = a; + 2'b10: y = b; + default: y = a; + endcase + end +endmodule + +module gold ( + input wire [1:0] sel, + input wire [3:0] a, + input wire [3:0] b, + output reg [3:0] y +); + always @* begin + if (sel == 2'b10) y = b; + else y = a; + end +endmodule +EOF + +proc +opt -full + +select -assert-count 1 top/o:y %ci* top/i:b %i + +equiv_make gold top equiv +cd equiv +equiv_simple +equiv_status -assert From 2bc5aa5cf4346ca478a547bf90c752399a73a7a7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 25 Jun 2026 14:20:27 +0200 Subject: [PATCH 055/101] Update ABC as per 2026-06-25 --- abc | 2 +- cmake/YosysAbc.cmake | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/abc b/abc index 30c47da5c..a35f806b8 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit 30c47da5c9343713ef0b3e12914686ffd28ef367 +Subproject commit a35f806b8ce47d29537cab973679b5a3523ab085 diff --git a/cmake/YosysAbc.cmake b/cmake/YosysAbc.cmake index 0632a9b17..696752e76 100644 --- a/cmake/YosysAbc.cmake +++ b/cmake/YosysAbc.cmake @@ -60,6 +60,7 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) $<$>:ABC_NAMESPACE=abc> ABC_USE_STDINT_H=1 ABC_USE_CUDD=1 + ABC_NO_HISTORY=1 ABC_NO_DYNAMIC_LINKING $<${YOSYS_ENABLE_THREADS}:ABC_USE_PTHREADS> $<${YOSYS_ENABLE_READLINE}:ABC_USE_READLINE> @@ -83,6 +84,7 @@ function(yosys_abc_target arg_LIBNAME arg_EXENAME) -Wno-deprecated-comma-subscript -Wno-format -Wno-constant-logical-operand + -Wno-sizeof-pointer-memaccess ) target_link_libraries(${arg_LIBNAME} PUBLIC $<${YOSYS_ENABLE_THREADS}:Threads::Threads> From 06a64af1f4c539d99e06b391279b5849856311ce Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 07:56:30 +0200 Subject: [PATCH 056/101] Set CodeQL to be executed weekly --- .github/workflows/codeql.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index dcdfc03cb..e020b459a 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -3,7 +3,7 @@ name: "CodeQL" on: workflow_dispatch: schedule: - - cron: '0 3 * * *' + - cron: '0 3 * * 6' jobs: analyze: From 63dd0e1a604fb1949610546dc3aace3d19101912 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 08:02:58 +0200 Subject: [PATCH 057/101] Add ccache --- .github/workflows/extra-builds.yml | 33 +++++++++++++++++++-------- .github/workflows/test-build.yml | 7 +++++- .github/workflows/test-compile.yml | 9 ++++++-- .github/workflows/test-sanitizers.yml | 8 ++++++- 4 files changed, 44 insertions(+), 13 deletions(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 603d91e5d..788e12c29 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -45,6 +45,11 @@ jobs: - name: Setup MSVC uses: ilammy/msvc-dev-cmd@v1 + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.23 + with: + key: vs-build + - name: Install flex/bison shell: pwsh run: | @@ -57,8 +62,9 @@ jobs: - name: Configure CMake run: > cmake -S . -B build - -A x64 + -G Ninja -DCMAKE_BUILD_TYPE=Release + -DYOSYS_COMPILER_LAUNCHER=ccache - name: Build run: > @@ -85,6 +91,11 @@ jobs: install: >- base-devel + bison + flex + gawk + diffutils + make mingw-w64-x86_64-toolchain mingw-w64-x86_64-cmake mingw-w64-x86_64-gtest @@ -93,13 +104,12 @@ jobs: mingw-w64-x86_64-tcl mingw-w64-x86_64-libffi mingw-w64-x86_64-git + mingw-w64-x86_64-ccache - msys2-install: >- - bison - flex - gawk - diffutils - make + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.23 + with: + key: mingw-build - name: Build Yosys shell: msys2 {0} @@ -107,7 +117,7 @@ jobs: set -e procs=$(nproc) rm -rf build - cmake -S . -B build -DCMAKE_BUILD_TYPE=Release + cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache cmake --build build -j${procs} ctest --test-dir build/tests/unit --output-on-failure @@ -121,6 +131,11 @@ jobs: with: submodules: true persist-credentials: false + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.23 + with: + key: wasi-build + - name: Build run: | WASI_VER=33 @@ -140,7 +155,7 @@ jobs: make install) export PATH=${WASI_SDK_PATH}/bin:$(pwd)/flex-prefix/bin:${PATH} - cmake -B build -DCMAKE_TOOLCHAIN_FILE=${WASI_SDK_PATH}/share/cmake/wasi-sdk-p1.cmake -DCMAKE_BUILD_TYPE=Release . + cmake -B build -DCMAKE_TOOLCHAIN_FILE=${WASI_SDK_PATH}/share/cmake/wasi-sdk-p1.cmake -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache . cmake --build build -j$(nproc) nix-build: diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index e09fd9eb3..6edf4fb25 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -79,11 +79,16 @@ jobs: runs-on: ${{ matrix.os }} get-build-deps: true + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.23 + with: + key: test-build-${{ matrix.os }} + - name: Build shell: bash run: | rm -rf build - cmake -B build . -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=Release + cmake -B build . -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache cmake --build build -j$procs ctest --test-dir build/tests/unit diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 3093e8dfd..87798c3a1 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -69,6 +69,11 @@ jobs: runs-on: ${{ matrix.os }} get-build-deps: true + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.23 + with: + key: test-compile-${{ matrix.os }}-${{ matrix.compiler }} + - name: Setup Cpp uses: aminya/setup-cpp@v1 with: @@ -91,7 +96,7 @@ jobs: shell: bash run: | rm -rf build - cmake -B build -DCMAKE_CXX_STANDARD=20 . --fresh + cmake -B build -DCMAKE_CXX_STANDARD=20 -DYOSYS_COMPILER_LAUNCHER=ccache . --fresh cmake --build build --target yosys -j$procs # maximum standard, only on newest compilers @@ -100,7 +105,7 @@ jobs: shell: bash run: | rm -rf build - cmake -B build -DCMAKE_CXX_STANDARD=26 . --fresh + cmake -B build -DCMAKE_CXX_STANDARD=26 -DYOSYS_COMPILER_LAUNCHER=ccache . --fresh cmake --build build --target yosys -j$procs test-compile-result: diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index d6c77fcf1..94ef62f04 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -60,13 +60,19 @@ jobs: get-test-deps: true get-iverilog: true + - name: ccache + uses: hendrikmuhs/ccache-action@v1.2.23 + with: + key: test-san-${{ matrix.os }} + - name: Build shell: bash run: | rm -rf build cmake -B build . \ -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ \ - -DCMAKE_BUILD_TYPE=Sanitize -DSANITIZE=${{ matrix.sanitizer }} + -DCMAKE_BUILD_TYPE=Sanitize -DSANITIZE=${{ matrix.sanitizer }} \ + -DYOSYS_COMPILER_LAUNCHER=ccache cmake --build build -j$procs - name: Log yosys-config output From 3f4fa079f83a05169af4e04ed5d5ceaef0da769b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 08:06:44 +0200 Subject: [PATCH 058/101] Upgrade base github actions --- .github/workflows/codeql.yml | 2 +- .github/workflows/extra-builds.yml | 8 ++++---- .github/workflows/prepare-docs.yml | 4 ++-- .github/workflows/source-vendor.yml | 2 +- .github/workflows/test-build.yml | 12 ++++++------ .github/workflows/test-compile.yml | 2 +- .github/workflows/test-sanitizers.yml | 2 +- .github/workflows/test-verific-cfg.yml | 2 +- .github/workflows/test-verific.yml | 6 +++--- .github/workflows/wheels.yml | 2 +- 10 files changed, 21 insertions(+), 21 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index e020b459a..708f6e4ac 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -11,7 +11,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout repository - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: submodules: true persist-credentials: false diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 788e12c29..2e2dafa21 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -37,7 +37,7 @@ jobs: needs: [pre_job] if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v7 with: submodules: true persist-credentials: false @@ -78,7 +78,7 @@ jobs: needs: [pre_job] if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v7 with: submodules: true persist-credentials: false @@ -127,7 +127,7 @@ jobs: if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' runs-on: ubuntu-latest steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v7 with: submodules: true persist-credentials: false @@ -168,7 +168,7 @@ jobs: os: [ubuntu-latest, macos-latest] fail-fast: false steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v7 with: submodules: true persist-credentials: false diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index ff2b96872..7e0237f35 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -46,7 +46,7 @@ jobs: runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys - uses: actions/checkout@v4 + uses: actions/checkout@v7 with: persist-credentials: false submodules: true @@ -72,7 +72,7 @@ jobs: cmake --build build --target docs-prepare -j$procs - name: Upload artifact - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@v7 with: name: cmd-ref-${{ github.sha }} path: | diff --git a/.github/workflows/source-vendor.yml b/.github/workflows/source-vendor.yml index d85b2af08..b64306c29 100644 --- a/.github/workflows/source-vendor.yml +++ b/.github/workflows/source-vendor.yml @@ -12,7 +12,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Checkout repository with submodules - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: submodules: 'recursive' persist-credentials: false diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 6edf4fb25..c1ce56008 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -68,7 +68,7 @@ jobs: fail-fast: false steps: - name: Checkout Yosys - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: submodules: true persist-credentials: false @@ -122,7 +122,7 @@ jobs: fail-fast: false steps: - name: Checkout Yosys - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: persist-credentials: false @@ -171,7 +171,7 @@ jobs: os: [ubuntu-latest] steps: - name: Checkout Yosys - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: persist-credentials: false @@ -209,7 +209,7 @@ jobs: fail-fast: false steps: - name: Checkout Yosys - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: persist-credentials: false @@ -251,7 +251,7 @@ jobs: fail-fast: false steps: - name: Checkout Yosys - uses: actions/checkout@v4 + uses: actions/checkout@v7 with: submodules: true persist-credentials: false @@ -281,7 +281,7 @@ jobs: cmake --build build --target docs-${{ matrix.docs-target }} -j$procs - name: Store docs build artifact - uses: actions/upload-artifact@v4 + uses: actions/upload-artifact@v7 with: name: docs-build-${{ matrix.docs-target }} path: docs/build/ diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 87798c3a1..77a85ac6e 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -58,7 +58,7 @@ jobs: fail-fast: false steps: - name: Checkout Yosys - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: submodules: true persist-credentials: false diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 94ef62f04..4575c961e 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -47,7 +47,7 @@ jobs: fail-fast: false steps: - name: Checkout Yosys - uses: actions/checkout@v5 + uses: actions/checkout@v7 with: submodules: true persist-credentials: false diff --git a/.github/workflows/test-verific-cfg.yml b/.github/workflows/test-verific-cfg.yml index 6721c0c9b..733eb2989 100644 --- a/.github/workflows/test-verific-cfg.yml +++ b/.github/workflows/test-verific-cfg.yml @@ -9,7 +9,7 @@ jobs: runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys - uses: actions/checkout@v4 + uses: actions/checkout@v7 with: persist-credentials: false submodules: true diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 9143c2f19..28bcb2d3a 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -37,7 +37,7 @@ jobs: runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys - uses: actions/checkout@v4 + uses: actions/checkout@v7 with: persist-credentials: false submodules: true @@ -70,7 +70,7 @@ jobs: cmake --build build --target install - name: Checkout SBY - uses: actions/checkout@v4 + uses: actions/checkout@v7 with: repository: 'YosysHQ/sby' path: 'sby' @@ -125,7 +125,7 @@ jobs: runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys - uses: actions/checkout@v4 + uses: actions/checkout@v7 with: persist-credentials: false submodules: true diff --git a/.github/workflows/wheels.yml b/.github/workflows/wheels.yml index e6381a637..043c9a664 100644 --- a/.github/workflows/wheels.yml +++ b/.github/workflows/wheels.yml @@ -47,7 +47,7 @@ jobs: name: Build Wheels | ${{ matrix.os.name }} | ${{ matrix.os.archs }} runs-on: ${{ matrix.os.runner }} steps: - - uses: actions/checkout@v5 + - uses: actions/checkout@v7 with: fetch-depth: 0 submodules: true From b8459c9deca01d0f60206b846b8d115eda351d6d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 08:08:22 +0200 Subject: [PATCH 059/101] Use forked skip-duplicate-actions --- .github/workflows/extra-builds.yml | 2 +- .github/workflows/prepare-docs.yml | 2 +- .github/workflows/test-build.yml | 4 ++-- .github/workflows/test-compile.yml | 2 +- .github/workflows/test-sanitizers.yml | 2 +- .github/workflows/test-verific.yml | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 2e2dafa21..83ffd5e02 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -15,7 +15,7 @@ jobs: steps: - id: skip_check if: ${{ github.event_name != 'merge_group' }} - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml index 7e0237f35..32f4619f7 100644 --- a/.github/workflows/prepare-docs.yml +++ b/.github/workflows/prepare-docs.yml @@ -18,7 +18,7 @@ jobs: docs_export: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }} steps: - id: skip_check - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: paths_ignore: '["**/README.md"]' # don't cancel in case we're updating docs diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index c1ce56008..807873fbf 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -15,7 +15,7 @@ jobs: steps: - id: skip_check if: ${{ github.event_name != 'merge_group' }} - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' @@ -38,7 +38,7 @@ jobs: steps: - id: skip_check if: ${{ github.event_name != 'merge_group' }} - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: # don't run on readme changes paths_ignore: '["**/README.md"]' diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 77a85ac6e..5d14e666e 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -15,7 +15,7 @@ jobs: steps: - id: skip_check if: ${{ github.event_name != 'merge_group' }} - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 4575c961e..7cb6cf33f 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -15,7 +15,7 @@ jobs: steps: - id: skip_check if: ${{ github.event_name != 'merge_group' }} - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index 28bcb2d3a..f268f4b65 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -15,7 +15,7 @@ jobs: steps: - id: skip_check if: ${{ github.event_name != 'merge_group' }} - uses: fkirc/skip-duplicate-actions@v5 + uses: mmicko/skip-duplicate-actions@master with: # don't run on documentation changes paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]' From f1820e44231a7267f0c91e1aa250cca91107b9ae Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 08:08:53 +0200 Subject: [PATCH 060/101] Use updated msvc-dev-cmd action --- .github/workflows/extra-builds.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 83ffd5e02..9d39089f1 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -43,7 +43,9 @@ jobs: persist-credentials: false - name: Setup MSVC - uses: ilammy/msvc-dev-cmd@v1 + uses: TheMrMilchmann/setup-msvc-dev@v4 + with: + arch: x64 - name: ccache uses: hendrikmuhs/ccache-action@v1.2.23 From 53138724dbb472b1ced05eedaecf3d3eb58fec2d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 08:09:10 +0200 Subject: [PATCH 061/101] Remove intel macOS compiler --- .github/workflows/test-compile.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 5d14e666e..808f2a962 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -49,9 +49,6 @@ jobs: - 'clang-22' - 'gcc-16' include: - # macOS x86 - - os: macos-15-intel - compiler: 'clang-22' # macOS arm - os: macos-latest compiler: 'clang-22' From 18902ddd3423de0e85769cdf543f6eac7debb634 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 08:11:16 +0200 Subject: [PATCH 062/101] Fix formatting --- .github/workflows/extra-builds.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 9d39089f1..7963a411d 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -133,6 +133,7 @@ jobs: with: submodules: true persist-credentials: false + - name: ccache uses: hendrikmuhs/ccache-action@v1.2.23 with: From bd1cb398e4ccaf19cada48c9ad7da021af569fe6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 10:11:15 +0200 Subject: [PATCH 063/101] Update iverilog and build-env --- .github/actions/setup-build-env/action.yml | 8 ++++---- .github/actions/setup-iverilog/action.yml | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index c1d3e2b01..b61bb95ac 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -33,21 +33,21 @@ runs: # and docs/source/getting_started/installation.rst to match. - name: Linux common dependencies if: runner.os == 'Linux' - uses: awalsh128/cache-apt-pkgs-action@v1.6.0 + uses: awalsh128/cache-apt-pkgs-action@v1.6.1 with: packages: gawk git make python3 version: ${{ inputs.runs-on }}-commonys - name: Linux build dependencies if: runner.os == 'Linux' && inputs.get-build-deps == 'true' - uses: awalsh128/cache-apt-pkgs-action@v1.6.0 + uses: awalsh128/cache-apt-pkgs-action@v1.6.1 with: packages: bison clang flex libffi-dev libfl-dev libreadline-dev pkg-config tcl-dev zlib1g-dev libgtest-dev libgmock-dev version: ${{ inputs.runs-on }}-buildys - name: Linux docs dependencies if: runner.os == 'Linux' && inputs.get-docs-deps == 'true' - uses: awalsh128/cache-apt-pkgs-action@v1.6.0 + uses: awalsh128/cache-apt-pkgs-action@v1.6.1 with: packages: graphviz xdot version: ${{ inputs.runs-on }}-docsys @@ -70,7 +70,7 @@ runs: shell: bash run: | echo "${{ github.workspace }}/.local/bin" >> $GITHUB_PATH - echo "$(brew --prefix llvm@20)/bin" >> $GITHUB_PATH + echo "$(brew --prefix llvm)/bin" >> $GITHUB_PATH echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH echo "$(brew --prefix flex)/bin" >> $GITHUB_PATH echo "procs=$(sysctl -n hw.ncpu)" >> $GITHUB_ENV diff --git a/.github/actions/setup-iverilog/action.yml b/.github/actions/setup-iverilog/action.yml index 0acb582e3..3457303e2 100644 --- a/.github/actions/setup-iverilog/action.yml +++ b/.github/actions/setup-iverilog/action.yml @@ -11,7 +11,7 @@ runs: steps: - name: iverilog Linux deps if: steps.restore-iverilog.outputs.cache-hit != 'true' && runner.os == 'Linux' - uses: awalsh128/cache-apt-pkgs-action@v1.6.0 + uses: awalsh128/cache-apt-pkgs-action@v1.6.1 with: packages: autoconf gperf make gcc g++ bison flex libbz2-dev version: ${{ inputs.runs-on }}-iverilog @@ -40,7 +40,7 @@ runs: make -j$procs make install - - uses: actions/cache/restore@v4 + - uses: actions/cache/restore@v6 id: restore-iverilog with: path: .local/ @@ -62,7 +62,7 @@ runs: run: | iverilog -V - - uses: actions/cache/save@v4 + - uses: actions/cache/save@v6 id: save-iverilog if: steps.restore-iverilog.outputs.cache-hit != 'true' with: From cefe7266b1793b4cefc0c89ea8bc4d961adcfa9c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 10:55:28 +0200 Subject: [PATCH 064/101] Add restore keys --- .github/workflows/extra-builds.yml | 6 ++++++ .github/workflows/test-build.yml | 2 ++ .github/workflows/test-compile.yml | 2 ++ .github/workflows/test-sanitizers.yml | 2 ++ 4 files changed, 12 insertions(+) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 7963a411d..411fd9f55 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -51,6 +51,8 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: vs-build + restore-keys: | + vs-build- - name: Install flex/bison shell: pwsh @@ -112,6 +114,8 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: mingw-build + restore-keys: | + mingw-build- - name: Build Yosys shell: msys2 {0} @@ -138,6 +142,8 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: wasi-build + restore-keys: | + wasi-build- - name: Build run: | diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 807873fbf..0c8ac6b90 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -83,6 +83,8 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: test-build-${{ matrix.os }} + restore-keys: | + test-build-${{ matrix.os }}- - name: Build shell: bash diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 808f2a962..fafa82894 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -70,6 +70,8 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: test-compile-${{ matrix.os }}-${{ matrix.compiler }} + restore-keys: | + test-compile-${{ matrix.os }}-${{ matrix.compiler }}- - name: Setup Cpp uses: aminya/setup-cpp@v1 diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 7cb6cf33f..5439b16b4 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -64,6 +64,8 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: test-san-${{ matrix.os }} + restore-keys: | + test-san-${{ matrix.os }}- - name: Build shell: bash From 459a933005d4e276be76c78e8f480840be4a577b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 14:33:12 +0200 Subject: [PATCH 065/101] Store caches on main --- .github/workflows/extra-builds.yml | 15 ++++++++++----- .github/workflows/test-build.yml | 15 +++++++++------ .github/workflows/test-compile.yml | 9 ++++++--- .github/workflows/test-sanitizers.yml | 10 +++++++--- 4 files changed, 32 insertions(+), 17 deletions(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 411fd9f55..46615cd27 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -3,8 +3,8 @@ name: Test extra build flows on: pull_request: merge_group: - #push: - # branches: [ main ] + push: + branches: [ main ] workflow_dispatch: jobs: @@ -27,6 +27,8 @@ jobs: run: | if [ "${{ github.event_name }}" = "merge_group" ]; then echo "should_skip=false" >> $GITHUB_OUTPUT + elif [ "${{ github.event_name }}" = "push" ]; then + should_skip=false else echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT fi @@ -35,7 +37,7 @@ jobs: name: Visual Studio build runs-on: windows-latest needs: [pre_job] - if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' steps: - uses: actions/checkout@v7 with: @@ -51,6 +53,7 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: vs-build + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} restore-keys: | vs-build- @@ -80,7 +83,7 @@ jobs: name: MINGW64 build runs-on: windows-latest needs: [pre_job] - if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' steps: - uses: actions/checkout@v7 with: @@ -114,6 +117,7 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: mingw-build + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} restore-keys: | mingw-build- @@ -130,7 +134,7 @@ jobs: wasi-build: name: WASI build needs: pre_job - if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' runs-on: ubuntu-latest steps: - uses: actions/checkout@v7 @@ -142,6 +146,7 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: wasi-build + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} restore-keys: | wasi-build- diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 0c8ac6b90..860d69416 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -3,8 +3,8 @@ name: Build and run tests on: pull_request: merge_group: - #push: - # branches: [ main ] + push: + branches: [ main ] workflow_dispatch: jobs: @@ -50,6 +50,8 @@ jobs: run: | if [ "${{ github.event_name }}" = "merge_group" ]; then echo "should_skip=false" >> $GITHUB_OUTPUT + elif [ "${{ github.event_name }}" = "push" ]; then + should_skip=false else echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT fi @@ -83,6 +85,7 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: test-build-${{ matrix.os }} + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} restore-keys: | test-build-${{ matrix.os }}- @@ -115,7 +118,7 @@ jobs: name: Run tests runs-on: ${{ matrix.os }} needs: [build-yosys, pre_job] - if: needs.pre_job.outputs.should_skip != 'true' + if: github.event_name != 'push' && needs.pre_job.outputs.should_skip != 'true' env: CC: clang strategy: @@ -165,7 +168,7 @@ jobs: name: Run test_cell runs-on: ${{ matrix.os }} needs: [build-yosys, pre_job] - if: needs.pre_job.outputs.should_skip != 'true' + if: github.event_name != 'push' && needs.pre_job.outputs.should_skip != 'true' env: CC: clang strategy: @@ -204,7 +207,7 @@ jobs: name: Run docs tests runs-on: ${{ matrix.os }} needs: [build-yosys, pre_docs_job] - if: needs.pre_docs_job.outputs.should_skip != 'true' + if: github.event_name != 'push' && needs.pre_job.outputs.should_skip != 'true' strategy: matrix: os: [ubuntu-latest] @@ -246,7 +249,7 @@ jobs: name: Try build docs runs-on: [self-hosted, linux, x64, fast] needs: [pre_docs_job] - if: ${{ needs.pre_docs_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} + if: ${{ github.event_name != 'push' && needs.pre_docs_job.outputs.should_skip != 'true' && github.repository_owner == 'YosysHQ' }} strategy: matrix: docs-target: [html, latexpdf] diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index fafa82894..9bf31481f 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -3,8 +3,8 @@ name: Compiler testing on: pull_request: merge_group: - #push: - # branches: [ main ] + push: + branches: [ main ] workflow_dispatch: jobs: @@ -27,6 +27,8 @@ jobs: run: | if [ "${{ github.event_name }}" = "merge_group" ]; then echo "should_skip=false" >> $GITHUB_OUTPUT + elif [ "${{ github.event_name }}" = "push" ]; then + should_skip=false else echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT fi @@ -34,7 +36,7 @@ jobs: test-compile: runs-on: ${{ matrix.os }} needs: pre_job - if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' env: CXXFLAGS: ${{ startsWith(matrix.compiler, 'gcc') && '-Wp,-D_GLIBCXX_ASSERTIONS' || ''}} strategy: @@ -70,6 +72,7 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: test-compile-${{ matrix.os }}-${{ matrix.compiler }} + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} restore-keys: | test-compile-${{ matrix.os }}-${{ matrix.compiler }}- diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 5439b16b4..950e0c2e2 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -3,8 +3,8 @@ name: Check clang sanitizers on: pull_request: merge_group: - #push: - # branches: [ main ] + push: + branches: [ main ] workflow_dispatch: jobs: @@ -27,6 +27,8 @@ jobs: run: | if [ "${{ github.event_name }}" = "merge_group" ]; then echo "should_skip=false" >> $GITHUB_OUTPUT + elif [ "${{ github.event_name }}" = "push" ]; then + should_skip=false else echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT fi @@ -35,7 +37,7 @@ jobs: name: Build and run tests runs-on: ${{ matrix.os }} needs: pre_job - if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' env: CC: clang ASAN_OPTIONS: halt_on_error=1 detect_container_overflow=0 @@ -64,6 +66,7 @@ jobs: uses: hendrikmuhs/ccache-action@v1.2.23 with: key: test-san-${{ matrix.os }} + save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} restore-keys: | test-san-${{ matrix.os }}- @@ -82,6 +85,7 @@ jobs: ./build/yosys-config || true - name: Run tests + if: github.event_name != 'push' shell: bash run: | make -C tests -j$procs vanilla-test From 84248a008b1f09de63ee0d80f87115a638efbd85 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 18 Jun 2026 13:05:49 +0200 Subject: [PATCH 066/101] Bump minimal clang to 16 --- .github/workflows/test-compile.yml | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index 9bf31481f..b57b0df53 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -45,7 +45,7 @@ jobs: - ubuntu-latest compiler: # oldest supported - - 'clang-14' + - 'clang-16' - 'gcc-11' # newest, make sure to update maximum standard step to match - 'clang-22' @@ -80,7 +80,6 @@ jobs: uses: aminya/setup-cpp@v1 with: compiler: ${{ matrix.compiler }} - gcc: ${{ (matrix.os == 'ubuntu-latest' && matrix.compiler == 'clang-14') && '12' || '' }} - name: Tool versions shell: bash @@ -88,11 +87,6 @@ jobs: $CC --version $CXX --version - - name: Fix clang-14 toolchain - if: matrix.os == 'ubuntu-latest' && matrix.compiler == 'clang-14' - run: | - echo 'CXXFLAGS=--gcc-toolchain=/usr -isystem /usr/include/c++/12 -isystem /usr/include/x86_64-linux-gnu/c++/12' >> $GITHUB_ENV - # minimum standard - name: Build C++20 shell: bash From 8ad1b7f2b28dced7b729bb7b918e8898552bcfe2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 20 Jun 2026 17:15:10 +0200 Subject: [PATCH 067/101] Remove nix parameter --- .github/workflows/extra-builds.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 46615cd27..644529c9d 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -189,7 +189,7 @@ jobs: - uses: cachix/install-nix-action@v31 with: install_url: https://releases.nixos.org/nix/nix-2.30.0/install - - run: nix build .?submodules=1 -L + - run: nix build -L extra-builds-result: runs-on: ubuntu-latest From 0c132579159d2356dddc1f1e6ef14ac248a06cd1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 16:07:34 +0200 Subject: [PATCH 068/101] Sanitizer self hosted --- .github/workflows/test-sanitizers.yml | 39 +++++++-------------------- 1 file changed, 10 insertions(+), 29 deletions(-) diff --git a/.github/workflows/test-sanitizers.yml b/.github/workflows/test-sanitizers.yml index 950e0c2e2..d0509eb43 100644 --- a/.github/workflows/test-sanitizers.yml +++ b/.github/workflows/test-sanitizers.yml @@ -3,8 +3,8 @@ name: Check clang sanitizers on: pull_request: merge_group: - push: - branches: [ main ] + #push: + # branches: [ main ] workflow_dispatch: jobs: @@ -33,20 +33,14 @@ jobs: echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT fi - run_san: - name: Build and run tests - runs-on: ${{ matrix.os }} + test-sanitizers: + runs-on: [self-hosted, linux, x64, fast] needs: pre_job - if: (github.event_name == 'push' || github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' + if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' env: CC: clang ASAN_OPTIONS: halt_on_error=1 detect_container_overflow=0 UBSAN_OPTIONS: halt_on_error=1 - strategy: - matrix: - os: [ubuntu-latest, macos-latest] - sanitizer: ['undefined,address'] - fail-fast: false steps: - name: Checkout Yosys uses: actions/checkout@v7 @@ -54,21 +48,9 @@ jobs: submodules: true persist-credentials: false - - name: Setup environment - uses: ./.github/actions/setup-build-env - with: - runs-on: ${{ matrix.os }} - get-build-deps: true - get-test-deps: true - get-iverilog: true - - - name: ccache - uses: hendrikmuhs/ccache-action@v1.2.23 - with: - key: test-san-${{ matrix.os }} - save: ${{ github.event_name == 'push' && github.ref == 'refs/heads/main' }} - restore-keys: | - test-san-${{ matrix.os }}- + - name: Runtime environment + run: | + echo "procs=$(nproc)" >> $GITHUB_ENV - name: Build shell: bash @@ -76,7 +58,7 @@ jobs: rm -rf build cmake -B build . \ -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ \ - -DCMAKE_BUILD_TYPE=Sanitize -DSANITIZE=${{ matrix.sanitizer }} \ + -DCMAKE_BUILD_TYPE=Sanitize -DSANITIZE='undefined,address' \ -DYOSYS_COMPILER_LAUNCHER=ccache cmake --build build -j$procs @@ -85,7 +67,6 @@ jobs: ./build/yosys-config || true - name: Run tests - if: github.event_name != 'push' shell: bash run: | make -C tests -j$procs vanilla-test @@ -99,7 +80,7 @@ jobs: test-sanitizers-result: runs-on: ubuntu-latest needs: - - run_san + - test-sanitizers if: always() steps: - name: Check results From cd4198e024d933ffa980acf263d0141904b0983a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 17:17:35 +0200 Subject: [PATCH 069/101] Skip this step during merge queue since we have already run those --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 860d69416..8a71d39be 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -26,7 +26,7 @@ jobs: - id: set_output run: | if [ "${{ github.event_name }}" = "merge_group" ]; then - echo "should_skip=false" >> $GITHUB_OUTPUT + echo "should_skip=true" >> $GITHUB_OUTPUT else echo "should_skip=${{ steps.skip_check.outputs.should_skip }}" >> $GITHUB_OUTPUT fi From 049dca7ded732e45be01a8e7bd5ce9646f97451c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 18:02:37 +0200 Subject: [PATCH 070/101] Fix skipping test-build on merge --- .github/workflows/test-build.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/test-build.yml b/.github/workflows/test-build.yml index 8a71d39be..33205aa83 100644 --- a/.github/workflows/test-build.yml +++ b/.github/workflows/test-build.yml @@ -49,7 +49,7 @@ jobs: - id: set_output run: | if [ "${{ github.event_name }}" = "merge_group" ]; then - echo "should_skip=false" >> $GITHUB_OUTPUT + echo "should_skip=true" >> $GITHUB_OUTPUT elif [ "${{ github.event_name }}" = "push" ]; then should_skip=false else From 9144d2bd2fc91539de4390bcd79a18947ec2f178 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 19:35:44 +0200 Subject: [PATCH 071/101] Moving nix to weekly as non-critical --- .github/workflows/extra-builds.yml | 20 -------------------- .github/workflows/nix.yml | 24 ++++++++++++++++++++++++ 2 files changed, 24 insertions(+), 20 deletions(-) create mode 100644 .github/workflows/nix.yml diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index 644529c9d..d041794d7 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -172,32 +172,12 @@ jobs: cmake -B build -DCMAKE_TOOLCHAIN_FILE=${WASI_SDK_PATH}/share/cmake/wasi-sdk-p1.cmake -DCMAKE_BUILD_TYPE=Release -DYOSYS_COMPILER_LAUNCHER=ccache . cmake --build build -j$(nproc) - nix-build: - name: "Build nix flake" - needs: pre_job - if: (github.event_name == 'merge_group' || github.event_name == 'workflow_dispatch') && needs.pre_job.outputs.should_skip != 'true' - runs-on: ${{ matrix.os }} - strategy: - matrix: - os: [ubuntu-latest, macos-latest] - fail-fast: false - steps: - - uses: actions/checkout@v7 - with: - submodules: true - persist-credentials: false - - uses: cachix/install-nix-action@v31 - with: - install_url: https://releases.nixos.org/nix/nix-2.30.0/install - - run: nix build -L - extra-builds-result: runs-on: ubuntu-latest needs: - vs-build - mingw-build - wasi-build - - nix-build if: always() steps: - name: Check results diff --git a/.github/workflows/nix.yml b/.github/workflows/nix.yml new file mode 100644 index 000000000..120240bd6 --- /dev/null +++ b/.github/workflows/nix.yml @@ -0,0 +1,24 @@ +name: Test nix build + +on: + workflow_dispatch: + schedule: + - cron: '0 5 * * 6' + +jobs: + nix-build: + name: "Build nix flake" + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: [ubuntu-latest, macos-latest] + fail-fast: false + steps: + - uses: actions/checkout@v7 + with: + submodules: true + persist-credentials: false + - uses: cachix/install-nix-action@v31 + with: + install_url: https://releases.nixos.org/nix/nix-2.30.0/install + - run: nix build -L From 0c0d3f717c5be17ec479f2a095adadffd725bfab Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 26 Jun 2026 20:57:24 +0200 Subject: [PATCH 072/101] Install just some brew packages --- .github/actions/setup-build-env/action.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/actions/setup-build-env/action.yml b/.github/actions/setup-build-env/action.yml index b61bb95ac..6f631ff30 100644 --- a/.github/actions/setup-build-env/action.yml +++ b/.github/actions/setup-build-env/action.yml @@ -56,7 +56,7 @@ runs: if: runner.os == 'macOS' shell: bash run: | - brew bundle + brew install bison flex gawk libffi git pkg-config python3 bash googletest tcl-tk llvm - name: Linux runtime environment if: runner.os == 'Linux' From 97e2600e5c53a7928669dac0b04254cfe7b4ac4c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 29 Jun 2026 08:32:44 +0200 Subject: [PATCH 073/101] Removed rewrite leftovers from log --- kernel/log.cc | 6 ------ kernel/log.h | 13 ------------- 2 files changed, 19 deletions(-) diff --git a/kernel/log.cc b/kernel/log.cc index 2f5a6350b..2c3e45c2b 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -388,12 +388,6 @@ void log_formatted_file_error(std::string_view filename, int lineno, std::string log_error_with_prefix(prefix, str); } -void logv_file_error(const string &filename, int lineno, - const char *format, va_list ap) -{ - log_formatted_file_error(filename, lineno, vstringf(format, ap)); -} - void log_experimental(const std::string &str) { if (log_experimentals_ignored.count(str) == 0 && log_experimentals.count(str) == 0) { diff --git a/kernel/log.h b/kernel/log.h index d132ba1a0..37260319b 100644 --- a/kernel/log.h +++ b/kernel/log.h @@ -24,7 +24,6 @@ #include -#include #include #define YS_REGEX_COMPILE(param) std::regex(param, \ std::regex_constants::nosubs | \ @@ -44,20 +43,11 @@ # endif #endif -#if defined(_MSC_VER) -// At least this is not in MSVC++ 2013. -# define __PRETTY_FUNCTION__ __FUNCTION__ -#endif - // from libs/sha1/sha1.h class SHA1; YOSYS_NAMESPACE_BEGIN -#define S__LINE__sub2(x) #x -#define S__LINE__sub1(x) S__LINE__sub2(x) -#define S__LINE__ S__LINE__sub1(__LINE__) - // YS_DEBUGTRAP is a macro that is functionally equivalent to a breakpoint // if the platform provides such functionality, and does nothing otherwise. // If no debugger is attached, it starts a just-in-time debugger if available, @@ -120,9 +110,6 @@ extern int log_make_debug; extern int log_force_debug; extern int log_debug_suppressed; -[[deprecated]] -[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); - void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg)); extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int left_line, unsigned int left_col, unsigned int right_line, unsigned int right_col, const char *msg); From a1759e7ae7c7a54017d95d05581f1218ea333399 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 13:42:08 +0200 Subject: [PATCH 074/101] fabulous: remove unused `-edif` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0074a52af..f2b6090f1 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -48,10 +48,6 @@ struct SynthPass : public ScriptPass log(" write the design to the specified BLIF file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); - log(" -edif \n"); - log(" write the design to the specified EDIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); From 32bd3e54183b0bb3a9658d2df272bc0f47ad00db Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 13:42:57 +0200 Subject: [PATCH 075/101] fabulous: remove unused `-encfile` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 3 --- 1 file changed, 3 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index f2b6090f1..0abfd843e 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -69,9 +69,6 @@ struct SynthPass : public ScriptPass log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" times).\n"); log("\n"); - log(" -encfile \n"); - log(" passed to 'fsm_recode' via 'fsm'\n"); - log("\n"); log(" -nofsm\n"); log(" do not run FSM optimization\n"); log("\n"); From d671de97e9f9464481b9e89a9952cf38f6283d0d Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 13:59:01 +0200 Subject: [PATCH 076/101] fabulous: remove legacy `-vpr` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0abfd843e..b9efe5498 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -55,9 +55,6 @@ struct SynthPass : public ScriptPass log(" -lut \n"); log(" perform synthesis for a k-LUT architecture (default 4).\n"); log("\n"); - log(" -vpr\n"); - log(" perform synthesis for the FABulous VPR flow (using slightly different techmapping).\n"); - log("\n"); log(" -plib \n"); log(" use the specified Verilog file as a primitive library.\n"); log("\n"); @@ -118,7 +115,7 @@ struct SynthPass : public ScriptPass string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode; std::vector extra_plib, extra_map; - bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; + bool autotop, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; int lut; void clear_flags() override @@ -127,7 +124,6 @@ struct SynthPass : public ScriptPass plib.clear(); autotop = false; lut = 4; - forvpr = false; noalumacc = false; nofsm = false; noshare = false; @@ -170,10 +166,6 @@ struct SynthPass : public ScriptPass } continue; } - if (args[argidx] == "-vpr") { - forvpr = true; - continue; - } if (args[argidx] == "-auto-top") { autotop = true; continue; @@ -371,8 +363,7 @@ struct SynthPass : public ScriptPass } if (check_label("map_cells")) { - if (!forvpr) - run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut)); + run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut)); run("clean"); } if (check_label("check")) { From 54c37b395b37aaa7ba86bac60e928f7bc97eab3a Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:16:34 +0200 Subject: [PATCH 077/101] fabulous: fix argument check in `-lut` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index b9efe5498..17c3b86f5 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -170,7 +170,7 @@ struct SynthPass : public ScriptPass autotop = true; continue; } - if (args[argidx] == "-lut") { + if (args[argidx] == "-lut" && argidx+1 < args.size()) { lut = atoi(args[++argidx].c_str()); continue; } From 30640c71e2ca4f3a19af1ddd7773bd0b64828730 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:24:18 +0200 Subject: [PATCH 078/101] fabulous: fix argument check in `-carry` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 17c3b86f5..e22443d25 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -218,7 +218,7 @@ struct SynthPass : public ScriptPass complexdff = true; continue; } - if (args[argidx] == "-carry") { + if (args[argidx] == "-carry" && argidx+1 < args.size()) { carry_mode = args[++argidx]; if (carry_mode != "none" && carry_mode != "ha") log_cmd_error("Unsupported carry style: %s\n", carry_mode); From 6c82468031508540520f85e4bd8194162e4d253f Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:11:12 +0200 Subject: [PATCH 079/101] fabulous: add `-ff` option, remove legacy `-plib`/`-complex-dff` option The concept of 'COMPLEX_DFF' is deprecated. Instead, simply specify the supported flip-flops using `-ff ` and supply the mapping file. Signed-off-by: Leo Moser --- techlibs/fabulous/cells_map.v | 4 - techlibs/fabulous/ff_map.v | 9 - techlibs/fabulous/latches_map.v | 11 - techlibs/fabulous/prims.v | 487 ---------------------------- techlibs/fabulous/synth_fabulous.cc | 47 ++- 5 files changed, 20 insertions(+), 538 deletions(-) delete mode 100644 techlibs/fabulous/ff_map.v delete mode 100644 techlibs/fabulous/latches_map.v delete mode 100644 techlibs/fabulous/prims.v diff --git a/techlibs/fabulous/cells_map.v b/techlibs/fabulous/cells_map.v index e33e641a8..2329286f5 100644 --- a/techlibs/fabulous/cells_map.v +++ b/techlibs/fabulous/cells_map.v @@ -8,11 +8,9 @@ module \$lut (A, Y); generate if (WIDTH == 1) begin LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0])); - end else if (WIDTH == 2) begin LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1])); - end else if (WIDTH == 3) begin LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); @@ -30,5 +28,3 @@ module \$lut (A, Y); end endgenerate endmodule - -module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule diff --git a/techlibs/fabulous/ff_map.v b/techlibs/fabulous/ff_map.v deleted file mode 100644 index 0a03bd692..000000000 --- a/techlibs/fabulous/ff_map.v +++ /dev/null @@ -1,9 +0,0 @@ -module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule - -module \$_DFFE_PP_ (input D, C, E, output Q); LUTFF_E _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E)); endmodule - -module \$_SDFF_PP0_ (input D, C, R, output Q); LUTFF_SR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .R(R)); endmodule -module \$_SDFF_PP1_ (input D, C, R, output Q); LUTFF_SS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .S(R)); endmodule - -module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); LUTFF_ESR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .R(R)); endmodule -module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); LUTFF_ESS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .S(R)); endmodule diff --git a/techlibs/fabulous/latches_map.v b/techlibs/fabulous/latches_map.v deleted file mode 100644 index c28f88cf7..000000000 --- a/techlibs/fabulous/latches_map.v +++ /dev/null @@ -1,11 +0,0 @@ -module \$_DLATCH_N_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = !E ? D : Q; -endmodule - -module \$_DLATCH_P_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = E ? D : Q; -endmodule diff --git a/techlibs/fabulous/prims.v b/techlibs/fabulous/prims.v deleted file mode 100644 index d1c493080..000000000 --- a/techlibs/fabulous/prims.v +++ /dev/null @@ -1,487 +0,0 @@ -module LUT1(output O, input I0); - parameter [1:0] INIT = 0; - assign O = I0 ? INIT[1] : INIT[0]; -endmodule - -module LUT2(output O, input I0, I1); - parameter [3:0] INIT = 0; - wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -module LUT3(output O, input I0, I1, I2); - parameter [7:0] INIT = 0; - wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -module LUT4(output O, input I0, I1, I2, I3); - parameter [15:0] INIT = 0; - wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci); - parameter [15:0] INIT = 0; - parameter I0MUX = 1'b1; - - wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - - wire I0_sel = I0MUX ? Ci : I0; - assign O = I0_sel ? s1[1] : s1[0]; - - assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2); -endmodule - -module LUT5(output O, input I0, I1, I2, I3, I4); - parameter [31:0] INIT = 0; - wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -module LUT6(output O, input I0, I1, I2, I3, I4, I5); - parameter [63:0] INIT = 0; - wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; - wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci); - parameter [63:0] INIT = 0; - - wire comb1, comb2; - - LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1)); - LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2)); - - assign O = comb1 ^ Ci; - assign Co = comb1 ? Ci : comb2; -endmodule - - -module LUTFF(input CLK, D, output reg O); - initial O = 1'b0; - always @ (posedge CLK) begin - O <= D; - end -endmodule - -module FABULOUS_MUX2(input I0, I1, S0, output O); - assign O = S0 ? I1 : I0; -endmodule - -module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O); - wire A0 = S0 ? I1 : I0; - wire A1 = S0 ? I3 : I2; - assign O = S1 ? A1 : A0; -endmodule - -module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O); - wire A0 = S0 ? I1 : I0; - wire A1 = S0 ? I3 : I2; - wire A2 = S0 ? I5 : I4; - wire A3 = S0 ? I7 : I6; - wire B0 = S1 ? A1 : A0; - wire B1 = S1 ? A3 : A2; - assign O = S2 ? B1 : B0; -endmodule - -module FABULOUS_LC #( - parameter K = 4, - parameter [2**K-1:0] INIT = 0, - parameter DFF_ENABLE = 1'b0 -) ( - input CLK, - input [K-1:0] I, - output O, - output Q -); - wire f_wire; - - //LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); - generate - if (K == 1) begin - LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0])); - end else - if (K == 2) begin - LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1])); - end else - if (K == 3) begin - LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2])); - end else - if (K == 4) begin - LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3])); - end - endgenerate - - LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); - - assign O = f_wire; -endmodule - -(* blackbox *) -module Global_Clock (output CLK); -`ifndef SYNTHESIS - initial CLK = 0; - always #10 CLK = ~CLK; -`endif -endmodule - -(* blackbox, keep *) -module InPass4_frame_config (input CLK, output O0, O1, O2, O3); - -endmodule - - -(* blackbox, keep *) -module OutPass4_frame_config (input CLK, I0, I1, I2, I3); - -endmodule - -(* blackbox, keep *) -module InPass4_frame_config_mux #( - parameter [3:0] O_reg = 0 -) ( - input CLK, - output O0, - output O1, - output O2, - output O3 -); -endmodule - -(* blackbox, keep *) -module OutPass4_frame_config_mux #( - parameter [3:0] I_reg = 0 -) ( - input I0, - input I1, - input I2, - input I3, - input CLK -); -endmodule - -(* keep *) -module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD); - assign PAD = T ? 1'bz : I; - assign O = PAD; - reg Q_q; - always @(posedge CLK) Q_q <= O; - assign Q = Q_q; -endmodule - - -module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK); - parameter A_reg = 1'b0; - parameter B_reg = 1'b0; - parameter C_reg = 1'b0; - parameter ACC = 1'b0; - parameter signExtension = 1'b0; - parameter ACCout = 1'b0; - - //parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value) - // IMPORTANT: this has to be in a dedicated line - input A7;// operand A - input A6; - input A5; - input A4; - input A3; - input A2; - input A1; - input A0; - input B7;// operand B - input B6; - input B5; - input B4; - input B3; - input B2; - input B1; - input B0; - input C19;// operand C - input C18; - input C17; - input C16; - input C15; - input C14; - input C13; - input C12; - input C11; - input C10; - input C9; - input C8; - input C7; - input C6; - input C5; - input C4; - input C3; - input C2; - input C1; - input C0; - output Q19;// result - output Q18; - output Q17; - output Q16; - output Q15; - output Q14; - output Q13; - output Q12; - output Q11; - output Q10; - output Q9; - output Q8; - output Q7; - output Q6; - output Q5; - output Q4; - output Q3; - output Q2; - output Q1; - output Q0; - - input clr; - input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) - // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label - - - wire [7:0] A; // port A read data - wire [7:0] B; // port B read data - wire [19:0] C; // port B read data - reg [7:0] A_q; // port A read data register - reg [7:0] B_q; // port B read data register - reg [19:0] C_q; // port B read data register - wire [7:0] OPA; // port A - wire [7:0] OPB; // port B - wire [19:0] OPC; // port B - reg [19:0] ACC_data ; // accumulator register - wire [19:0] sum;// port B read data register - wire [19:0] sum_in;// port B read data register - wire [15:0] product; - wire [19:0] product_extended; - - assign A = {A7,A6,A5,A4,A3,A2,A1,A0}; - assign B = {B7,B6,B5,B4,B3,B2,B1,B0}; - assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0}; - - assign OPA = A_reg ? A_q : A; - assign OPB = B_reg ? B_q : B; - assign OPC = C_reg ? C_q : C; - - assign sum_in = ACC ? ACC_data : OPC;// we can - - assign product = OPA * OPB; - -// The sign extension was not tested - assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product}; - - assign sum = product_extended + sum_in; - - assign Q19 = ACCout ? ACC_data[19] : sum[19]; - assign Q18 = ACCout ? ACC_data[18] : sum[18]; - assign Q17 = ACCout ? ACC_data[17] : sum[17]; - assign Q16 = ACCout ? ACC_data[16] : sum[16]; - assign Q15 = ACCout ? ACC_data[15] : sum[15]; - assign Q14 = ACCout ? ACC_data[14] : sum[14]; - assign Q13 = ACCout ? ACC_data[13] : sum[13]; - assign Q12 = ACCout ? ACC_data[12] : sum[12]; - assign Q11 = ACCout ? ACC_data[11] : sum[11]; - assign Q10 = ACCout ? ACC_data[10] : sum[10]; - assign Q9 = ACCout ? ACC_data[9] : sum[9]; - assign Q8 = ACCout ? ACC_data[8] : sum[8]; - assign Q7 = ACCout ? ACC_data[7] : sum[7]; - assign Q6 = ACCout ? ACC_data[6] : sum[6]; - assign Q5 = ACCout ? ACC_data[5] : sum[5]; - assign Q4 = ACCout ? ACC_data[4] : sum[4]; - assign Q3 = ACCout ? ACC_data[3] : sum[3]; - assign Q2 = ACCout ? ACC_data[2] : sum[2]; - assign Q1 = ACCout ? ACC_data[1] : sum[1]; - assign Q0 = ACCout ? ACC_data[0] : sum[0]; - - always @ (posedge CLK) - begin - A_q <= A; - B_q <= B; - C_q <= C; - if (clr == 1'b1) begin - ACC_data <= 20'b00000000000000000000; - end else begin - ACC_data <= sum; - end - end - -endmodule - -module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK); - //parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value) - parameter AD_reg = 1'b0; - parameter BD_reg = 1'b0; - // IMPORTANT: this has to be in a dedicated line - input D0; // Register File write port - input D1; - input D2; - input D3; - input W_ADR0; - input W_ADR1; - input W_ADR2; - input W_ADR3; - input W_ADR4; - input W_en; - - output AD0;// Register File read port A - output AD1; - output AD2; - output AD3; - input A_ADR0; - input A_ADR1; - input A_ADR2; - input A_ADR3; - input A_ADR4; - - output BD0;//Register File read port B - output BD1; - output BD2; - output BD3; - input B_ADR0; - input B_ADR1; - input B_ADR2; - input B_ADR3; - input B_ADR4; - - input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) - - // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label - - - //type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit - //signal mem : memtype := (others => (others => '0')); - reg [3:0] mem [31:0]; - - wire [4:0] W_ADR;// write address - wire [4:0] A_ADR;// port A read address - wire [4:0] B_ADR;// port B read address - - wire [3:0] D; // write data - wire [3:0] AD; // port A read data - wire [3:0] BD; // port B read data - - reg [3:0] AD_q; // port A read data register - reg [3:0] BD_q; // port B read data register - - integer i; - - assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0}; - assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0}; - assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0}; - - assign D = {D3,D2,D1,D0}; - - initial begin - for (i=0; i<32; i=i+1) begin - mem[i] = 4'b0000; - end - end - - always @ (posedge CLK) begin : P_write - if (W_en == 1'b1) begin - mem[W_ADR] <= D ; - end - end - - assign AD = mem[A_ADR]; - assign BD = mem[B_ADR]; - - always @ (posedge CLK) begin - AD_q <= AD; - BD_q <= BD; - end - - assign AD0 = AD_reg ? AD_q[0] : AD[0]; - assign AD1 = AD_reg ? AD_q[1] : AD[1]; - assign AD2 = AD_reg ? AD_q[2] : AD[2]; - assign AD3 = AD_reg ? AD_q[3] : AD[3]; - - assign BD0 = BD_reg ? BD_q[0] : BD[0]; - assign BD1 = BD_reg ? BD_q[1] : BD[1]; - assign BD2 = BD_reg ? BD_q[2] : BD[2]; - assign BD3 = BD_reg ? BD_q[3] : BD[3]; - -endmodule - -`ifdef EQUIV -`define COMPLEX_DFF -`endif - -`ifdef COMPLEX_DFF -module LUTFF_E ( - output reg O, - input CLK, E, D -); - initial O = 1'b0; - always @(posedge CLK) - if (E) - O <= D; -endmodule - -module LUTFF_SR ( - output reg O, - input CLK, R, D -); - initial O = 1'b0; - always @(posedge CLK) - if (R) - O <= 0; - else - O <= D; -endmodule - -module LUTFF_SS ( - output reg O, - input CLK, S, D -); - initial O = 1'b0; - always @(posedge CLK) - if (S) - O <= 1; - else - O <= D; -endmodule - -module LUTFF_ESR ( - output reg O, - input CLK, E, R, D -); - initial O = 1'b0; - always @(posedge CLK) - if (E) begin - if (R) - O <= 0; - else - O <= D; - end -endmodule - -module LUTFF_ESS ( - output reg O, - input CLK, E, S, D -); - initial O = 1'b0; - always @(posedge CLK) - if (E) begin - if (S) - O <= 1; - else - O <= D; - end -endmodule -`endif // COMPLEX_DFF diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index e22443d25..76973098e 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -55,8 +55,8 @@ struct SynthPass : public ScriptPass log(" -lut \n"); log(" perform synthesis for a k-LUT architecture (default 4).\n"); log("\n"); - log(" -plib \n"); - log(" use the specified Verilog file as a primitive library.\n"); + log(" -ff \n"); + log(" convert FFs to cell types via dfflegalize (can be specified multiple times).\n"); log("\n"); log(" -extra-plib \n"); log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); @@ -83,10 +83,6 @@ struct SynthPass : public ScriptPass log(" enable automatic insertion of IO buffers (otherwise a wrapper\n"); log(" with manually inserted and constrained IO should be used.)\n"); log("\n"); - log(" -complex-dff\n"); - log(" enable support for FFs with enable and synchronous SR (must also be\n"); - log(" supported by the target fabric.)\n"); - log("\n"); log(" -noflatten\n"); log(" do not flatten design after elaboration\n"); log("\n"); @@ -112,23 +108,22 @@ struct SynthPass : public ScriptPass log("\n"); } - string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode; + string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode; std::vector extra_plib, extra_map; + std::vector> extra_ffs; - bool autotop, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; + bool autotop, noalumacc, nofsm, noshare, noregfile, iopad, flatten; int lut; void clear_flags() override { top_module.clear(); - plib.clear(); autotop = false; lut = 4; noalumacc = false; nofsm = false; noshare = false; iopad = false; - complexdff = false; carry_mode = "none"; flatten = true; json_file = ""; @@ -174,8 +169,10 @@ struct SynthPass : public ScriptPass lut = atoi(args[++argidx].c_str()); continue; } - if (args[argidx] == "-plib" && argidx+1 < args.size()) { - plib = args[++argidx]; + if (args[argidx] == "-ff" && argidx+2 < args.size()) { + string cell = args[++argidx]; + string init = args[++argidx]; + extra_ffs.push_back({cell, init}); continue; } if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) { @@ -214,10 +211,6 @@ struct SynthPass : public ScriptPass iopad = true; continue; } - if (args[argidx] == "-complex-dff") { - complexdff = true; - continue; - } if (args[argidx] == "-carry" && argidx+1 < args.size()) { carry_mode = args[++argidx]; if (carry_mode != "none" && carry_mode != "ha") @@ -245,11 +238,6 @@ struct SynthPass : public ScriptPass void script() override { - if (plib.empty()) - run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : "")); - else - run("read_verilog -lib " + plib); - if (help_mode) { run("read_verilog -lib ", "(for each -extra-plib)"); } else for (auto lib : extra_plib) { @@ -339,13 +327,18 @@ struct SynthPass : public ScriptPass if (check_label("map_ffs")) { - if (complexdff) { - run("dfflegalize -cell $_DFF_P_ 0 -cell $_SDFF_PP?_ 0 -cell $_SDFFCE_PP?P_ 0 -cell $_DLATCH_?_ x", "with -complex-dff"); - } else { - run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff"); + if (help_mode) { + run("dfflegalize -cell ...", "(for each -ff)"); + } else if (!extra_map.empty()) { + std::string dff_str = "dfflegalize"; + for (const auto &[cell, init] : extra_ffs) + dff_str += stringf(" -cell %s %s", cell, init); + run(dff_str); } - run("techmap -map +/fabulous/latches_map.v"); - run("techmap -map +/fabulous/ff_map.v"); + run("opt_merge"); + } + + if (check_label("map_extra")) { if (help_mode) { run("techmap -map ...", "(for each -extra-map)"); } else if (!extra_map.empty()) { From c73fd4f70ba0a879e157a093b3c8f8734cc0c49e Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:15:38 +0200 Subject: [PATCH 080/101] fabulous: add `-extra-mlibmap` option, remove legacy `-noregfile` option - this allows to map to any memories - to map legacy register files, use: `-extra-plib regfile.v -extra-mlibmap ram_regfile.txt -extra-map regfile_map.v` Signed-off-by: Leo Moser --- techlibs/fabulous/ram_regfile.txt | 46 ----------------------------- techlibs/fabulous/regfile_map.v | 42 -------------------------- techlibs/fabulous/synth_fabulous.cc | 32 ++++++++++---------- 3 files changed, 17 insertions(+), 103 deletions(-) delete mode 100644 techlibs/fabulous/ram_regfile.txt delete mode 100644 techlibs/fabulous/regfile_map.v diff --git a/techlibs/fabulous/ram_regfile.txt b/techlibs/fabulous/ram_regfile.txt deleted file mode 100644 index af834b005..000000000 --- a/techlibs/fabulous/ram_regfile.txt +++ /dev/null @@ -1,46 +0,0 @@ -# Yosys doesn't support configurable sync/async ports. -# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync - -ram distributed $__REGFILE_AA_ { - abits 5; - width 4; - cost 6; - port sw "W" { - clock posedge "CLK"; - } - port ar "A" { - } - port ar "B" { - } -} - -ram distributed $__REGFILE_SA_ { - abits 5; - width 4; - cost 5; - port sw "W" { - clock posedge "CLK"; - wrtrans all old; - } - port sr "A" { - clock posedge "CLK"; - } - port ar "B" { - } -} - -ram distributed $__REGFILE_SS_ { - abits 5; - width 4; - cost 4; - port sw "W" { - clock posedge "CLK"; - wrtrans all old; - } - port sr "A" { - clock posedge "CLK"; - } - port sr "B" { - clock posedge "CLK"; - } -} diff --git a/techlibs/fabulous/regfile_map.v b/techlibs/fabulous/regfile_map.v deleted file mode 100644 index 14342495e..000000000 --- a/techlibs/fabulous/regfile_map.v +++ /dev/null @@ -1,42 +0,0 @@ -(* techmap_celltype = "$__REGFILE_[AS][AS]_" *) -module \$__REGFILE_XX_ (...); - -parameter _TECHMAP_CELLTYPE_ = ""; -localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S"; -localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S"; - -localparam WIDTH = 4; -localparam ABITS = 5; - -input [WIDTH-1:0] PORT_W_WR_DATA; -input [ABITS-1:0] PORT_W_ADDR; -input PORT_W_WR_EN; - -output [WIDTH-1:0] PORT_A_RD_DATA; -input [ABITS-1:0] PORT_A_ADDR; - -output [WIDTH-1:0] PORT_B_RD_DATA; -input [ABITS-1:0] PORT_B_ADDR; - -// Unused - we have a shared clock - but keep techmap happy -input PORT_W_CLK; -input PORT_A_CLK; -input PORT_B_CLK; - -input CLK_CLK; - -RegFile_32x4 #( - .AD_reg(A_SYNC), - .BD_reg(B_SYNC) -) _TECHMAP_REPLACE_ ( - .D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]), - .W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]), - .W_en(PORT_W_WR_EN), - .AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]), - .A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]), - .BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]), - .B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]), - .CLK(CLK_CLK) -); - -endmodule diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 76973098e..32837af61 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -66,6 +66,10 @@ struct SynthPass : public ScriptPass log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n"); log(" times).\n"); log("\n"); + log(" -extra-mlibmap \n"); + log(" use the provided library convert memory into hardware supported memory (can be specified\n"); + log(" multiple times).\n"); + log("\n"); log(" -nofsm\n"); log(" do not run FSM optimization\n"); log("\n"); @@ -76,9 +80,6 @@ struct SynthPass : public ScriptPass log(" -carry \n"); log(" carry mapping style (none, half-adders, ...) default=none\n"); log("\n"); - log(" -noregfile\n"); - log(" do not map register files\n"); - log("\n"); log(" -iopad\n"); log(" enable automatic insertion of IO buffers (otherwise a wrapper\n"); log(" with manually inserted and constrained IO should be used.)\n"); @@ -109,10 +110,10 @@ struct SynthPass : public ScriptPass } string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode; - std::vector extra_plib, extra_map; + std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; - bool autotop, noalumacc, nofsm, noshare, noregfile, iopad, flatten; + bool autotop, noalumacc, nofsm, noshare, iopad, flatten; int lut; void clear_flags() override @@ -183,6 +184,10 @@ struct SynthPass : public ScriptPass extra_map.push_back(args[++argidx]); continue; } + if (args[argidx] == "-extra-mlibmap" && argidx+1 < args.size()) { + extra_mlibmap.push_back(args[++argidx]); + continue; + } if (args[argidx] == "-nofsm") { nofsm = true; continue; @@ -203,10 +208,6 @@ struct SynthPass : public ScriptPass memory_opts += " -no-rw-check"; continue; } - if (args[argidx] == "-noregfile") { - noregfile = true; - continue; - } if (args[argidx] == "-iopad") { iopad = true; continue; @@ -294,12 +295,13 @@ struct SynthPass : public ScriptPass run("opt_clean"); } - if (check_label("map_ram", "(unless -noregfile)")) { - // RegFile extraction - if (!noregfile) { - run("memory_libmap -lib +/fabulous/ram_regfile.txt"); - run("techmap -map +/fabulous/regfile_map.v"); - } + if (check_label("map_memory")) { + if (help_mode) { + run("memory_libmap -lib ", "(for each -extra-mlibmap)"); + } else + for (auto lib : extra_mlibmap) { + run("memory_libmap -lib " + lib); + } } if (check_label("map_ffram")) { From ec8155e04044ad47319023b61b18c0dff053cee1 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:23:36 +0200 Subject: [PATCH 081/101] fabulous: convert `-iopad` to `-noiopad`, map to `$__FABULOUS_[I|O|T|IO]BUF` - with PCF support in nextpnr fabulous, `-iopad` is now the default - supply further mapping using `-extra-plib` Signed-off-by: Leo Moser --- techlibs/fabulous/io_map.v | 7 ------- techlibs/fabulous/synth_fabulous.cc | 30 ++++++++++++++--------------- 2 files changed, 15 insertions(+), 22 deletions(-) delete mode 100644 techlibs/fabulous/io_map.v diff --git a/techlibs/fabulous/io_map.v b/techlibs/fabulous/io_map.v deleted file mode 100644 index d3736258c..000000000 --- a/techlibs/fabulous/io_map.v +++ /dev/null @@ -1,7 +0,0 @@ -module \$__FABULOUS_IBUF (input PAD, output O); - IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .O(O), .T(1'b1)); -endmodule - -module \$__FABULOUS_OBUF (output PAD, input I); - IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0)); -endmodule diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 32837af61..401607424 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -80,9 +80,9 @@ struct SynthPass : public ScriptPass log(" -carry \n"); log(" carry mapping style (none, half-adders, ...) default=none\n"); log("\n"); - log(" -iopad\n"); - log(" enable automatic insertion of IO buffers (otherwise a wrapper\n"); - log(" with manually inserted and constrained IO should be used.)\n"); + log(" -noiopad\n"); + log(" disable I/O buffer insertion (useful for hierarchical or \n"); + log(" out-of-context flows).\n"); log("\n"); log(" -noflatten\n"); log(" do not flatten design after elaboration\n"); @@ -113,7 +113,7 @@ struct SynthPass : public ScriptPass std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; - bool autotop, noalumacc, nofsm, noshare, iopad, flatten; + bool autotop, noalumacc, nofsm, noshare, noiopad, flatten; int lut; void clear_flags() override @@ -124,7 +124,7 @@ struct SynthPass : public ScriptPass noalumacc = false; nofsm = false; noshare = false; - iopad = false; + noiopad = false; carry_mode = "none"; flatten = true; json_file = ""; @@ -208,8 +208,8 @@ struct SynthPass : public ScriptPass memory_opts += " -no-rw-check"; continue; } - if (args[argidx] == "-iopad") { - iopad = true; + if (args[argidx] == "-noiopad") { + noiopad = true; continue; } if (args[argidx] == "-carry" && argidx+1 < args.size()) { @@ -317,14 +317,13 @@ struct SynthPass : public ScriptPass run("opt -fast"); } - if (check_label("map_iopad", "(if -iopad)")) { - if (iopad || help_mode) { - run("opt -full"); - run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD " - "-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD " - "-tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top", "(skip if '-noiopad')"); - run("techmap -map +/fabulous/io_map.v"); - } + if (check_label("map_iopad", "(skip if -noiopad)") && !noiopad) { + run("opt -full"); + run("iopadmap -bits " + "-inpad $__FABULOUS_IBUF OUT:PAD " + "-outpad $__FABULOUS_OBUF IN:PAD " + "-toutpad $__FABULOUS_TBUF EN:IN:PAD " + "-tinoutpad $__FABULOUS_IOBUF EN:OUT:IN:PAD"); } @@ -349,6 +348,7 @@ struct SynthPass : public ScriptPass map_str += stringf(" -map %s", map); run(map_str); } + run("simplemap"); run("clean"); } From d72cca29457c0a52aeb060751735566a2b3b9840 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:29:14 +0200 Subject: [PATCH 082/101] fabulous: add `-clkbuf-map` option, map to `$__FABULOUS_GBUF` Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 401607424..11fcefbb2 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -58,6 +58,9 @@ struct SynthPass : public ScriptPass log(" -ff \n"); log(" convert FFs to cell types via dfflegalize (can be specified multiple times).\n"); log("\n"); + log(" -clkbuf-map \n"); + log(" insert clock buffers using clkbufmap and map to the specified Verilog file.\n"); + log("\n"); log(" -extra-plib \n"); log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); log(" times).\n"); @@ -109,7 +112,7 @@ struct SynthPass : public ScriptPass log("\n"); } - string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode; + string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, clkbuf_map; std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; @@ -176,6 +179,10 @@ struct SynthPass : public ScriptPass extra_ffs.push_back({cell, init}); continue; } + if (args[argidx] == "-clkbuf-map" && argidx+1 < args.size()) { + clkbuf_map = args[++argidx]; + continue; + } if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) { extra_plib.push_back(args[++argidx]); continue; @@ -361,6 +368,18 @@ struct SynthPass : public ScriptPass run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut)); run("clean"); } + + if (check_label("map_clkbufs")) { + if (help_mode) { + run("clkbufmap -buf $__FABULOUS_GBUF OUT:IN", "(if -clkbuf-map )"); + run("techmap -map ", "(if -clkbuf-map )"); + } else if (clkbuf_map != "") { + run("clkbufmap -buf $__FABULOUS_GBUF OUT:IN"); + run(stringf("techmap -map %s", clkbuf_map)); + run("clean"); + } + } + if (check_label("check")) { run("hierarchy -check"); run("stat"); From f79c0ad21464b24c8b0fb013d7e1c1ad7a9286e8 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 14:44:39 +0200 Subject: [PATCH 083/101] fabulous: add `-multiplier-map` option, map to `$__FABULOUS_MUL` - an example: `-multiplier-map multiplier_map.v 8:8:2:2:10` Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 42 +++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 11fcefbb2..979db0165 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -61,6 +61,9 @@ struct SynthPass : public ScriptPass log(" -clkbuf-map \n"); log(" insert clock buffers using clkbufmap and map to the specified Verilog file.\n"); log("\n"); + log(" -multiplier-map \n"); + log(" convert multiplications to multiplier primitives and map to the specified Verilog file.\n"); + log("\n"); log(" -extra-plib \n"); log(" use the specified Verilog file for extra primitives (can be specified multiple\n"); log(" times).\n"); @@ -112,12 +115,12 @@ struct SynthPass : public ScriptPass log("\n"); } - string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, clkbuf_map; + string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, clkbuf_map, multiplier_map; std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; bool autotop, noalumacc, nofsm, noshare, noiopad, flatten; - int lut; + int lut, multiplier_a_max, multiplier_b_max, multiplier_a_min, multiplier_b_min, multiplier_y_min; void clear_flags() override { @@ -183,6 +186,15 @@ struct SynthPass : public ScriptPass clkbuf_map = args[++argidx]; continue; } + if (args[argidx] == "-multiplier-map" && argidx+6 < args.size()) { + multiplier_map = args[++argidx]; + multiplier_a_max = atoi(args[++argidx].c_str()); + multiplier_b_max = atoi(args[++argidx].c_str()); + multiplier_a_min = atoi(args[++argidx].c_str()); + multiplier_b_min = atoi(args[++argidx].c_str()); + multiplier_y_min = atoi(args[++argidx].c_str()); + continue; + } if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) { extra_plib.push_back(args[++argidx]); continue; @@ -293,6 +305,32 @@ struct SynthPass : public ScriptPass run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)"); else if (lut) run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut)); + if (help_mode || multiplier_map != "") { + run("wreduce t:$mul"); + if (help_mode) { + run("techmap -map +/mul2dsp.v -map -D DSP_A_MAXWIDTH= -D DSP_B_MAXWIDTH= " + "-D DSP_A_MINWIDTH= -D DSP_B_MINWIDTH= -D DSP_Y_MINWIDTH= " + "-D DSP_NAME=$__FABULOUS_MUL", "(if -multiplier-map)"); + } else { + run(stringf("techmap -map +/mul2dsp.v -map %s -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d " + "-D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_Y_MINWIDTH=%d " + "-D DSP_NAME=$__FABULOUS_MUL", + multiplier_map.c_str(), + multiplier_a_max, + multiplier_b_max, + multiplier_a_min, + multiplier_b_min, + multiplier_y_min + ) + ); + } + run("select a:mul2dsp", " (if -multiplier-map)"); + run("setattr -unset mul2dsp", " (if -multiplier-map)"); + run("opt_expr -fine", " (if -multiplier-map)"); + run("wreduce", " (if -multiplier-map)"); + run("select -clear", " (if -multiplier-map)"); + run("chtype -set $mul t:$__soft_mul", "(if -multiplier-map)"); + } if (!noalumacc) run("alumacc", " (unless -noalumacc)"); if (!noshare) From aa84f4a13b91587f09b0e535ecb7335dfa354286 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 15:03:48 +0200 Subject: [PATCH 084/101] fabulous: remove legacy `arith_map.v` mapping Signed-off-by: Leo Moser --- techlibs/fabulous/arith_map.v | 64 ----------------------------- techlibs/fabulous/synth_fabulous.cc | 6 +-- 2 files changed, 3 insertions(+), 67 deletions(-) delete mode 100644 techlibs/fabulous/arith_map.v diff --git a/techlibs/fabulous/arith_map.v b/techlibs/fabulous/arith_map.v deleted file mode 100644 index 8cf5a234b..000000000 --- a/techlibs/fabulous/arith_map.v +++ /dev/null @@ -1,64 +0,0 @@ -`default_nettype none - -`ifdef ARITH_ha -(* techmap_celltype = "$alu" *) -module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO); - -parameter A_SIGNED = 0; -parameter B_SIGNED = 0; -parameter A_WIDTH = 1; -parameter B_WIDTH = 1; -parameter Y_WIDTH = 1; - -parameter _TECHMAP_CONSTMSK_CI_ = 0; -parameter _TECHMAP_CONSTVAL_CI_ = 0; - -(* force_downto *) -input [A_WIDTH-1:0] A; -(* force_downto *) -input [B_WIDTH-1:0] B; -input CI, BI; -(* force_downto *) -output [Y_WIDTH-1:0] X, Y, CO; - -(* force_downto *) -wire [Y_WIDTH-1:0] A_buf, B_buf; -\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); -\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); - -(* force_downto *) -wire [Y_WIDTH-1:0] AA = A_buf; -(* force_downto *) -wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; -wire [Y_WIDTH:0] CARRY; - - -LUT4_HA #( - .INIT(16'b0), - .I0MUX(1'b1) -) carry_statrt ( - .I0(), .I1(CI), .I2(CI), .I3(), - .Ci(), - .Co(CARRY[0]) -); - -// Carry chain -genvar i; -generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - LUT4_HA #( - .INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0) - .I0MUX(1'b1) - ) lut_i ( - .I0(), .I1(AA[i]), .I2(BB[i]), .I3(), - .Ci(CARRY[i]), - .O(Y[i]), - .Co(CARRY[i+1]) - ); - - assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i])); -end endgenerate - -assign X = AA ^ BB; - -endmodule -`endif diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 979db0165..e174da3ab 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -357,8 +357,7 @@ struct SynthPass : public ScriptPass if (check_label("map_gates")) { run("opt -full"); - run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s", - help_mode ? "" : carry_mode.c_str())); + run("techmap -map +/techmap.v"); run("opt -fast"); } @@ -386,11 +385,12 @@ struct SynthPass : public ScriptPass if (check_label("map_extra")) { if (help_mode) { - run("techmap -map ...", "(for each -extra-map)"); + run("techmap -map -D ARITH_...", "(for each -extra-map)"); } else if (!extra_map.empty()) { std::string map_str = "techmap"; for (auto map : extra_map) map_str += stringf(" -map %s", map); + map_str += stringf(" -D ARITH_%s", carry_mode.c_str()); run(map_str); } run("simplemap"); From 253550421710b88388b064849c0378e6270ab5ec Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 15:05:11 +0200 Subject: [PATCH 085/101] fabulous: update CMakeLists.txt Signed-off-by: Leo Moser --- techlibs/fabulous/CMakeLists.txt | 7 ------- 1 file changed, 7 deletions(-) diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt index 53091e5d3..7794a01e4 100644 --- a/techlibs/fabulous/CMakeLists.txt +++ b/techlibs/fabulous/CMakeLists.txt @@ -31,11 +31,4 @@ yosys_pass(synth_fabulous fabulous DATA_FILES cells_map.v - prims.v - latches_map.v - ff_map.v - ram_regfile.txt - regfile_map.v - io_map.v - arith_map.v ) From d50999ea45dec45146fd34cb28cc23f38a7bd509 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 24 Jun 2026 15:15:05 +0200 Subject: [PATCH 086/101] fabulous: format using clang Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 83 ++++++++++++----------------- 1 file changed, 35 insertions(+), 48 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index e174da3ab..525a2e2e8 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -17,17 +17,16 @@ * */ -#include "kernel/register.h" #include "kernel/celltypes.h" -#include "kernel/rtlil.h" #include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct SynthPass : public ScriptPass -{ - SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") { } +struct SynthPass : public ScriptPass { + SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") {} void help() override { @@ -143,28 +142,27 @@ struct SynthPass : public ScriptPass clear_flags(); size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - if (args[argidx] == "-top" && argidx+1 < args.size()) { + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-top" && argidx + 1 < args.size()) { top_module = args[++argidx]; continue; } - if (args[argidx] == "-json" && argidx+1 < args.size()) { + if (args[argidx] == "-json" && argidx + 1 < args.size()) { json_file = args[++argidx]; continue; } - if (args[argidx] == "-blif" && argidx+1 < args.size()) { + if (args[argidx] == "-blif" && argidx + 1 < args.size()) { blif_file = args[++argidx]; continue; } - if (args[argidx] == "-run" && argidx+1 < args.size()) { - size_t pos = args[argidx+1].find(':'); + if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[argidx + 1].find(':'); if (pos == std::string::npos) { run_from = args[++argidx]; run_to = args[argidx]; } else { run_from = args[++argidx].substr(0, pos); - run_to = args[argidx].substr(pos+1); + run_to = args[argidx].substr(pos + 1); } continue; } @@ -172,21 +170,21 @@ struct SynthPass : public ScriptPass autotop = true; continue; } - if (args[argidx] == "-lut" && argidx+1 < args.size()) { + if (args[argidx] == "-lut" && argidx + 1 < args.size()) { lut = atoi(args[++argidx].c_str()); continue; } - if (args[argidx] == "-ff" && argidx+2 < args.size()) { + if (args[argidx] == "-ff" && argidx + 2 < args.size()) { string cell = args[++argidx]; string init = args[++argidx]; extra_ffs.push_back({cell, init}); continue; } - if (args[argidx] == "-clkbuf-map" && argidx+1 < args.size()) { + if (args[argidx] == "-clkbuf-map" && argidx + 1 < args.size()) { clkbuf_map = args[++argidx]; continue; } - if (args[argidx] == "-multiplier-map" && argidx+6 < args.size()) { + if (args[argidx] == "-multiplier-map" && argidx + 6 < args.size()) { multiplier_map = args[++argidx]; multiplier_a_max = atoi(args[++argidx].c_str()); multiplier_b_max = atoi(args[++argidx].c_str()); @@ -195,15 +193,15 @@ struct SynthPass : public ScriptPass multiplier_y_min = atoi(args[++argidx].c_str()); continue; } - if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) { + if (args[argidx] == "-extra-plib" && argidx + 1 < args.size()) { extra_plib.push_back(args[++argidx]); continue; } - if (args[argidx] == "-extra-map" && argidx+1 < args.size()) { + if (args[argidx] == "-extra-map" && argidx + 1 < args.size()) { extra_map.push_back(args[++argidx]); continue; } - if (args[argidx] == "-extra-mlibmap" && argidx+1 < args.size()) { + if (args[argidx] == "-extra-mlibmap" && argidx + 1 < args.size()) { extra_mlibmap.push_back(args[++argidx]); continue; } @@ -231,7 +229,7 @@ struct SynthPass : public ScriptPass noiopad = true; continue; } - if (args[argidx] == "-carry" && argidx+1 < args.size()) { + if (args[argidx] == "-carry" && argidx + 1 < args.size()) { carry_mode = args[++argidx]; if (carry_mode != "none" && carry_mode != "ha") log_cmd_error("Unsupported carry style: %s\n", carry_mode); @@ -260,9 +258,10 @@ struct SynthPass : public ScriptPass { if (help_mode) { run("read_verilog -lib ", "(for each -extra-plib)"); - } else for (auto lib : extra_plib) { - run("read_verilog -lib " + lib); - } + } else + for (auto lib : extra_plib) { + run("read_verilog -lib " + lib); + } if (check_label("begin")) { if (top_module.empty()) { @@ -275,9 +274,7 @@ struct SynthPass : public ScriptPass run("proc"); } - - if (check_label("flatten", "(unless -noflatten)")) - { + if (check_label("flatten", "(unless -noflatten)")) { if (flatten) { run("check"); run("flatten"); @@ -287,7 +284,7 @@ struct SynthPass : public ScriptPass } if (check_label("coarse")) { - run("tribuf -logic"); + run("tribuf -logic"); run("deminout"); // synth pass @@ -309,21 +306,16 @@ struct SynthPass : public ScriptPass run("wreduce t:$mul"); if (help_mode) { run("techmap -map +/mul2dsp.v -map -D DSP_A_MAXWIDTH= -D DSP_B_MAXWIDTH= " - "-D DSP_A_MINWIDTH= -D DSP_B_MINWIDTH= -D DSP_Y_MINWIDTH= " - "-D DSP_NAME=$__FABULOUS_MUL", "(if -multiplier-map)"); + "-D DSP_A_MINWIDTH= -D DSP_B_MINWIDTH= -D DSP_Y_MINWIDTH= " + "-D DSP_NAME=$__FABULOUS_MUL", + "(if -multiplier-map)"); } else { run(stringf("techmap -map +/mul2dsp.v -map %s -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d " "-D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_Y_MINWIDTH=%d " "-D DSP_NAME=$__FABULOUS_MUL", - multiplier_map.c_str(), - multiplier_a_max, - multiplier_b_max, - multiplier_a_min, - multiplier_b_min, - multiplier_y_min - ) - ); - } + multiplier_map.c_str(), multiplier_a_max, multiplier_b_max, multiplier_a_min, multiplier_b_min, + multiplier_y_min)); + } run("select a:mul2dsp", " (if -multiplier-map)"); run("setattr -unset mul2dsp", " (if -multiplier-map)"); run("opt_expr -fine", " (if -multiplier-map)"); @@ -370,7 +362,6 @@ struct SynthPass : public ScriptPass "-tinoutpad $__FABULOUS_IOBUF EN:OUT:IN:PAD"); } - if (check_label("map_ffs")) { if (help_mode) { run("dfflegalize -cell ...", "(for each -ff)"); @@ -423,18 +414,14 @@ struct SynthPass : public ScriptPass run("stat"); } - if (check_label("blif")) - { - if (!blif_file.empty() || help_mode) - { + if (check_label("blif")) { + if (!blif_file.empty() || help_mode) { run("opt_clean -purge"); - run(stringf("write_blif -attr -cname -conn -param %s", - help_mode ? "" : blif_file.c_str())); + run(stringf("write_blif -attr -cname -conn -param %s", help_mode ? "" : blif_file.c_str())); } } - if (check_label("json")) - { + if (check_label("json")) { if (!json_file.empty() || help_mode) run(stringf("write_json %s", help_mode ? "" : json_file)); } From 4fac567673eb6bb8b7166d18bc983732b0d7c3bd Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Tue, 30 Jun 2026 14:56:48 +0200 Subject: [PATCH 087/101] fabulous: add `-arith-map` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 525a2e2e8..f79bf4a73 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -57,6 +57,9 @@ struct SynthPass : public ScriptPass { log(" -ff \n"); log(" convert FFs to cell types via dfflegalize (can be specified multiple times).\n"); log("\n"); + log(" -arith-map \n"); + log(" mapping file for arithmetic operations.\n"); + log("\n"); log(" -clkbuf-map \n"); log(" insert clock buffers using clkbufmap and map to the specified Verilog file.\n"); log("\n"); @@ -114,7 +117,7 @@ struct SynthPass : public ScriptPass { log("\n"); } - string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, clkbuf_map, multiplier_map; + string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, arith_map, clkbuf_map, multiplier_map; std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; @@ -180,6 +183,10 @@ struct SynthPass : public ScriptPass { extra_ffs.push_back({cell, init}); continue; } + if (args[argidx] == "-arith-map" && argidx + 1 < args.size()) { + arith_map = args[++argidx]; + continue; + } if (args[argidx] == "-clkbuf-map" && argidx + 1 < args.size()) { clkbuf_map = args[++argidx]; continue; @@ -347,6 +354,15 @@ struct SynthPass : public ScriptPass { run("opt -undriven -fine"); } + if (check_label("map_arith")) { + if (help_mode) { + run("techmap -map -D ARITH_"); + } else if (!arith_map.empty()) { + run(stringf("techmap -map %s -D ARITH_%s", arith_map.c_str(), carry_mode.c_str())); + } + run("clean"); + } + if (check_label("map_gates")) { run("opt -full"); run("techmap -map +/techmap.v"); @@ -376,12 +392,11 @@ struct SynthPass : public ScriptPass { if (check_label("map_extra")) { if (help_mode) { - run("techmap -map -D ARITH_...", "(for each -extra-map)"); + run("techmap -map ...", "(for each -extra-map)"); } else if (!extra_map.empty()) { std::string map_str = "techmap"; for (auto map : extra_map) map_str += stringf(" -map %s", map); - map_str += stringf(" -D ARITH_%s", carry_mode.c_str()); run(map_str); } run("simplemap"); From 655cb40d0f1569202639124e1fb66af90db8850b Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Tue, 30 Jun 2026 15:29:26 +0200 Subject: [PATCH 088/101] fabulous: add `--cells-map` option Signed-off-by: Leo Moser --- techlibs/fabulous/CMakeLists.txt | 1 - techlibs/fabulous/synth_fabulous.cc | 15 +++++++++++++-- {techlibs => tests/arch}/fabulous/cells_map.v | 0 3 files changed, 13 insertions(+), 3 deletions(-) rename {techlibs => tests/arch}/fabulous/cells_map.v (100%) diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt index 7794a01e4..ff6c08a0d 100644 --- a/techlibs/fabulous/CMakeLists.txt +++ b/techlibs/fabulous/CMakeLists.txt @@ -30,5 +30,4 @@ yosys_pass(synth_fabulous DATA_DIR fabulous DATA_FILES - cells_map.v ) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index f79bf4a73..d77dd54a9 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -57,6 +57,9 @@ struct SynthPass : public ScriptPass { log(" -ff \n"); log(" convert FFs to cell types via dfflegalize (can be specified multiple times).\n"); log("\n"); + log(" -cells-map \n"); + log(" map luts to corresponding cells.\n"); + log("\n"); log(" -arith-map \n"); log(" mapping file for arithmetic operations.\n"); log("\n"); @@ -117,7 +120,7 @@ struct SynthPass : public ScriptPass { log("\n"); } - string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, arith_map, clkbuf_map, multiplier_map; + string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map; std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; @@ -183,6 +186,10 @@ struct SynthPass : public ScriptPass { extra_ffs.push_back({cell, init}); continue; } + if (args[argidx] == "-cells-map" && argidx + 1 < args.size()) { + cells_map = args[++argidx]; + continue; + } if (args[argidx] == "-arith-map" && argidx + 1 < args.size()) { arith_map = args[++argidx]; continue; @@ -409,7 +416,11 @@ struct SynthPass : public ScriptPass { } if (check_label("map_cells")) { - run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut)); + if (help_mode) { + run("techmap -D LUT_K= -map "); + } else if (!cells_map.empty()) { + run(stringf("techmap -D LUT_K=%d -map %s", lut, cells_map.c_str())); + } run("clean"); } diff --git a/techlibs/fabulous/cells_map.v b/tests/arch/fabulous/cells_map.v similarity index 100% rename from techlibs/fabulous/cells_map.v rename to tests/arch/fabulous/cells_map.v From e87d8e162e2aaf6079bd88b897f52975df15ce32 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Tue, 30 Jun 2026 14:57:21 +0200 Subject: [PATCH 089/101] fabulous: update tests for new options Signed-off-by: Leo Moser --- tests/arch/fabulous/arith_map.v | 65 ++++ tests/arch/fabulous/carry.ys | 2 +- tests/arch/fabulous/complexflop.ys | 2 +- tests/arch/fabulous/counter.ys | 2 +- tests/arch/fabulous/ff_map.v | 9 + tests/arch/fabulous/fsm.ys | 2 +- tests/arch/fabulous/io_map.v | 15 + tests/arch/fabulous/latches_map.v | 11 + tests/arch/fabulous/logic.ys | 2 +- tests/arch/fabulous/prims.v | 488 ++++++++++++++++++++++++++++ tests/arch/fabulous/ram_regfile.txt | 46 +++ tests/arch/fabulous/regfile.ys | 2 +- tests/arch/fabulous/regfile_map.v | 42 +++ tests/arch/fabulous/tribuf.ys | 2 +- 14 files changed, 683 insertions(+), 7 deletions(-) create mode 100644 tests/arch/fabulous/arith_map.v create mode 100644 tests/arch/fabulous/ff_map.v create mode 100644 tests/arch/fabulous/io_map.v create mode 100644 tests/arch/fabulous/latches_map.v create mode 100644 tests/arch/fabulous/prims.v create mode 100644 tests/arch/fabulous/ram_regfile.txt create mode 100644 tests/arch/fabulous/regfile_map.v diff --git a/tests/arch/fabulous/arith_map.v b/tests/arch/fabulous/arith_map.v new file mode 100644 index 000000000..b27729f08 --- /dev/null +++ b/tests/arch/fabulous/arith_map.v @@ -0,0 +1,65 @@ +`default_nettype none + +`ifdef ARITH_ha +(* techmap_celltype = "$alu" *) +module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 1; +parameter B_WIDTH = 1; +parameter Y_WIDTH = 1; + +parameter _TECHMAP_CONSTMSK_CI_ = 0; +parameter _TECHMAP_CONSTVAL_CI_ = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +input CI, BI; +(* force_downto *) +output [Y_WIDTH-1:0] X, Y, CO; + +(* force_downto *) +wire [Y_WIDTH-1:0] A_buf, B_buf; +\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); +\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + +(* force_downto *) +wire [Y_WIDTH-1:0] AA = A_buf; +(* force_downto *) +wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; +wire [Y_WIDTH:0] CARRY; + + +LUT4_HA #( + .INIT(16'b0), + .I0MUX(1'b1) +) carry_start ( + .I0(), .I1(CI), .I2(CI), .I3(), + .Ci(), + .Co(CARRY[0]) +); + +// Carry chain +genvar i; +generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice + LUT4_HA #( + .INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0) + .I0MUX(1'b1) + ) lut_i ( + .I0(), .I1(AA[i]), .I2(BB[i]), .I3(), + .Ci(CARRY[i]), + .O(Y[i]), + .Co(CARRY[i+1]) + ); + + assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i])); +end endgenerate + +assign X = AA ^ BB; + +endmodule +`endif + diff --git a/tests/arch/fabulous/carry.ys b/tests/arch/fabulous/carry.ys index bba969d37..b0e723c75 100644 --- a/tests/arch/fabulous/carry.ys +++ b/tests/arch/fabulous/carry.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -carry ha -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-max 10 t:LUT4_HA diff --git a/tests/arch/fabulous/complexflop.ys b/tests/arch/fabulous/complexflop.ys index 13f4522b9..c5f300284 100644 --- a/tests/arch/fabulous/complexflop.ys +++ b/tests/arch/fabulous/complexflop.ys @@ -25,7 +25,7 @@ EOT hierarchy -top top proc flatten -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -complex-dff # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DFFE_PP_ x -ff $_SDFF_PP?_ x -ff $_SDFFCE_PP?P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -extra-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/fabulous/counter.ys b/tests/arch/fabulous/counter.ys index d79b378a6..32647caae 100644 --- a/tests/arch/fabulous/counter.ys +++ b/tests/arch/fabulous/counter.ys @@ -15,7 +15,7 @@ EOT hierarchy -top top proc flatten -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/fabulous/ff_map.v b/tests/arch/fabulous/ff_map.v new file mode 100644 index 000000000..0a03bd692 --- /dev/null +++ b/tests/arch/fabulous/ff_map.v @@ -0,0 +1,9 @@ +module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule + +module \$_DFFE_PP_ (input D, C, E, output Q); LUTFF_E _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E)); endmodule + +module \$_SDFF_PP0_ (input D, C, R, output Q); LUTFF_SR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .R(R)); endmodule +module \$_SDFF_PP1_ (input D, C, R, output Q); LUTFF_SS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .S(R)); endmodule + +module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); LUTFF_ESR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .R(R)); endmodule +module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); LUTFF_ESS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .S(R)); endmodule diff --git a/tests/arch/fabulous/fsm.ys b/tests/arch/fabulous/fsm.ys index 5f7ae28dd..b00c8a388 100644 --- a/tests/arch/fabulous/fsm.ys +++ b/tests/arch/fabulous/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/fabulous/prims.v synth_fabulous +equiv_opt -run :prove -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v async2sync miter -equiv -make_assert -flatten gold gate miter stat diff --git a/tests/arch/fabulous/io_map.v b/tests/arch/fabulous/io_map.v new file mode 100644 index 000000000..031bd4a35 --- /dev/null +++ b/tests/arch/fabulous/io_map.v @@ -0,0 +1,15 @@ +module \$__FABULOUS_IBUF (input PAD, output OUT); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(1'b1), .O(OUT), .PAD(PAD)); +endmodule + +module \$__FABULOUS_OBUF (output PAD, input IN); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(1'b0), .I(IN), .PAD(PAD)); +endmodule + +module \$__FABULOUS_TBUF (output PAD, output IN, output EN); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(!EN), .I(IN), .PAD(PAD)); +endmodule + +module \$__FABULOUS_IOBUF (inout PAD, output OUT, input IN, output EN); + IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.T(!EN), .I(IN), .O(OUT), .PAD(PAD)); +endmodule diff --git a/tests/arch/fabulous/latches_map.v b/tests/arch/fabulous/latches_map.v new file mode 100644 index 000000000..c28f88cf7 --- /dev/null +++ b/tests/arch/fabulous/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/tests/arch/fabulous/logic.ys b/tests/arch/fabulous/logic.ys index 730d9ab54..e5b4773e7 100644 --- a/tests/arch/fabulous/logic.ys +++ b/tests/arch/fabulous/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/fabulous/prims.v synth_fabulous # equivalency check +equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-max 1 t:LUT1 diff --git a/tests/arch/fabulous/prims.v b/tests/arch/fabulous/prims.v new file mode 100644 index 000000000..dfb70dc85 --- /dev/null +++ b/tests/arch/fabulous/prims.v @@ -0,0 +1,488 @@ +module LUT1(output O, input I0); + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; +endmodule + +module LUT2(output O, input I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT3(output O, input I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT4(output O, input I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci); + parameter [15:0] INIT = 0; + parameter I0MUX = 1'b1; + + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + + wire I0_sel = I0MUX ? Ci : I0; + assign O = I0_sel ? s1[1] : s1[0]; + + assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2); +endmodule + +module LUT5(output O, input I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT6(output O, input I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci); + parameter [63:0] INIT = 0; + + wire comb1, comb2; + + LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1)); + LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2)); + + assign O = comb1 ^ Ci; + assign Co = comb1 ? Ci : comb2; +endmodule + + +module LUTFF(input CLK, D, output reg O); + initial O = 1'b0; + always @ (posedge CLK) begin + O <= D; + end +endmodule + +module FABULOUS_MUX2(input I0, I1, S0, output O); + assign O = S0 ? I1 : I0; +endmodule + +module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O); + wire A0 = S0 ? I1 : I0; + wire A1 = S0 ? I3 : I2; + assign O = S1 ? A1 : A0; +endmodule + +module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O); + wire A0 = S0 ? I1 : I0; + wire A1 = S0 ? I3 : I2; + wire A2 = S0 ? I5 : I4; + wire A3 = S0 ? I7 : I6; + wire B0 = S1 ? A1 : A0; + wire B1 = S1 ? A3 : A2; + assign O = S2 ? B1 : B0; +endmodule + +module FABULOUS_LC #( + parameter K = 4, + parameter [2**K-1:0] INIT = 0, + parameter DFF_ENABLE = 1'b0 +) ( + input CLK, + input [K-1:0] I, + output O, + output Q +); + wire f_wire; + + //LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); + generate + if (K == 1) begin + LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0])); + end else + if (K == 2) begin + LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1])); + end else + if (K == 3) begin + LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2])); + end else + if (K == 4) begin + LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3])); + end + endgenerate + + LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); + + assign O = f_wire; +endmodule + +(* blackbox *) +module Global_Clock (output CLK); +`ifndef SYNTHESIS + initial CLK = 0; + always #10 CLK = ~CLK; +`endif +endmodule + +(* blackbox, keep *) +module InPass4_frame_config (input CLK, output O0, O1, O2, O3); + +endmodule + + +(* blackbox, keep *) +module OutPass4_frame_config (input CLK, I0, I1, I2, I3); + +endmodule + +(* blackbox, keep *) +module InPass4_frame_config_mux #( + parameter [3:0] O_reg = 0 +) ( + input CLK, + output O0, + output O1, + output O2, + output O3 +); +endmodule + +(* blackbox, keep *) +module OutPass4_frame_config_mux #( + parameter [3:0] I_reg = 0 +) ( + input I0, + input I1, + input I2, + input I3, + input CLK +); +endmodule + +(* keep *) +module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD); + assign PAD = T ? 1'bz : I; + assign O = PAD; + reg Q_q; + always @(posedge CLK) Q_q <= O; + assign Q = Q_q; +endmodule + + +module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK); + parameter A_reg = 1'b0; + parameter B_reg = 1'b0; + parameter C_reg = 1'b0; + parameter ACC = 1'b0; + parameter signExtension = 1'b0; + parameter ACCout = 1'b0; + + //parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value) + // IMPORTANT: this has to be in a dedicated line + input A7;// operand A + input A6; + input A5; + input A4; + input A3; + input A2; + input A1; + input A0; + input B7;// operand B + input B6; + input B5; + input B4; + input B3; + input B2; + input B1; + input B0; + input C19;// operand C + input C18; + input C17; + input C16; + input C15; + input C14; + input C13; + input C12; + input C11; + input C10; + input C9; + input C8; + input C7; + input C6; + input C5; + input C4; + input C3; + input C2; + input C1; + input C0; + output Q19;// result + output Q18; + output Q17; + output Q16; + output Q15; + output Q14; + output Q13; + output Q12; + output Q11; + output Q10; + output Q9; + output Q8; + output Q7; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; + + input clr; + input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) + // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label + + + wire [7:0] A; // port A read data + wire [7:0] B; // port B read data + wire [19:0] C; // port B read data + reg [7:0] A_q; // port A read data register + reg [7:0] B_q; // port B read data register + reg [19:0] C_q; // port B read data register + wire [7:0] OPA; // port A + wire [7:0] OPB; // port B + wire [19:0] OPC; // port B + reg [19:0] ACC_data ; // accumulator register + wire [19:0] sum;// port B read data register + wire [19:0] sum_in;// port B read data register + wire [15:0] product; + wire [19:0] product_extended; + + assign A = {A7,A6,A5,A4,A3,A2,A1,A0}; + assign B = {B7,B6,B5,B4,B3,B2,B1,B0}; + assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0}; + + assign OPA = A_reg ? A_q : A; + assign OPB = B_reg ? B_q : B; + assign OPC = C_reg ? C_q : C; + + assign sum_in = ACC ? ACC_data : OPC;// we can + + assign product = OPA * OPB; + +// The sign extension was not tested + assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product}; + + assign sum = product_extended + sum_in; + + assign Q19 = ACCout ? ACC_data[19] : sum[19]; + assign Q18 = ACCout ? ACC_data[18] : sum[18]; + assign Q17 = ACCout ? ACC_data[17] : sum[17]; + assign Q16 = ACCout ? ACC_data[16] : sum[16]; + assign Q15 = ACCout ? ACC_data[15] : sum[15]; + assign Q14 = ACCout ? ACC_data[14] : sum[14]; + assign Q13 = ACCout ? ACC_data[13] : sum[13]; + assign Q12 = ACCout ? ACC_data[12] : sum[12]; + assign Q11 = ACCout ? ACC_data[11] : sum[11]; + assign Q10 = ACCout ? ACC_data[10] : sum[10]; + assign Q9 = ACCout ? ACC_data[9] : sum[9]; + assign Q8 = ACCout ? ACC_data[8] : sum[8]; + assign Q7 = ACCout ? ACC_data[7] : sum[7]; + assign Q6 = ACCout ? ACC_data[6] : sum[6]; + assign Q5 = ACCout ? ACC_data[5] : sum[5]; + assign Q4 = ACCout ? ACC_data[4] : sum[4]; + assign Q3 = ACCout ? ACC_data[3] : sum[3]; + assign Q2 = ACCout ? ACC_data[2] : sum[2]; + assign Q1 = ACCout ? ACC_data[1] : sum[1]; + assign Q0 = ACCout ? ACC_data[0] : sum[0]; + + always @ (posedge CLK) + begin + A_q <= A; + B_q <= B; + C_q <= C; + if (clr == 1'b1) begin + ACC_data <= 20'b00000000000000000000; + end else begin + ACC_data <= sum; + end + end + +endmodule + +module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK); + //parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value) + parameter AD_reg = 1'b0; + parameter BD_reg = 1'b0; + // IMPORTANT: this has to be in a dedicated line + input D0; // Register File write port + input D1; + input D2; + input D3; + input W_ADR0; + input W_ADR1; + input W_ADR2; + input W_ADR3; + input W_ADR4; + input W_en; + + output AD0;// Register File read port A + output AD1; + output AD2; + output AD3; + input A_ADR0; + input A_ADR1; + input A_ADR2; + input A_ADR3; + input A_ADR4; + + output BD0;//Register File read port B + output BD1; + output BD2; + output BD3; + input B_ADR0; + input B_ADR1; + input B_ADR2; + input B_ADR3; + input B_ADR4; + + input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top) + + // GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label + + + //type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit + //signal mem : memtype := (others => (others => '0')); + reg [3:0] mem [31:0]; + + wire [4:0] W_ADR;// write address + wire [4:0] A_ADR;// port A read address + wire [4:0] B_ADR;// port B read address + + wire [3:0] D; // write data + wire [3:0] AD; // port A read data + wire [3:0] BD; // port B read data + + reg [3:0] AD_q; // port A read data register + reg [3:0] BD_q; // port B read data register + + integer i; + + assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0}; + assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0}; + assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0}; + + assign D = {D3,D2,D1,D0}; + + initial begin + for (i=0; i<32; i=i+1) begin + mem[i] = 4'b0000; + end + end + + always @ (posedge CLK) begin : P_write + if (W_en == 1'b1) begin + mem[W_ADR] <= D ; + end + end + + assign AD = mem[A_ADR]; + assign BD = mem[B_ADR]; + + always @ (posedge CLK) begin + AD_q <= AD; + BD_q <= BD; + end + + assign AD0 = AD_reg ? AD_q[0] : AD[0]; + assign AD1 = AD_reg ? AD_q[1] : AD[1]; + assign AD2 = AD_reg ? AD_q[2] : AD[2]; + assign AD3 = AD_reg ? AD_q[3] : AD[3]; + + assign BD0 = BD_reg ? BD_q[0] : BD[0]; + assign BD1 = BD_reg ? BD_q[1] : BD[1]; + assign BD2 = BD_reg ? BD_q[2] : BD[2]; + assign BD3 = BD_reg ? BD_q[3] : BD[3]; + +endmodule + +module LUTFF(input CLK, D, output reg O); + initial O = 1'b0; + always @ (posedge CLK) begin + O <= D; + end +endmodule + +module LUTFF_E ( + output reg O, + input CLK, E, D +); + initial O = 1'b0; + always @(posedge CLK) + if (E) + O <= D; +endmodule + +module LUTFF_SR ( + output reg O, + input CLK, R, D +); + initial O = 1'b0; + always @(posedge CLK) + if (R) + O <= 0; + else + O <= D; +endmodule + +module LUTFF_SS ( + output reg O, + input CLK, S, D +); + initial O = 1'b0; + always @(posedge CLK) + if (S) + O <= 1; + else + O <= D; +endmodule + +module LUTFF_ESR ( + output reg O, + input CLK, E, R, D +); + initial O = 1'b0; + always @(posedge CLK) + if (E) begin + if (R) + O <= 0; + else + O <= D; + end +endmodule + +module LUTFF_ESS ( + output reg O, + input CLK, E, S, D +); + initial O = 1'b0; + always @(posedge CLK) + if (E) begin + if (S) + O <= 1; + else + O <= D; + end +endmodule diff --git a/tests/arch/fabulous/ram_regfile.txt b/tests/arch/fabulous/ram_regfile.txt new file mode 100644 index 000000000..af834b005 --- /dev/null +++ b/tests/arch/fabulous/ram_regfile.txt @@ -0,0 +1,46 @@ +# Yosys doesn't support configurable sync/async ports. +# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync + +ram distributed $__REGFILE_AA_ { + abits 5; + width 4; + cost 6; + port sw "W" { + clock posedge "CLK"; + } + port ar "A" { + } + port ar "B" { + } +} + +ram distributed $__REGFILE_SA_ { + abits 5; + width 4; + cost 5; + port sw "W" { + clock posedge "CLK"; + wrtrans all old; + } + port sr "A" { + clock posedge "CLK"; + } + port ar "B" { + } +} + +ram distributed $__REGFILE_SS_ { + abits 5; + width 4; + cost 4; + port sw "W" { + clock posedge "CLK"; + wrtrans all old; + } + port sr "A" { + clock posedge "CLK"; + } + port sr "B" { + clock posedge "CLK"; + } +} diff --git a/tests/arch/fabulous/regfile.ys b/tests/arch/fabulous/regfile.ys index 8d1eedef0..191c596d7 100644 --- a/tests/arch/fabulous/regfile.ys +++ b/tests/arch/fabulous/regfile.ys @@ -10,7 +10,7 @@ module sync_sync(input clk, we, input [4:0] aw, aa, ab, input [3:0] wd, output r endmodule EOT -synth_fabulous -top sync_sync +synth_fabulous -top sync_sync -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -arith-map arith_map.v -cells-map cells_map.v -extra-map ff_map.v -extra-map latches_map.v -extra-mlibmap ram_regfile.txt -extra-map regfile_map.v cd sync_sync select -assert-count 1 t:RegFile_32x4 diff --git a/tests/arch/fabulous/regfile_map.v b/tests/arch/fabulous/regfile_map.v new file mode 100644 index 000000000..14342495e --- /dev/null +++ b/tests/arch/fabulous/regfile_map.v @@ -0,0 +1,42 @@ +(* techmap_celltype = "$__REGFILE_[AS][AS]_" *) +module \$__REGFILE_XX_ (...); + +parameter _TECHMAP_CELLTYPE_ = ""; +localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S"; +localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S"; + +localparam WIDTH = 4; +localparam ABITS = 5; + +input [WIDTH-1:0] PORT_W_WR_DATA; +input [ABITS-1:0] PORT_W_ADDR; +input PORT_W_WR_EN; + +output [WIDTH-1:0] PORT_A_RD_DATA; +input [ABITS-1:0] PORT_A_ADDR; + +output [WIDTH-1:0] PORT_B_RD_DATA; +input [ABITS-1:0] PORT_B_ADDR; + +// Unused - we have a shared clock - but keep techmap happy +input PORT_W_CLK; +input PORT_A_CLK; +input PORT_B_CLK; + +input CLK_CLK; + +RegFile_32x4 #( + .AD_reg(A_SYNC), + .BD_reg(B_SYNC) +) _TECHMAP_REPLACE_ ( + .D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]), + .W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]), + .W_en(PORT_W_WR_EN), + .AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]), + .A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]), + .BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]), + .B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]), + .CLK(CLK_CLK) +); + +endmodule diff --git a/tests/arch/fabulous/tribuf.ys b/tests/arch/fabulous/tribuf.ys index 0dcf1cbab..65305756b 100644 --- a/tests/arch/fabulous/tribuf.ys +++ b/tests/arch/fabulous/tribuf.ys @@ -4,7 +4,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/fabulous/prims.v -map +/simcells.v synth_fabulous -iopad # equivalency check +equiv_opt -assert -map prims.v -map +/simcells.v synth_fabulous -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v -extra-map io_map.v # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 3 t:IO_1_bidirectional_frame_config_pass From b06c57b2bfdec18427fc09cb158ca34020b47525 Mon Sep 17 00:00:00 2001 From: Leo Moser Date: Wed, 1 Jul 2026 10:30:06 +0200 Subject: [PATCH 090/101] fabulous: remove unused `-blif` option Signed-off-by: Leo Moser --- techlibs/fabulous/synth_fabulous.cc | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index d77dd54a9..59358c07e 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -43,10 +43,6 @@ struct SynthPass : public ScriptPass { log(" -auto-top\n"); log(" automatically determine the top of the design hierarchy\n"); log("\n"); - log(" -blif \n"); - log(" write the design to the specified BLIF file. writing of an output file\n"); - log(" is omitted if this parameter is not specified.\n"); - log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); @@ -120,7 +116,7 @@ struct SynthPass : public ScriptPass { log("\n"); } - string top_module, json_file, blif_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map; + string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map; std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; @@ -139,7 +135,6 @@ struct SynthPass : public ScriptPass { carry_mode = "none"; flatten = true; json_file = ""; - blif_file = ""; } void execute(std::vector args, RTLIL::Design *design) override @@ -157,10 +152,6 @@ struct SynthPass : public ScriptPass { json_file = args[++argidx]; continue; } - if (args[argidx] == "-blif" && argidx + 1 < args.size()) { - blif_file = args[++argidx]; - continue; - } if (args[argidx] == "-run" && argidx + 1 < args.size()) { size_t pos = args[argidx + 1].find(':'); if (pos == std::string::npos) { @@ -440,13 +431,6 @@ struct SynthPass : public ScriptPass { run("stat"); } - if (check_label("blif")) { - if (!blif_file.empty() || help_mode) { - run("opt_clean -purge"); - run(stringf("write_blif -attr -cname -conn -param %s", help_mode ? "" : blif_file.c_str())); - } - } - if (check_label("json")) { if (!json_file.empty() || help_mode) run(stringf("write_json %s", help_mode ? "" : json_file)); From 30a813b090077d8c832d81ac0e320b76908938d4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 2 Jul 2026 11:34:22 +0200 Subject: [PATCH 091/101] Update ABC as per 2026-07-02 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index a35f806b8..e026ed538 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit a35f806b8ce47d29537cab973679b5a3523ab085 +Subproject commit e026ed5380f3bdc3beea2ff9ffc23236fc549d5b From 2b4ec9d57a51800b78f9e5fa224c5dd7131d219e Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 6 Jul 2026 13:26:00 +0200 Subject: [PATCH 092/101] Fix covers_nothing. --- kernel/bitpattern.h | 24 +++++++++------ tests/unit/kernel/bitpatternTest.cc | 10 ++++++ tests/verilog/temp/issue4402_syn.v | 48 +++++++++++++++++++++++++++++ 3 files changed, 72 insertions(+), 10 deletions(-) create mode 100644 tests/verilog/temp/issue4402_syn.v diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h index 76c008b89..848a753a5 100644 --- a/kernel/bitpattern.h +++ b/kernel/bitpattern.h @@ -102,15 +102,19 @@ struct BitPatternPool bits_t bits; bits.bitdata = sig.as_const().to_bits(); for (auto &b : bits.bitdata) - if (b > RTLIL::State::S1 && b != RTLIL::State::Sx && b != RTLIL::State::Sz) + if (b > RTLIL::State::S1) b = RTLIL::State::Sa; return bits; } - static bool covers_nothing(const bits_t &bits) + /** + * A literal x/z bit can never match a 2-valued selector, so a pattern containing + * one covers nothing. + */ + static bool covers_nothing(RTLIL::SigSpec sig) { - for (auto &b : bits.bitdata) - if (b == RTLIL::State::Sx || b == RTLIL::State::Sz) + for (auto bit : sig) + if (bit.wire == NULL && (bit.data == RTLIL::State::Sx || bit.data == RTLIL::State::Sz)) return true; return false; } @@ -139,9 +143,9 @@ struct BitPatternPool */ bool has_any(RTLIL::SigSpec sig) { - bits_t bits = sig2bits(sig); - if (covers_nothing(bits)) + if (covers_nothing(sig)) return false; + bits_t bits = sig2bits(sig); for (auto &it : database) if (match(it, bits)) return true; @@ -159,9 +163,9 @@ struct BitPatternPool */ bool has_all(RTLIL::SigSpec sig) { - bits_t bits = sig2bits(sig); - if (covers_nothing(bits)) + if (covers_nothing(sig)) return true; + bits_t bits = sig2bits(sig); for (auto &it : database) if (match(it, bits)) { for (int i = 0; i < width; i++) @@ -182,9 +186,9 @@ struct BitPatternPool bool take(RTLIL::SigSpec sig) { bool status = false; - bits_t bits = sig2bits(sig); - if (covers_nothing(bits)) + if (covers_nothing(sig)) return false; + bits_t bits = sig2bits(sig); for (auto it = database.begin(); it != database.end();) if (match(*it, bits)) { for (int i = 0; i < width; i++) { diff --git a/tests/unit/kernel/bitpatternTest.cc b/tests/unit/kernel/bitpatternTest.cc index 001d47060..a641b85a3 100644 --- a/tests/unit/kernel/bitpatternTest.cc +++ b/tests/unit/kernel/bitpatternTest.cc @@ -11,6 +11,8 @@ TEST(BitpatternTest, has) SigSpec _01a = {RTLIL::S0, RTLIL::S1, RTLIL::Sa}; SigSpec _011 = {RTLIL::S0, RTLIL::S1, RTLIL::S1}; SigSpec _111 = {RTLIL::S1, RTLIL::S1, RTLIL::S1}; + SigSpec _01x = {RTLIL::S0, RTLIL::S1, RTLIL::Sx}; + SigSpec _01z = {RTLIL::S0, RTLIL::S1, RTLIL::Sz}; EXPECT_TRUE(BitPatternPool(_aaa).has_any(_01a)); EXPECT_TRUE(BitPatternPool(_01a).has_any(_01a)); @@ -19,6 +21,10 @@ TEST(BitpatternTest, has) // overlap is symmetric EXPECT_TRUE(BitPatternPool(_01a).has_any(_011)); EXPECT_FALSE(BitPatternPool(_111).has_any(_01a)); + // overlaps nothing + EXPECT_FALSE(BitPatternPool(_011).has_any(_01x)); + EXPECT_FALSE(BitPatternPool(_011).has_any(_01z)); + EXPECT_FALSE(BitPatternPool(_aaa).has_any(_01x)); EXPECT_TRUE(BitPatternPool(_aaa).has_all(_01a)); EXPECT_TRUE(BitPatternPool(_01a).has_all(_01a)); @@ -27,6 +33,10 @@ TEST(BitpatternTest, has) // 01a is not covered by 011 EXPECT_FALSE(BitPatternPool(_011).has_all(_01a)); EXPECT_FALSE(BitPatternPool(_111).has_all(_01a)); + // trivially covered by any pool + EXPECT_TRUE(BitPatternPool(_011).has_all(_01x)); + EXPECT_TRUE(BitPatternPool(_011).has_all(_01z)); + EXPECT_TRUE(BitPatternPool(_111).has_all(_01x)); } YOSYS_NAMESPACE_END diff --git a/tests/verilog/temp/issue4402_syn.v b/tests/verilog/temp/issue4402_syn.v new file mode 100644 index 000000000..b098b8d6f --- /dev/null +++ b/tests/verilog/temp/issue4402_syn.v @@ -0,0 +1,48 @@ +/* Generated by Yosys 0.66+154 (git sha1 23aadd92a-dirty, Release, Clang /nix/store/mw4gasdvwgscgpxpzihjgchfhs3hhqhn-clang-wrapper-21.1.8/bin/clang++ 21.1.8) [git@github.com:YosysHQ/yosys at nella/x-wildcard] */ + +(* top = 1 *) +(* src = "< Date: Mon, 6 Jul 2026 13:47:10 +0200 Subject: [PATCH 093/101] Make opt_dff -sat conflict with -keepdc. --- passes/opt/opt_dff.cc | 13 +++++++++++-- tests/opt/opt_dff_eqbits.ys | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index 1b1c3bf0e..fcb961125 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -1071,7 +1071,7 @@ struct OptDffWorker ff_for_cell.emplace(cell, ff); for (int i = 0; i < ff.width; i++) { - // Skip bits whose reset drives an undefined (x) value + // Skip bits whose reset value is undefined (x) if (ff.has_srst && !is_def(ff.val_srst[i])) continue; if (ff.has_arst && !is_def(ff.val_arst[i])) continue; @@ -1424,7 +1424,9 @@ struct OptDffPass : public Pass { log("\n"); log(" -sat\n"); log(" additionally invoke SAT solver to detect and remove flip-flops (with\n"); - log(" non-constant inputs) that can also be replaced with a constant driver\n"); + log(" non-constant inputs) that can also be replaced with a constant driver,\n"); + log(" or merged with equivalent flip-flops. this reasons in 2-valued logic\n"); + log(" and may resolve don't-care bits, so it is incompatible with -keepdc.\n"); log("\n"); log(" -keepdc\n"); log(" some optimizations change the behavior of the circuit with respect to\n"); @@ -1456,6 +1458,13 @@ struct OptDffPass : public Pass { } extra_args(args, argidx, design); + // The SAT engine reasons in 2-valued logic (a constant x is treated as + // 0), so it can resolve don't-care bits to concrete values -- exactly + // what -keepdc promises not to do. Refuse the combination rather than + // silently ignore -keepdc. + if (opt.sat && opt.keepdc) + log_cmd_error("The -sat and -keepdc options are mutually exclusive.\n"); + bool did_something = false; for (auto mod : design->selected_modules()) { OptDffWorker worker(opt, mod); diff --git a/tests/opt/opt_dff_eqbits.ys b/tests/opt/opt_dff_eqbits.ys index 10e9045e4..f990fe71a 100644 --- a/tests/opt/opt_dff_eqbits.ys +++ b/tests/opt/opt_dff_eqbits.ys @@ -54,3 +54,36 @@ design -copy-from gate -as gate test_case equiv_make gold gate equiv equiv_induct equiv equiv_status -assert + +# verify keepdc exclusivity +design -reset +read_verilog -sv < Date: Mon, 6 Jul 2026 15:49:56 +0200 Subject: [PATCH 094/101] Slang frontend integration --- .gitmodules | 15 +++++++++++++ CMakeLists.txt | 2 ++ frontends/CMakeLists.txt | 1 + frontends/slang/CMakeLists.txt | 39 ++++++++++++++++++++++++++++++++++ frontends/slang/lib | 1 + libs/CMakeLists.txt | 38 +++++++++++++++++++++++++++++++++ libs/boost_regex | 1 + libs/fmt | 1 + libs/slang | 1 + libs/tomlplusplus | 1 + 10 files changed, 100 insertions(+) create mode 100644 frontends/slang/CMakeLists.txt create mode 160000 frontends/slang/lib create mode 160000 libs/boost_regex create mode 160000 libs/fmt create mode 160000 libs/slang create mode 160000 libs/tomlplusplus diff --git a/.gitmodules b/.gitmodules index 9f18be11e..ab798fb71 100644 --- a/.gitmodules +++ b/.gitmodules @@ -5,3 +5,18 @@ [submodule "cxxopts"] path = libs/cxxopts url = https://github.com/jarro2783/cxxopts +[submodule "fmt"] + path = libs/fmt + url = https://github.com/fmtlib/fmt +[submodule "tomlplusplus"] + path = libs/tomlplusplus + url = https://github.com/marzer/tomlplusplus +[submodule "boost_regex"] + path = libs/boost_regex + url = https://github.com/MikePopoloski/regex +[submodule "slang"] + path = libs/slang + url = https://github.com/MikePopoloski/slang +[submodule "sv-elab"] + path = frontends/slang/lib + url = https://github.com/povik/sv-elab diff --git a/CMakeLists.txt b/CMakeLists.txt index a37b52ebe..dad7277f7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,6 +53,7 @@ option(YOSYS_WITHOUT_ZLIB "Disable zlib integration" OFF) option(YOSYS_WITHOUT_LIBFFI "Disable libffi integration" OFF) option(YOSYS_WITHOUT_READLINE "Disable readline integration" OFF) option(YOSYS_WITHOUT_EDITLINE "Disable editline integration" OFF) +option(YOSYS_WITHOUT_SLANG "Disable Slang integration" OFF) option(YOSYS_WITHOUT_TCL "Disable Tcl integration" OFF) option(YOSYS_WITH_PYTHON "Enable Python integration" OFF) @@ -308,6 +309,7 @@ condition(YOSYS_ENABLE_EDITLINE editline_FOUND AND NOT YOSYS_WITHOUT_EDITLINE AN condition(YOSYS_ENABLE_TCL tcl_FOUND AND libtommath_FOUND AND NOT YOSYS_WITHOUT_TCL) condition(YOSYS_ENABLE_PYTHON Python3Devel_FOUND AND PyosysEnv_FOUND AND YOSYS_WITH_PYTHON) condition(YOSYS_ENABLE_VERIFIC YOSYS_VERIFIC_DIR AND zlib_FOUND) +condition(YOSYS_ENABLE_SLANG NOT YOSYS_WITHOUT_SLANG) # Describe dependencies and features # CMake 4.0 would let us use proper conditions, but that's too new for now. diff --git a/frontends/CMakeLists.txt b/frontends/CMakeLists.txt index cc4c02d88..6e6eda488 100644 --- a/frontends/CMakeLists.txt +++ b/frontends/CMakeLists.txt @@ -6,5 +6,6 @@ add_subdirectory(json) add_subdirectory(liberty) add_subdirectory(rpc) add_subdirectory(rtlil) +add_subdirectory(slang) add_subdirectory(verific) add_subdirectory(verilog) diff --git a/frontends/slang/CMakeLists.txt b/frontends/slang/CMakeLists.txt new file mode 100644 index 000000000..dae714de9 --- /dev/null +++ b/frontends/slang/CMakeLists.txt @@ -0,0 +1,39 @@ +include(lib/cmake/GitRevision.cmake) +git_rev_parse(YOSYS_SLANG_REVISION ${CMAKE_CURRENT_SOURCE_DIR}/lib) +git_rev_parse(SLANG_REVISION ${PROJECT_SOURCE_DIR}/libs/slang) +configure_file(${CMAKE_CURRENT_SOURCE_DIR}/lib/src/version.h.in ${CMAKE_CURRENT_BINARY_DIR}/version.h) + +yosys_frontend(slang + lib/src/abort_helpers.cc + lib/src/addressing.cc + lib/src/async_pattern.cc + lib/src/async_pattern.h + lib/src/blackboxes.cc + lib/src/builder.cc + lib/src/cases.cc + lib/src/cases.h + lib/src/diag.cc + lib/src/diag.h + lib/src/initialization.cc + lib/src/lvalue.cc + lib/src/memory.h + lib/src/naming.cc + lib/src/procedural.cc + lib/src/slang_frontend.cc + lib/src/slang_frontend.h + lib/src/statements.h + lib/src/sva.cc + lib/src/variables.cc + lib/src/variables.h + ${CMAKE_CURRENT_BINARY_DIR}/version.h + DEFINITIONS + YOSYS_MAJOR=${YOSYS_VERSION_MAJOR} + YOSYS_MINOR=${YOSYS_VERSION_MINOR} + ENABLE_IF + YOSYS_ENABLE_SLANG + INCLUDE_DIRS + ${CMAKE_CURRENT_BINARY_DIR} + LIBRARIES + $<${YOSYS_ENABLE_SLANG}:slang::slang> + fmt::fmt +) diff --git a/frontends/slang/lib b/frontends/slang/lib new file mode 160000 index 000000000..cac7d9ae8 --- /dev/null +++ b/frontends/slang/lib @@ -0,0 +1 @@ +Subproject commit cac7d9ae8b8b3bc25b846d8f4d2cbadace651f1e diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index ae13387c0..ca0e487f9 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -7,3 +7,41 @@ add_subdirectory(json11) add_subdirectory(minisat) add_subdirectory(sha1) add_subdirectory(subcircuit) +block() + set(BUILD_SHARED_LIBS OFF) + include(FetchContent) + set(FETCHCONTENT_FULLY_DISCONNECTED ON) + + option(FMT_INSTALL OFF) + FetchContent_Declare( + fmt + EXCLUDE_FROM_ALL + SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/fmt + ) + FetchContent_MakeAvailable(fmt) + + FetchContent_Declare( + tomlplusplus + EXCLUDE_FROM_ALL + SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/tomlplusplus + ) + FetchContent_MakeAvailable(tomlplusplus) + + FetchContent_Declare( + boost_regex + EXCLUDE_FROM_ALL + SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/boost_regex + SOURCE_SUBDIR _no_build_ + ) + FetchContent_MakeAvailable(boost_regex) + + if (NOT YOSYS_WITHOUT_SLANG) + set(SLANG_USE_MIMALLOC OFF) + add_subdirectory(slang) + # Headers autodetect based on but when version + # does exist but does not match requirements it becomes problematic + if(NOT Boost_FOUND) + target_compile_definitions(slang_slang PRIVATE BOOST_REGEX_STANDALONE) + endif() + endif() +endblock() diff --git a/libs/boost_regex b/libs/boost_regex new file mode 160000 index 000000000..2b3ac0834 --- /dev/null +++ b/libs/boost_regex @@ -0,0 +1 @@ +Subproject commit 2b3ac0834f31086c6e3c0e0ceb8516e427d5c39d diff --git a/libs/fmt b/libs/fmt new file mode 160000 index 000000000..1be298e1b --- /dev/null +++ b/libs/fmt @@ -0,0 +1 @@ +Subproject commit 1be298e1bd68957e4cd352e1f676f00e07dcfb57 diff --git a/libs/slang b/libs/slang new file mode 160000 index 000000000..617575096 --- /dev/null +++ b/libs/slang @@ -0,0 +1 @@ +Subproject commit 6175750969f17289695f94be5105f6006c82eb61 diff --git a/libs/tomlplusplus b/libs/tomlplusplus new file mode 160000 index 000000000..a43ad3787 --- /dev/null +++ b/libs/tomlplusplus @@ -0,0 +1 @@ +Subproject commit a43ad3787293f4a46b1d70c0924b5a25d10e79fc From 310016a81291065f159e0f11c4e64129ce777fd4 Mon Sep 17 00:00:00 2001 From: nella Date: Tue, 7 Jul 2026 04:03:17 +0200 Subject: [PATCH 095/101] Rm. --- tests/verilog/temp/issue4402_syn.v | 48 ------------------------------ 1 file changed, 48 deletions(-) delete mode 100644 tests/verilog/temp/issue4402_syn.v diff --git a/tests/verilog/temp/issue4402_syn.v b/tests/verilog/temp/issue4402_syn.v deleted file mode 100644 index b098b8d6f..000000000 --- a/tests/verilog/temp/issue4402_syn.v +++ /dev/null @@ -1,48 +0,0 @@ -/* Generated by Yosys 0.66+154 (git sha1 23aadd92a-dirty, Release, Clang /nix/store/mw4gasdvwgscgpxpzihjgchfhs3hhqhn-clang-wrapper-21.1.8/bin/clang++ 21.1.8) [git@github.com:YosysHQ/yosys at nella/x-wildcard] */ - -(* top = 1 *) -(* src = "< Date: Tue, 7 Jul 2026 08:19:11 +0200 Subject: [PATCH 096/101] fabulous: add to CODEOWNERS Signed-off-by: Leo Moser --- CODEOWNERS | 1 + 1 file changed, 1 insertion(+) diff --git a/CODEOWNERS b/CODEOWNERS index 4617c39bb..681854226 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -36,6 +36,7 @@ frontends/ast/ @widlarizer techlibs/intel_alm/ @Ravenslofty techlibs/gowin/ @pepijndevos techlibs/gatemate/ @pu-cc +techlibs/fabulous/ fpga.research.group@gmail.com # pyosys pyosys/* @donn From 2cb3d671d649abd26311c3c934adef15f79a4965 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 Jul 2026 12:19:38 +0200 Subject: [PATCH 097/101] yosys-witness: give error on justice property, support only 'b' --- backends/smt2/witness.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/backends/smt2/witness.py b/backends/smt2/witness.py index 83416c695..8c7d455bd 100755 --- a/backends/smt2/witness.py +++ b/backends/smt2/witness.py @@ -192,8 +192,10 @@ def aiw2yw(input, mapfile, output, skip_x, present_only): header_lines = list(itertools.islice(input, 0, 2)) - if len(header_lines) == 2 and header_lines[1][0] in ".bcjf": + if len(header_lines) == 2 and header_lines[1][0] in ".bj": status = header_lines[0].strip() + if header_lines[1][0]=='j': + raise click.ClickException(f"{input_name}: justice property in AIGER witness not yet supported") if status == "0": raise click.ClickException(f"{input_name}: file contains no trace, the AIGER status is unsat") elif status == "2": From 2d9fdf859c4893ae2048fc46f05713aacd41ff43 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 Jul 2026 14:49:40 +0200 Subject: [PATCH 098/101] Add slang information in README --- README.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 61062243b..7dc02522e 100644 --- a/README.md +++ b/README.md @@ -5,6 +5,9 @@ This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. +Yosys is using [sv-elab](https://github.com/povik/sv-elab) and [slang](https://github.com/MikePopoloski/slang) libraries to provide comprehensive SystemVerilog support. +It supports an (informally defined) synthesizable subset of SystemVerilog in version IEEE 1800-2017 or IEEE 1800-2023. + Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ @@ -67,13 +70,9 @@ on Read the Docs. When cloning Yosys, some required libraries are included as git submodules. Make sure to call e.g. - $ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git - -or - $ git clone https://github.com/YosysHQ/yosys.git $ cd yosys - $ git submodule update --init --recursive + $ git submodule update --init A C++ compiler with C++20 support is required as well as some standard tools such as GNU Flex, GNU Bison (>=3.8), CMake (>=3.28), Make (or other CMake From 61bc3bd2879e3cca71a43b3d3d7ecfc755d7b344 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Tue, 7 Jul 2026 14:51:44 +0200 Subject: [PATCH 099/101] Add option to build/install slang tools --- libs/CMakeLists.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index ca0e487f9..8d264a120 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -43,5 +43,15 @@ block() if(NOT Boost_FOUND) target_compile_definitions(slang_slang PRIVATE BOOST_REGEX_STANDALONE) endif() + if (SLANG_INCLUDE_TOOLS) + # Temporary to prevent build issues + set_target_properties(slang_tidy_obj_lib PROPERTIES YOSYS_IS_ABC ON) + + install(TARGETS slang_driver RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(TARGETS slang_hier RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(TARGETS slang_reflect RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(TARGETS rewriter RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(TARGETS slang_tidy RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) + endif() endif() endblock() From ff8a8677642463a6da95b3f44055b94a19dd7833 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 7 Jul 2026 15:20:19 +0200 Subject: [PATCH 100/101] Bump sv-elab to 2026-07-07 --- frontends/slang/lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/slang/lib b/frontends/slang/lib index cac7d9ae8..2caaaefa8 160000 --- a/frontends/slang/lib +++ b/frontends/slang/lib @@ -1 +1 @@ -Subproject commit cac7d9ae8b8b3bc25b846d8f4d2cbadace651f1e +Subproject commit 2caaaefa831a1d548a681268ccf3eea925ca1312 From 8ad4ffcdd151952768b07658b1cc6af8bb538b28 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 8 Jul 2026 08:34:01 +0200 Subject: [PATCH 101/101] Cleanup --- libs/CMakeLists.txt | 1 - passes/opt/opt_dff.cc | 8 ++++---- tests/arch/fabulous/arith_map.v | 1 - 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/libs/CMakeLists.txt b/libs/CMakeLists.txt index 8d264a120..5ea08ef9d 100644 --- a/libs/CMakeLists.txt +++ b/libs/CMakeLists.txt @@ -50,7 +50,6 @@ block() install(TARGETS slang_driver RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS slang_hier RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS slang_reflect RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) - install(TARGETS rewriter RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS slang_tidy RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}) endif() endif() diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index fcb961125..49275bc7c 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -1032,7 +1032,7 @@ struct OptDffWorker uint16_t flags; bool operator==(const SigKey &o) const { - return flags == o.flags && clk == o.clk && ce == o.ce && srst == o.srst && arst == o.arst + return flags == o.flags && clk == o.clk && ce == o.ce && srst == o.srst && arst == o.arst && aload == o.aload && clr == o.clr && set == o.set && cell_type == o.cell_type; } @@ -1076,7 +1076,7 @@ struct OptDffWorker if (ff.has_arst && !is_def(ff.val_arst[i])) continue; // Class members are assumed equal in the current cycle and proven equal in the next, which needs - // a base case anchoring them to a common known value + // a base case anchoring them to a common known value bool def_init = is_def(ff.val_init[i]); if (!def_init && !ff.has_srst && !ff.has_arst) continue; @@ -1208,7 +1208,7 @@ struct OptDffWorker // Build the next-state function n_lit[idx] of every candidate bit by // folding the FF's control logic on top of the D input (-> next value) - + // Two bits are equivalent if their next states always agree whenever their // current states (and those of every other candidate pair) agree for (auto &cls : classes) { @@ -1249,7 +1249,7 @@ struct OptDffWorker // Assume the induction hypo (that every current class is internally equal in the present cycle), and try // to prove that the members of each class therefore also agree in the next cycle - + // A class survives only if no counterexample exists under that hypo, so combined with the common init/reset // value that every class shares, this makes the equality an inductive invariant -> bits are eq and safe to merge std::vector worklist; diff --git a/tests/arch/fabulous/arith_map.v b/tests/arch/fabulous/arith_map.v index b27729f08..0919beb11 100644 --- a/tests/arch/fabulous/arith_map.v +++ b/tests/arch/fabulous/arith_map.v @@ -62,4 +62,3 @@ assign X = AA ^ BB; endmodule `endif -