Merge branch 'main' into nella/latch-toggle

techlibs/quicklogic/pp3/abc9_map.v

@@ -1,5 +1,5 @@
-// This file exists to map purely-synchronous flops to ABC9 flops, while 
-// mapping flops with asynchronous-set/clear as boxes, this is because ABC9 
+// This file exists to map purely-synchronous flops to ABC9 flops, while
+// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
 // doesn't support asynchronous-set/clear flops in sequential synthesis.
 
 module dffepc (

techlibs/quicklogic/ql_bram_merge.cc

@@ -180,7 +180,7 @@ struct QlBramMergeWorker {
 };
 
 struct QlBramMergePass : public Pass {
-	
+
 	QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
 
 	void help() override

techlibs/quicklogic/ql_bram_types.cc

@@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 
 struct QlBramTypesPass : public Pass {
-	
+
 	QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {}
 
 	void help() override
@@ -81,7 +81,7 @@ struct QlBramTypesPass : public Pass {
 			{
 				if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS)))
 					continue;
-				
+
 				RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS));
 
 				bool split = mode_bits.extract(80).as_bool();
@@ -139,7 +139,7 @@ struct QlBramTypesPass : public Pass {
 						type += "SYNC_";
 					else
 						type += "ASYNC_";
-				} else 
+				} else
 					type += "_BRAM_";
 
 				if (split) {
@@ -162,4 +162,4 @@ struct QlBramTypesPass : public Pass {
 
 } QlBramMergePass;
 
-PRIVATE_NAMESPACE_END
+PRIVATE_NAMESPACE_END

techlibs/quicklogic/qlf_k6n10f/arith_map.v

@@ -96,4 +96,3 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
 
 	assign X = S;
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/brams_map.v

@@ -4285,4 +4285,4 @@ module BRAM2x18_AFIFO (
 		.FLUSH2_i(Async_Flush2)
 	);
 
-endmodule
+endmodule

techlibs/quicklogic/qlf_k6n10f/brams_sim.v

@@ -10946,4 +10946,4 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split (
 	endspecify
 `endif
 
-endmodule
+endmodule

techlibs/quicklogic/qlf_k6n10f/cells_sim.v

@@ -372,4 +372,3 @@ module latchnsre (
 		endspecify
 
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v

@@ -262,4 +262,3 @@ module dsp_t1_10x9x32_cfg_params (
     assign dly_b_o = dly_b_o[8:0];
 
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/ffs_map.v

@@ -130,4 +130,3 @@ module \$__SHREG_DFF_P_ (D, Q, C);
    endgenerate
 
 endmodule
-

techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v

@@ -15,7 +15,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA,
-					   PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);  
+					   PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA);
 
 parameter INIT = 0;
 
@@ -480,4 +480,4 @@ TDP36K #(
 	.FLUSH2_i(1'b0)
 );
 
-endmodule
+endmodule

techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v

@@ -61,4 +61,3 @@ module sram1024x18 (
 	end
 
 endmodule
-

techlibs/quicklogic/synth_quicklogic.cc

@@ -359,7 +359,7 @@ struct SynthQuickLogicPass : public ScriptPass {
 			run("clean");
 			run("opt_lut");
 		}
-		
+
 		if (check_label("iomap", "(for qlf_k6n10f, skip if -noioff)") && (family == "qlf_k6n10f" || help_mode)) {
 			if (ioff || help_mode) {
 				run("ql_ioff");