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Merge branch 'main' into nella/latch-toggle

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nella 2026-07-08 11:41:08 +02:00 • committed by GitHub
commit f5809a7c2c
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675 changed files with 10003 additions and 8149 deletions
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1
techlibs/lattice/cells_bb_ecp5.v
View file

@ -2030,4 +2030,3 @@ module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_
input D_REFCLKI;
output D_FFS_PLOL;
endmodule

1
techlibs/lattice/cells_bb_nexus.v
View file

@ -10589,4 +10589,3 @@ module PCLKDIVSP(CLKIN, CLKOUT, LSRPDIV);
output CLKOUT;
input LSRPDIV;
endmodule

1
techlibs/lattice/cells_bb_xo2.v
View file

@ -579,4 +579,3 @@ endmodule
module TSALL(TSALL);
input TSALL;
endmodule

1
techlibs/lattice/cells_bb_xo3.v
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@ -579,4 +579,3 @@ endmodule
module TSALL(TSALL);
input TSALL;
endmodule

1
techlibs/lattice/cells_bb_xo3d.v
View file

@ -580,4 +580,3 @@ endmodule
module TSALL(TSALL);
input TSALL;
endmodule

4
techlibs/lattice/cells_sim_nexus.v
View file

@ -446,7 +446,7 @@ module OXIDE_DSP_SIM #(
input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,
output wire [Z_WIDTH-1:0] Z
);
localparam M_WIDTH = (A_WIDTH+B_WIDTH);
/******** REGISTERS ********/
@ -511,7 +511,7 @@ module OXIDE_DSP_SIM #(
if (ADDSUB_USED) begin
assign pipe_d = mult_m;
assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
end else begin
assign z_d = mult_m;
end

6
techlibs/lattice/dsp_map_nexus.v
View file

@ -94,10 +94,10 @@ module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS")
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.A(A),
.B(B),
.C({6'b0, C}),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
.Z(Y)
);

6
techlibs/lattice/lattice_dsp_nexus.cc
View file

@ -25,12 +25,12 @@ struct LatticeDspNexusPass : public Pass {
for (auto module : design->selected_modules()) {
lattice_dsp_nexus_pm pm(module, module->cells());
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac18();
pm.run_nexus_preadd18();
}
}
} LatticeDspNexusPass;
PRIVATE_NAMESPACE_END
PRIVATE_NAMESPACE_END

10
techlibs/lattice/lattice_dsp_nexus.pmg
View file

@ -38,7 +38,7 @@ code
mac->setPort(\B, port(mul, \B));
mac->setPort(\C, port(add, add_C));
mac->setPort(\Y, port(add, \Y));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
autoremove(mul);
@ -178,9 +178,9 @@ code
{
Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
return s;
};
@ -205,4 +205,4 @@ code
}
accept;
endcode
endcode

4
techlibs/lattice/lattice_gsr.cc
View file

@ -83,12 +83,12 @@ struct LatticeGsrPass : public Pass {
{
if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
continue;
bool gsren = found_gsr;
if (cell->get_bool_attribute(ID(nogsr)))
gsren = false;
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
}
if (!found_gsr)