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Merge branch 'main' into nella/latch-toggle

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675 changed files with 10003 additions and 8149 deletions
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1
techlibs/achronix/speedster22i/cells_map.v
View file

@ -70,4 +70,3 @@ module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_
(.q(Q), .d(D), .ck(C));
endmodule

3
techlibs/achronix/speedster22i/cells_sim.v
View file

@ -74,6 +74,3 @@ module DFF (output reg q,
q <= d;
endmodule

1
techlibs/analogdevices/arith_map.v
View file

@ -170,4 +170,3 @@ module _80_analogdevices_alu (A, B, CI, BI, X, Y, CO);
assign X = S;
endmodule

4
techlibs/analogdevices/cells_sim.v
View file

@ -958,7 +958,7 @@ module RAMD64X1 (
(DPRA2 => DPO) = 147;
(DPRA3 => DPO) = 139;
(DPRA4 => DPO) = 131;
(DPRA5 => DPO) = 64;
(DPRA5 => DPO) = 64;
(posedge WCLK => (SPO : D)) = 761;
(posedge WCLK => (DPO : D)) = 733;
endspecify
@ -984,7 +984,7 @@ module RAMD64X1 (
(DPRA2 => DPO) = 513;
(DPRA3 => DPO) = 505;
(DPRA4 => DPO) = 496;
(DPRA5 => DPO) = 199;
(DPRA5 => DPO) = 199;
(posedge WCLK => (SPO : D)) = 1798;
(posedge WCLK => (DPO : D)) = 1807;
endspecify

1
techlibs/analogdevices/ff_map.v
View file

@ -60,4 +60,3 @@ module \$_SDFFE_PP1P_ (input D, C, E, R, output Q);
endmodule
`endif

1
techlibs/analogdevices/lut_map.v
View file

@ -76,4 +76,3 @@ module \$lut (A, Y);
endmodule
`endif

16
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -48,8 +48,8 @@ static void fix_carry_chain(Module *module)
SigSpec o = cell->getPort(ID(o));
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
}
}
@ -64,8 +64,8 @@ static void fix_carry_chain(Module *module)
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
adders_to_fix_cells.push_back(cell);
@ -90,10 +90,10 @@ static void fix_carry_chain(Module *module)
c->setPort(ID(b), State::S0);
c->setPort(ID(c), State::S0);
c->setPort(ID(o), bits);
cell->setPort(ID(c), new_bit);
}
}
struct AnlogicCarryFixPass : public Pass {
@ -110,7 +110,7 @@ struct AnlogicCarryFixPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -123,7 +123,7 @@ struct AnlogicCarryFixPass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found.\n");
fix_carry_chain(module);
fix_carry_chain(module);
}
} AnlogicCarryFixPass;

4
techlibs/anlogic/arith_map.v
View file

@ -36,7 +36,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
@ -85,7 +85,7 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
.c(COx[i]),
.o({cout, CO[i]})
);
end: slice
end: slice
endgenerate
/* End implementation */

10
techlibs/anlogic/cells_sim.v
View file

@ -82,7 +82,7 @@ module AL_MAP_LUT1 (
parameter [1:0] INIT = 2'h0;
parameter EQN = "(A)";
assign o = a ? INIT[1] : INIT[0];
assign o = a ? INIT[1] : INIT[0];
endmodule
module AL_MAP_LUT2 (
@ -94,7 +94,7 @@ module AL_MAP_LUT2 (
parameter EQN = "(A)";
wire [1:0] s1 = b ? INIT[ 3:2] : INIT[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT3 (
@ -108,7 +108,7 @@ module AL_MAP_LUT3 (
wire [3:0] s2 = c ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT4 (
@ -124,7 +124,7 @@ module AL_MAP_LUT4 (
wire [7:0] s3 = d ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = c ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = b ? s2[ 3:2] : s2[1:0];
assign o = a ? s1[1] : s1[0];
assign o = a ? s1[1] : s1[0];
endmodule
module AL_MAP_LUT5 (
@ -186,6 +186,6 @@ module AL_MAP_ADDER (
"A_LE_B_CARRY": assign o = { a, 1'b0 };
default: assign o = a + b + c;
endcase
endgenerate
endgenerate
endmodule

24
techlibs/anlogic/eagle_bb.v
View file

@ -44,7 +44,7 @@ endmodule
(* blackbox *)
module EG_LOGIC_MBOOT(
input rebootn,
input [7:0] dynamic_addr
input [7:0] dynamic_addr
);
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b00000000;
@ -242,7 +242,7 @@ module EG_LOGIC_MULT(
input rstan,
input rstbn,
input rstpdn
);
);
parameter INPUT_WIDTH_A = 18;
parameter INPUT_WIDTH_B = 18;
parameter OUTPUT_WIDTH = 36;
@ -561,7 +561,7 @@ module EG_PHY_FIFO(
parameter [13:0] F = 14'b01111111110000;
parameter [13:0] AEP1 = 14'b00000001110000;
parameter [13:0] AFM1 = 14'b01111110000000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [13:0] FM1 = 14'b01111111100000;
parameter [4:0] E = 5'b00000;
parameter [5:0] EP1 = 6'b010000;
parameter GSR = "ENABLE";
@ -604,8 +604,8 @@ module EG_PHY_MULT18(
input rstbn,
input rstpdn,
input sourcea,
input sourceb
);
input sourceb
);
parameter INPUTREGA = "ENABLE";
parameter INPUTREGB = "ENABLE";
parameter OUTPUTREG = "ENABLE";
@ -628,7 +628,7 @@ endmodule
module EG_PHY_GCLK(
input clki,
output clko
);
);
endmodule
(* blackbox *)
@ -647,7 +647,7 @@ module EG_PHY_CLKDIV(
input clki,
input rst,
input rls
);
);
parameter GSR = "DISABLE";
parameter DIV = 2;
endmodule
@ -677,7 +677,7 @@ module EG_PHY_CONFIG(
input dna_shift_en,
input mboot_rebootn,
input [7:0] mboot_dynamic_addr
);
);
parameter MBOOT_AUTO_SEL = "DISABLE";
parameter ADDR_SOURCE_SEL = "STATIC";
parameter STATIC_ADDR = 8'b0;
@ -694,7 +694,7 @@ endmodule
module EG_PHY_OSC(
input osc_dis,
output osc_clk
);
);
parameter STDBY = "DISABLE";
endmodule
@ -919,7 +919,7 @@ module EG_PHY_PLL(
parameter CLKC3_DIV2_ENABLE = "DISABLE";
parameter CLKC4_DIV2_ENABLE = "DISABLE";
parameter FEEDBK_MODE = "NORMAL";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter FEEDBK_PATH = "VCO_PHASE_0";
parameter STDBY_ENABLE = "ENABLE";
parameter CLKC0_FPHASE = 0;
parameter CLKC1_FPHASE = 0;
@ -992,7 +992,7 @@ module EG_LOGIC_BRAM(
parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B;
parameter BYTE_ENABLE = 0;
parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE;
parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;
parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;
parameter MODE = "DP";
parameter REGMODE_A = "NOREG";
parameter REGMODE_B = "NOREG";
@ -1005,7 +1005,7 @@ module EG_LOGIC_BRAM(
parameter INIT_FILE = "NONE";
parameter FILL_ALL = "NONE";
parameter IMPLEMENT = "9K";
endmodule
endmodule
(* blackbox *)
module EG_PHY_ADC(

4
techlibs/common/mul2dsp.v
View file

@ -20,8 +20,8 @@
* ---
*
* Tech-mapping rules for decomposing arbitrarily-sized $mul cells
* into an equivalent collection of smaller `DSP_NAME cells (with the
* same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
* into an equivalent collection of smaller `DSP_NAME cells (with the
* same interface as $mul) no larger than `DSP_[AB]_MAXWIDTH, attached
* to $shl and $add cells.
*
*/

16
techlibs/common/simlib.v
View file

@ -476,7 +476,7 @@ endmodule
//- $sshl (A, B, Y)
//* group binary
//-
//- An arithmatic shift-left operation.
//- An arithmatic shift-left operation.
//- This corresponds to the Verilog '<<<' operator.
//-
module \$sshl (A, B, Y);
@ -720,7 +720,7 @@ endmodule
//- $lt (A, B, Y)
//* group binary
//-
//- A less-than comparison between inputs 'A' and 'B'.
//- A less-than comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '<' operator.
//-
module \$lt (A, B, Y);
@ -752,7 +752,7 @@ endmodule
//- $le (A, B, Y)
//* group binary
//-
//- A less-than-or-equal-to comparison between inputs 'A' and 'B'.
//- A less-than-or-equal-to comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '<=' operator.
//-
module \$le (A, B, Y);
@ -784,7 +784,7 @@ endmodule
//- $eq (A, B, Y)
//* group binary
//-
//- An equality comparison between inputs 'A' and 'B'.
//- An equality comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '==' operator.
//-
module \$eq (A, B, Y);
@ -816,7 +816,7 @@ endmodule
//- $ne (A, B, Y)
//* group binary
//-
//- An inequality comparison between inputs 'A' and 'B'.
//- An inequality comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '!=' operator.
//-
module \$ne (A, B, Y);
@ -944,7 +944,7 @@ endmodule
//- $gt (A, B, Y)
//* group binary
//-
//- A greater-than comparison between inputs 'A' and 'B'.
//- A greater-than comparison between inputs 'A' and 'B'.
//- This corresponds to the Verilog '>' operator.
//-
module \$gt (A, B, Y);
@ -1477,7 +1477,7 @@ endmodule
//- $pow (A, B, Y)
//* group binary
//-
//- Exponentiation of an input (Y = A ** B).
//- Exponentiation of an input (Y = A ** B).
//- This corresponds to the Verilog '**' operator.
//-
`ifndef SIMLIB_NOPOW
@ -1809,7 +1809,7 @@ endmodule
//-
//- $tribuf (A, EN, Y)
//-
//- A tri-state buffer.
//- A tri-state buffer.
//- This buffer conditionally drives the output with the value of the input
//- based on the enable signal.
//-

6
techlibs/efinix/arith_map.v
View file

@ -36,7 +36,7 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire CIx;
(* force_downto *)
wire [Y_WIDTH-1:0] COx;
@ -73,14 +73,14 @@ module _80_efinix_alu (A, B, CI, BI, X, Y, CO);
.O(Y[i]),
.CO(COx[i])
);
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
EFX_ADD #(.I0_POLARITY(1'b1),.I1_POLARITY(1'b1))
adder_cout (
.I0(1'b0),
.I1(1'b0),
.CI(COx[i]),
.O(CO[i])
);
end: slice
end: slice
endgenerate
/* End implementation */

4
techlibs/efinix/brams_map.v
View file

@ -33,14 +33,14 @@ module $__EFINIX_5K_ (...);
PORT_W_WIDTH == 10 ? 9 :
8;
localparam READ_WIDTH =
localparam READ_WIDTH =
PORT_R_WIDTH == 1 ? 1 :
PORT_R_WIDTH == 2 ? 2 :
PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
(IS_5BIT ? 20 : 16);
localparam WRITE_WIDTH =
localparam WRITE_WIDTH =
PORT_W_WIDTH == 1 ? 1 :
PORT_W_WIDTH == 2 ? 2 :
PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :

28
techlibs/efinix/cells_sim.v
View file

@ -1,5 +1,5 @@
module EFX_LUT4(
output O,
output O,
input I0,
input I1,
input I2,
@ -10,7 +10,7 @@ module EFX_LUT4(
wire [7:0] s3 = I3 ? LUTMASK[15:8] : LUTMASK[7:0];
wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module EFX_ADD(
@ -64,9 +64,9 @@ module EFX_FF(
initial Q = 1'b0;
generate
if (SR_SYNC == 1)
if (SR_SYNC == 1)
begin
if (SR_SYNC_PRIORITY == 1)
if (SR_SYNC_PRIORITY == 1)
begin
always @(posedge clk)
if (sr)
@ -93,7 +93,7 @@ module EFX_FF(
Q <= SR_VALUE;
else if (ce)
Q <= d;
end
endgenerate
endmodule
@ -108,16 +108,16 @@ module EFX_GBUFCE(
wire ce;
assign ce = CE_POLARITY ? CE : ~CE;
assign O = I & ce;
endmodule
module EFX_RAM_5K
# (
parameter READ_WIDTH = 20,
parameter WRITE_WIDTH = 20,
localparam READ_ADDR_WIDTH =
localparam READ_ADDR_WIDTH =
(READ_WIDTH == 16) ? 8 : // 256x16
(READ_WIDTH == 8) ? 9 : // 512x8
(READ_WIDTH == 4) ? 10 : // 1024x4
@ -126,8 +126,8 @@ module EFX_RAM_5K
(READ_WIDTH == 20) ? 8 : // 256x20
(READ_WIDTH == 10) ? 9 : // 512x10
(READ_WIDTH == 5) ? 10 : -1, // 1024x5
localparam WRITE_ADDR_WIDTH =
localparam WRITE_ADDR_WIDTH =
(WRITE_WIDTH == 16) ? 8 : // 256x16
(WRITE_WIDTH == 8) ? 9 : // 512x8
(WRITE_WIDTH == 4) ? 10 : // 1024x4
@ -140,13 +140,13 @@ module EFX_RAM_5K
(
input [WRITE_WIDTH-1:0] WDATA,
input [WRITE_ADDR_WIDTH-1:0] WADDR,
input WE,
input WE,
(* clkbuf_sink *)
input WCLK,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input WCLKE,
output [READ_WIDTH-1:0] RDATA,
input [READ_ADDR_WIDTH-1:0] RADDR,
input RE,
input RE,
(* clkbuf_sink *)
input RCLK
);

14
techlibs/efinix/efinix_fixcarry.cc
View file

@ -45,12 +45,12 @@ static void fix_carry_chain(Module *module)
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID::CI));
SigBit bit_o = sigmap(cell->getPort(ID::O));
ci_bits.insert(bit_ci);
ci_bits.insert(bit_ci);
mapping_bits[bit_ci] = bit_o;
}
}
}
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
@ -60,8 +60,8 @@ static void fix_carry_chain(Module *module)
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(I1)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
if (bit_i0 == State::S0 && bit_i1== State::S0)
continue;
adders_to_fix_cells.push_back(cell);
@ -83,7 +83,7 @@ static void fix_carry_chain(Module *module)
c->setPort(ID(I1), State::S1);
c->setPort(ID::CI, State::S0);
c->setPort(ID::CO, new_bit);
cell->setPort(ID::CI, new_bit);
}
}
@ -102,7 +102,7 @@ struct EfinixCarryFixPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
@ -115,7 +115,7 @@ struct EfinixCarryFixPass : public Pass {
if (module == nullptr)
log_cmd_error("No top module found.\n");
fix_carry_chain(module);
fix_carry_chain(module);
}
} EfinixCarryFixPass;

8
techlibs/fabulous/CMakeLists.txt
View file

@ -30,12 +30,4 @@ yosys_pass(synth_fabulous
DATA_DIR
fabulous
DATA_FILES
cells_map.v
prims.v
latches_map.v
ff_map.v
ram_regfile.txt
regfile_map.v
io_map.v
arith_map.v
)

65
techlibs/fabulous/arith_map.v
View file

@ -1,65 +0,0 @@
`default_nettype none
`ifdef ARITH_ha
(* techmap_celltype = "$alu" *)
module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] CARRY;
LUT4_HA #(
.INIT(16'b0),
.I0MUX(1'b1)
) carry_statrt (
.I0(), .I1(CI), .I2(CI), .I3(),
.Ci(),
.Co(CARRY[0])
);
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
LUT4_HA #(
.INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0)
.I0MUX(1'b1)
) lut_i (
.I0(), .I1(AA[i]), .I2(BB[i]), .I3(),
.Ci(CARRY[i]),
.O(Y[i]),
.Co(CARRY[i+1])
);
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
`endif

34
techlibs/fabulous/cells_map.v
View file

@ -1,34 +0,0 @@
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .I5(A[5]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule

9
techlibs/fabulous/ff_map.v
View file

@ -1,9 +0,0 @@
module \$_DFF_P_ (input D, C, output Q); LUTFF _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); LUTFF_E _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E)); endmodule
module \$_SDFF_PP0_ (input D, C, R, output Q); LUTFF_SR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .R(R)); endmodule
module \$_SDFF_PP1_ (input D, C, R, output Q); LUTFF_SS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .S(R)); endmodule
module \$_SDFFCE_PP0P_ (input D, C, E, R, output Q); LUTFF_ESR _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .R(R)); endmodule
module \$_SDFFCE_PP1P_ (input D, C, E, R, output Q); LUTFF_ESS _TECHMAP_REPLACE_ (.D(D), .O(Q), .CLK(C), .E(E), .S(R)); endmodule

8
techlibs/fabulous/io_map.v
View file

@ -1,8 +0,0 @@
module \$__FABULOUS_IBUF (input PAD, output O);
IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .O(O), .T(1'b1));
endmodule
module \$__FABULOUS_OBUF (output PAD, input I);
IO_1_bidirectional_frame_config_pass _TECHMAP_REPLACE_ (.PAD(PAD), .I(I), .T(1'b0));
endmodule

11
techlibs/fabulous/latches_map.v
View file

@ -1,11 +0,0 @@
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule

487
techlibs/fabulous/prims.v
View file

@ -1,487 +0,0 @@
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
assign O = I0 ? INIT[1] : INIT[0];
endmodule
module LUT2(output O, input I0, I1);
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT3(output O, input I0, I1, I2);
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
parameter [15:0] INIT = 0;
parameter I0MUX = 1'b1;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
wire I0_sel = I0MUX ? Ci : I0;
assign O = I0_sel ? s1[1] : s1[0];
assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
endmodule
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci);
parameter [63:0] INIT = 0;
wire comb1, comb2;
LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1));
LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2));
assign O = comb1 ^ Ci;
assign Co = comb1 ? Ci : comb2;
endmodule
module LUTFF(input CLK, D, output reg O);
initial O = 1'b0;
always @ (posedge CLK) begin
O <= D;
end
endmodule
module FABULOUS_MUX2(input I0, I1, S0, output O);
assign O = S0 ? I1 : I0;
endmodule
module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O);
wire A0 = S0 ? I1 : I0;
wire A1 = S0 ? I3 : I2;
assign O = S1 ? A1 : A0;
endmodule
module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O);
wire A0 = S0 ? I1 : I0;
wire A1 = S0 ? I3 : I2;
wire A2 = S0 ? I5 : I4;
wire A3 = S0 ? I7 : I6;
wire B0 = S1 ? A1 : A0;
wire B1 = S1 ? A3 : A2;
assign O = S2 ? B1 : B0;
endmodule
module FABULOUS_LC #(
parameter K = 4,
parameter [2**K-1:0] INIT = 0,
parameter DFF_ENABLE = 1'b0
) (
input CLK,
input [K-1:0] I,
output O,
output Q
);
wire f_wire;
//LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
generate
if (K == 1) begin
LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0]));
end else
if (K == 2) begin
LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1]));
end else
if (K == 3) begin
LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]));
end else
if (K == 4) begin
LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]));
end
endgenerate
LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
assign O = f_wire;
endmodule
(* blackbox *)
module Global_Clock (output CLK);
`ifndef SYNTHESIS
initial CLK = 0;
always #10 CLK = ~CLK;
`endif
endmodule
(* blackbox, keep *)
module InPass4_frame_config (input CLK, output O0, O1, O2, O3);
endmodule
(* blackbox, keep *)
module OutPass4_frame_config (input CLK, I0, I1, I2, I3);
endmodule
(* blackbox, keep *)
module InPass4_frame_config_mux #(
parameter [3:0] O_reg = 0
) (
input CLK,
output O0,
output O1,
output O2,
output O3
);
endmodule
(* blackbox, keep *)
module OutPass4_frame_config_mux #(
parameter [3:0] I_reg = 0
) (
input I0,
input I1,
input I2,
input I3,
input CLK
);
endmodule
(* keep *)
module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD);
assign PAD = T ? 1'bz : I;
assign O = PAD;
reg Q_q;
always @(posedge CLK) Q_q <= O;
assign Q = Q_q;
endmodule
module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK);
parameter A_reg = 1'b0;
parameter B_reg = 1'b0;
parameter C_reg = 1'b0;
parameter ACC = 1'b0;
parameter signExtension = 1'b0;
parameter ACCout = 1'b0;
//parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value)
// IMPORTANT: this has to be in a dedicated line
input A7;// operand A
input A6;
input A5;
input A4;
input A3;
input A2;
input A1;
input A0;
input B7;// operand B
input B6;
input B5;
input B4;
input B3;
input B2;
input B1;
input B0;
input C19;// operand C
input C18;
input C17;
input C16;
input C15;
input C14;
input C13;
input C12;
input C11;
input C10;
input C9;
input C8;
input C7;
input C6;
input C5;
input C4;
input C3;
input C2;
input C1;
input C0;
output Q19;// result
output Q18;
output Q17;
output Q16;
output Q15;
output Q14;
output Q13;
output Q12;
output Q11;
output Q10;
output Q9;
output Q8;
output Q7;
output Q6;
output Q5;
output Q4;
output Q3;
output Q2;
output Q1;
output Q0;
input clr;
input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
wire [7:0] A; // port A read data
wire [7:0] B; // port B read data
wire [19:0] C; // port B read data
reg [7:0] A_q; // port A read data register
reg [7:0] B_q; // port B read data register
reg [19:0] C_q; // port B read data register
wire [7:0] OPA; // port A
wire [7:0] OPB; // port B
wire [19:0] OPC; // port B
reg [19:0] ACC_data ; // accumulator register
wire [19:0] sum;// port B read data register
wire [19:0] sum_in;// port B read data register
wire [15:0] product;
wire [19:0] product_extended;
assign A = {A7,A6,A5,A4,A3,A2,A1,A0};
assign B = {B7,B6,B5,B4,B3,B2,B1,B0};
assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0};
assign OPA = A_reg ? A_q : A;
assign OPB = B_reg ? B_q : B;
assign OPC = C_reg ? C_q : C;
assign sum_in = ACC ? ACC_data : OPC;// we can
assign product = OPA * OPB;
// The sign extension was not tested
assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product};
assign sum = product_extended + sum_in;
assign Q19 = ACCout ? ACC_data[19] : sum[19];
assign Q18 = ACCout ? ACC_data[18] : sum[18];
assign Q17 = ACCout ? ACC_data[17] : sum[17];
assign Q16 = ACCout ? ACC_data[16] : sum[16];
assign Q15 = ACCout ? ACC_data[15] : sum[15];
assign Q14 = ACCout ? ACC_data[14] : sum[14];
assign Q13 = ACCout ? ACC_data[13] : sum[13];
assign Q12 = ACCout ? ACC_data[12] : sum[12];
assign Q11 = ACCout ? ACC_data[11] : sum[11];
assign Q10 = ACCout ? ACC_data[10] : sum[10];
assign Q9 = ACCout ? ACC_data[9] : sum[9];
assign Q8 = ACCout ? ACC_data[8] : sum[8];
assign Q7 = ACCout ? ACC_data[7] : sum[7];
assign Q6 = ACCout ? ACC_data[6] : sum[6];
assign Q5 = ACCout ? ACC_data[5] : sum[5];
assign Q4 = ACCout ? ACC_data[4] : sum[4];
assign Q3 = ACCout ? ACC_data[3] : sum[3];
assign Q2 = ACCout ? ACC_data[2] : sum[2];
assign Q1 = ACCout ? ACC_data[1] : sum[1];
assign Q0 = ACCout ? ACC_data[0] : sum[0];
always @ (posedge CLK)
begin
A_q <= A;
B_q <= B;
C_q <= C;
if (clr == 1'b1) begin
ACC_data <= 20'b00000000000000000000;
end else begin
ACC_data <= sum;
end
end
endmodule
module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK);
//parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
parameter AD_reg = 1'b0;
parameter BD_reg = 1'b0;
// IMPORTANT: this has to be in a dedicated line
input D0; // Register File write port
input D1;
input D2;
input D3;
input W_ADR0;
input W_ADR1;
input W_ADR2;
input W_ADR3;
input W_ADR4;
input W_en;
output AD0;// Register File read port A
output AD1;
output AD2;
output AD3;
input A_ADR0;
input A_ADR1;
input A_ADR2;
input A_ADR3;
input A_ADR4;
output BD0;//Register File read port B
output BD1;
output BD2;
output BD3;
input B_ADR0;
input B_ADR1;
input B_ADR2;
input B_ADR3;
input B_ADR4;
input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
//type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit
//signal mem : memtype := (others => (others => '0'));
reg [3:0] mem [31:0];
wire [4:0] W_ADR;// write address
wire [4:0] A_ADR;// port A read address
wire [4:0] B_ADR;// port B read address
wire [3:0] D; // write data
wire [3:0] AD; // port A read data
wire [3:0] BD; // port B read data
reg [3:0] AD_q; // port A read data register
reg [3:0] BD_q; // port B read data register
integer i;
assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0};
assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0};
assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0};
assign D = {D3,D2,D1,D0};
initial begin
for (i=0; i<32; i=i+1) begin
mem[i] = 4'b0000;
end
end
always @ (posedge CLK) begin : P_write
if (W_en == 1'b1) begin
mem[W_ADR] <= D ;
end
end
assign AD = mem[A_ADR];
assign BD = mem[B_ADR];
always @ (posedge CLK) begin
AD_q <= AD;
BD_q <= BD;
end
assign AD0 = AD_reg ? AD_q[0] : AD[0];
assign AD1 = AD_reg ? AD_q[1] : AD[1];
assign AD2 = AD_reg ? AD_q[2] : AD[2];
assign AD3 = AD_reg ? AD_q[3] : AD[3];
assign BD0 = BD_reg ? BD_q[0] : BD[0];
assign BD1 = BD_reg ? BD_q[1] : BD[1];
assign BD2 = BD_reg ? BD_q[2] : BD[2];
assign BD3 = BD_reg ? BD_q[3] : BD[3];
endmodule
`ifdef EQUIV
`define COMPLEX_DFF
`endif
`ifdef COMPLEX_DFF
module LUTFF_E (
output reg O,
input CLK, E, D
);
initial O = 1'b0;
always @(posedge CLK)
if (E)
O <= D;
endmodule
module LUTFF_SR (
output reg O,
input CLK, R, D
);
initial O = 1'b0;
always @(posedge CLK)
if (R)
O <= 0;
else
O <= D;
endmodule
module LUTFF_SS (
output reg O,
input CLK, S, D
);
initial O = 1'b0;
always @(posedge CLK)
if (S)
O <= 1;
else
O <= D;
endmodule
module LUTFF_ESR (
output reg O,
input CLK, E, R, D
);
initial O = 1'b0;
always @(posedge CLK)
if (E) begin
if (R)
O <= 0;
else
O <= D;
end
endmodule
module LUTFF_ESS (
output reg O,
input CLK, E, S, D
);
initial O = 1'b0;
always @(posedge CLK)
if (E) begin
if (S)
O <= 1;
else
O <= D;
end
endmodule
`endif // COMPLEX_DFF

46
techlibs/fabulous/ram_regfile.txt
View file

@ -1,46 +0,0 @@
# Yosys doesn't support configurable sync/async ports.
# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync
ram distributed $__REGFILE_AA_ {
abits 5;
width 4;
cost 6;
port sw "W" {
clock posedge "CLK";
}
port ar "A" {
}
port ar "B" {
}
}
ram distributed $__REGFILE_SA_ {
abits 5;
width 4;
cost 5;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port ar "B" {
}
}
ram distributed $__REGFILE_SS_ {
abits 5;
width 4;
cost 4;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port sr "B" {
clock posedge "CLK";
}
}

42
techlibs/fabulous/regfile_map.v
View file

@ -1,42 +0,0 @@
(* techmap_celltype = "$__REGFILE_[AS][AS]_" *)
module \$__REGFILE_XX_ (...);
parameter _TECHMAP_CELLTYPE_ = "";
localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S";
localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S";
localparam WIDTH = 4;
localparam ABITS = 5;
input [WIDTH-1:0] PORT_W_WR_DATA;
input [ABITS-1:0] PORT_W_ADDR;
input PORT_W_WR_EN;
output [WIDTH-1:0] PORT_A_RD_DATA;
input [ABITS-1:0] PORT_A_ADDR;
output [WIDTH-1:0] PORT_B_RD_DATA;
input [ABITS-1:0] PORT_B_ADDR;
// Unused - we have a shared clock - but keep techmap happy
input PORT_W_CLK;
input PORT_A_CLK;
input PORT_B_CLK;
input CLK_CLK;
RegFile_32x4 #(
.AD_reg(A_SYNC),
.BD_reg(B_SYNC)
) _TECHMAP_REPLACE_ (
.D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]),
.W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]),
.W_en(PORT_W_WR_EN),
.AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]),
.A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]),
.BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]),
.B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]),
.CLK(CLK_CLK)
);
endmodule

266
techlibs/fabulous/synth_fabulous.cc
View file

@ -17,17 +17,16 @@
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
#include "kernel/register.h"
#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthPass : public ScriptPass
{
SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") { }
struct SynthPass : public ScriptPass {
SynthPass() : ScriptPass("synth_fabulous", "FABulous synthesis script") {}
void help() override
{
@ -44,14 +43,6 @@ struct SynthPass : public ScriptPass
log(" -auto-top\n");
log(" automatically determine the top of the design hierarchy\n");
log("\n");
log(" -blif <file>\n");
log(" write the design to the specified BLIF file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -edif <file>\n");
log(" write the design to the specified EDIF file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
@ -59,11 +50,20 @@ struct SynthPass : public ScriptPass
log(" -lut <k>\n");
log(" perform synthesis for a k-LUT architecture (default 4).\n");
log("\n");
log(" -vpr\n");
log(" perform synthesis for the FABulous VPR flow (using slightly different techmapping).\n");
log(" -ff <cell_type_pattern> <init_values>\n");
log(" convert FFs to cell types via dfflegalize (can be specified multiple times).\n");
log("\n");
log(" -plib <primitive_library.v>\n");
log(" use the specified Verilog file as a primitive library.\n");
log(" -cells-map <cells_map>\n");
log(" map luts to corresponding cells.\n");
log("\n");
log(" -arith-map <arith_map>\n");
log(" mapping file for arithmetic operations.\n");
log("\n");
log(" -clkbuf-map <clkbuf_map>\n");
log(" insert clock buffers using clkbufmap and map to the specified Verilog file.\n");
log("\n");
log(" -multiplier-map <multiplier_map> <a_max> <b_max> <a_min> <b_min> <y_min>\n");
log(" convert multiplications to multiplier primitives and map to the specified Verilog file.\n");
log("\n");
log(" -extra-plib <primitive_library.v>\n");
log(" use the specified Verilog file for extra primitives (can be specified multiple\n");
@ -73,8 +73,9 @@ struct SynthPass : public ScriptPass
log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
log(" times).\n");
log("\n");
log(" -encfile <file>\n");
log(" passed to 'fsm_recode' via 'fsm'\n");
log(" -extra-mlibmap <memory_map.txt>\n");
log(" use the provided library convert memory into hardware supported memory (can be specified\n");
log(" multiple times).\n");
log("\n");
log(" -nofsm\n");
log(" do not run FSM optimization\n");
@ -86,16 +87,9 @@ struct SynthPass : public ScriptPass
log(" -carry <none|ha>\n");
log(" carry mapping style (none, half-adders, ...) default=none\n");
log("\n");
log(" -noregfile\n");
log(" do not map register files\n");
log("\n");
log(" -iopad\n");
log(" enable automatic insertion of IO buffers (otherwise a wrapper\n");
log(" with manually inserted and constrained IO should be used.)\n");
log("\n");
log(" -complex-dff\n");
log(" enable support for FFs with enable and synchronous SR (must also be\n");
log(" supported by the target fabric.)\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design after elaboration\n");
@ -128,24 +122,22 @@ struct SynthPass : public ScriptPass
log("\n");
}
string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode, latches;
std::vector<string> extra_plib, extra_map;
string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map;
std::vector<string> extra_plib, extra_map, extra_mlibmap;
std::vector<std::pair<string, string>> extra_ffs;
bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
int lut;
bool autotop, noalumacc, nofsm, noshare, noiopad, flatten;
int lut, multiplier_a_max, multiplier_b_max, multiplier_a_min, multiplier_b_min, multiplier_y_min;
void clear_flags() override
{
top_module.clear();
plib.clear();
autotop = false;
lut = 4;
forvpr = false;
noalumacc = false;
nofsm = false;
noshare = false;
iopad = false;
complexdff = false;
noiopad = false;
carry_mode = "none";
flatten = true;
json_file = "";
@ -159,55 +151,73 @@ struct SynthPass : public ScriptPass
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-top" && argidx + 1 < args.size()) {
top_module = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
if (args[argidx] == "-json" && argidx + 1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-blif" && argidx+1 < args.size()) {
blif_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (args[argidx] == "-run" && argidx + 1 < args.size()) {
size_t pos = args[argidx + 1].find(':');
if (pos == std::string::npos) {
run_from = args[++argidx];
run_to = args[argidx];
} else {
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
run_to = args[argidx].substr(pos + 1);
}
continue;
}
if (args[argidx] == "-vpr") {
forvpr = true;
continue;
}
if (args[argidx] == "-auto-top") {
autotop = true;
continue;
}
if (args[argidx] == "-lut") {
if (args[argidx] == "-lut" && argidx + 1 < args.size()) {
lut = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-plib" && argidx+1 < args.size()) {
plib = args[++argidx];
if (args[argidx] == "-ff" && argidx + 2 < args.size()) {
string cell = args[++argidx];
string init = args[++argidx];
extra_ffs.push_back({cell, init});
continue;
}
if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) {
if (args[argidx] == "-cells-map" && argidx + 1 < args.size()) {
cells_map = args[++argidx];
continue;
}
if (args[argidx] == "-arith-map" && argidx + 1 < args.size()) {
arith_map = args[++argidx];
continue;
}
if (args[argidx] == "-clkbuf-map" && argidx + 1 < args.size()) {
clkbuf_map = args[++argidx];
continue;
}
if (args[argidx] == "-multiplier-map" && argidx + 6 < args.size()) {
multiplier_map = args[++argidx];
multiplier_a_max = atoi(args[++argidx].c_str());
multiplier_b_max = atoi(args[++argidx].c_str());
multiplier_a_min = atoi(args[++argidx].c_str());
multiplier_b_min = atoi(args[++argidx].c_str());
multiplier_y_min = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-extra-plib" && argidx + 1 < args.size()) {
extra_plib.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-extra-map" && argidx+1 < args.size()) {
if (args[argidx] == "-extra-map" && argidx + 1 < args.size()) {
extra_map.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-extra-mlibmap" && argidx + 1 < args.size()) {
extra_mlibmap.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-nofsm") {
nofsm = true;
continue;
@ -228,19 +238,11 @@ struct SynthPass : public ScriptPass
memory_opts += " -no-rw-check";
continue;
}
if (args[argidx] == "-noregfile") {
noregfile = true;
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-iopad") {
iopad = true;
continue;
}
if (args[argidx] == "-complex-dff") {
complexdff = true;
continue;
}
if (args[argidx] == "-carry") {
if (args[argidx] == "-carry" && argidx + 1 < args.size()) {
carry_mode = args[++argidx];
if (carry_mode != "none" && carry_mode != "ha")
log_cmd_error("Unsupported carry style: %s\n", carry_mode);
@ -273,16 +275,12 @@ struct SynthPass : public ScriptPass
void script() override
{
if (plib.empty())
run(stringf("read_verilog %s -lib +/fabulous/prims.v", complexdff ? "-DCOMPLEX_DFF" : ""));
else
run("read_verilog -lib " + plib);
if (help_mode) {
run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
} else for (auto lib : extra_plib) {
run("read_verilog -lib " + lib);
}
} else
for (auto lib : extra_plib) {
run("read_verilog -lib " + lib);
}
if (check_label("begin")) {
if (top_module.empty()) {
@ -295,9 +293,7 @@ struct SynthPass : public ScriptPass
run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
}
if (check_label("flatten", "(unless -noflatten)"))
{
if (check_label("flatten", "(unless -noflatten)")) {
if (flatten) {
run("check");
run("flatten");
@ -307,7 +303,7 @@ struct SynthPass : public ScriptPass
}
if (check_label("coarse")) {
run("tribuf -logic");
run("tribuf -logic");
run("deminout");
// synth pass
@ -325,6 +321,27 @@ struct SynthPass : public ScriptPass
run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
else if (lut)
run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut));
if (help_mode || multiplier_map != "") {
run("wreduce t:$mul");
if (help_mode) {
run("techmap -map +/mul2dsp.v -map <multiplier_map> -D DSP_A_MAXWIDTH=<a_max> -D DSP_B_MAXWIDTH=<b_max> "
"-D DSP_A_MINWIDTH=<a_min> -D DSP_B_MINWIDTH=<b_min> -D DSP_Y_MINWIDTH=<y_min> "
"-D DSP_NAME=$__FABULOUS_MUL",
"(if -multiplier-map)");
} else {
run(stringf("techmap -map +/mul2dsp.v -map %s -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d "
"-D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_Y_MINWIDTH=%d "
"-D DSP_NAME=$__FABULOUS_MUL",
multiplier_map.c_str(), multiplier_a_max, multiplier_b_max, multiplier_a_min, multiplier_b_min,
multiplier_y_min));
}
run("select a:mul2dsp", " (if -multiplier-map)");
run("setattr -unset mul2dsp", " (if -multiplier-map)");
run("opt_expr -fine", " (if -multiplier-map)");
run("wreduce", " (if -multiplier-map)");
run("select -clear", " (if -multiplier-map)");
run("chtype -set $mul t:$__soft_mul", "(if -multiplier-map)");
}
if (!noalumacc)
run("alumacc", " (unless -noalumacc)");
if (!noshare)
@ -334,12 +351,13 @@ struct SynthPass : public ScriptPass
run("opt_clean");
}
if (check_label("map_ram", "(unless -noregfile)")) {
// RegFile extraction
if (!noregfile) {
run("memory_libmap -lib +/fabulous/ram_regfile.txt");
run("techmap -map +/fabulous/regfile_map.v");
}
if (check_label("map_memory")) {
if (help_mode) {
run("memory_libmap -lib <memory_map.txt>", "(for each -extra-mlibmap)");
} else
for (auto lib : extra_mlibmap) {
run("memory_libmap -lib " + lib);
}
}
if (check_label("map_ffram")) {
@ -348,34 +366,47 @@ struct SynthPass : public ScriptPass
run("opt -undriven -fine");
}
if (check_label("map_arith")) {
if (help_mode) {
run("techmap -map <arith_map.v> -D ARITH_<carry>");
} else if (!arith_map.empty()) {
run(stringf("techmap -map %s -D ARITH_%s", arith_map.c_str(), carry_mode.c_str()));
}
run("clean");
}
if (check_label("map_gates")) {
run("opt -full");
run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s",
help_mode ? "<carry>" : carry_mode.c_str()));
run("techmap -map +/techmap.v");
run("opt -fast");
}
if (check_label("map_iopad", "(if -iopad)")) {
if (iopad || help_mode) {
run("opt -full");
run("iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD "
"-toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD "
"-tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top", "(skip if '-noiopad')");
run("techmap -map +/fabulous/io_map.v");
}
if (check_label("map_iopad", "(skip if -noiopad)") && !noiopad) {
run("opt -full");
run("iopadmap -bits "
"-inpad $__FABULOUS_IBUF OUT:PAD "
"-outpad $__FABULOUS_OBUF IN:PAD "
"-toutpad $__FABULOUS_TBUF EN:IN:PAD "
"-tinoutpad $__FABULOUS_IOBUF EN:OUT:IN:PAD");
}
if (check_label("map_ffs")) {
if (complexdff) {
run("dfflegalize -cell $_DFF_P_ 0 -cell $_SDFF_PP?_ 0 -cell $_SDFFCE_PP?P_ 0 -cell $_DLATCH_?_ x", "with -complex-dff");
} else {
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
if (help_mode) {
run("dfflegalize -cell <cell_type_pattern> <init_values>...", "(for each -ff)");
} else if (!extra_map.empty()) {
std::string dff_str = "dfflegalize";
for (const auto &[cell, init] : extra_ffs)
dff_str += stringf(" -cell %s %s", cell, init);
run(dff_str);
}
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v");
run("opt_merge");
}
if (check_label("map_extra")) {
if (help_mode) {
run("techmap -map <extra_map.v>...", "(for each -extra-map)");
} else if (!extra_map.empty()) {
@ -384,6 +415,7 @@ struct SynthPass : public ScriptPass
map_str += stringf(" -map %s", map);
run(map_str);
}
run("simplemap");
run("clean");
}
@ -393,27 +425,31 @@ struct SynthPass : public ScriptPass
}
if (check_label("map_cells")) {
if (!forvpr)
run(stringf("techmap -D LUT_K=%d -map +/fabulous/cells_map.v", lut));
if (help_mode) {
run("techmap -D LUT_K=<lut> -map <cells_map.v>");
} else if (!cells_map.empty()) {
run(stringf("techmap -D LUT_K=%d -map %s", lut, cells_map.c_str()));
}
run("clean");
}
if (check_label("map_clkbufs")) {
if (help_mode) {
run("clkbufmap -buf $__FABULOUS_GBUF OUT:IN", "(if -clkbuf-map <clkbuf_map.v>)");
run("techmap -map <clkbuf_map.v>", "(if -clkbuf-map <clkbuf_map.v>)");
} else if (clkbuf_map != "") {
run("clkbufmap -buf $__FABULOUS_GBUF OUT:IN");
run(stringf("techmap -map %s", clkbuf_map));
run("clean");
}
}
if (check_label("check")) {
run("hierarchy -check");
run("stat");
}
if (check_label("blif"))
{
if (!blif_file.empty() || help_mode)
{
run("opt_clean -purge");
run(stringf("write_blif -attr -cname -conn -param %s",
help_mode ? "<file-name>" : blif_file.c_str()));
}
}
if (check_label("json"))
{
if (check_label("json")) {
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}

2
techlibs/fix_mod.py
View file

@ -23,7 +23,7 @@ def main():
in_mod = True
elif in_mod:
decl += line
if in_mod and decl.rstrip()[-1] == ';':
in_mod = False
modules[mod] = decl

138
techlibs/gatemate/arith_map.v
View file

@ -1,69 +1,69 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1)
begin: slice
CC_ADDF addf_i (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.CO(CO[i]),
.S(Y[i])
);
end
endgenerate
assign X = AA ^ BB;
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$alu" *)
module _80_gatemate_alu(A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] C = {CO, CI};
genvar i;
generate
for (i = 0; i < Y_WIDTH; i = i + 1)
begin: slice
CC_ADDF addf_i (
.A(AA[i]),
.B(BB[i]),
.CI(C[i]),
.CO(CO[i]),
.S(Y[i])
);
end
endgenerate
assign X = AA ^ BB;
endmodule

1764
techlibs/gatemate/brams_map.v
View file

File diff suppressed because it is too large Load diff

680
techlibs/gatemate/cells_bb.v
View file

@ -1,340 +1,340 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOCK_REQ = 1,
parameter CLK270_DOUB = 0,
parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *) (* keep *)
module CC_SERDES #(
parameter [4:0] RX_BUF_RESET_TIME = 3,
parameter [4:0] RX_PCS_RESET_TIME = 3,
parameter [4:0] RX_RESET_TIMER_PRESC = 0,
parameter [0:0] RX_RESET_DONE_GATE = 0,
parameter [4:0] RX_CDR_RESET_TIME = 3,
parameter [4:0] RX_EQA_RESET_TIME = 3,
parameter [4:0] RX_PMA_RESET_TIME = 3,
parameter [0:0] RX_WAIT_CDR_LOCK = 1,
parameter [0:0] RX_CALIB_EN = 0,
parameter [0:0] RX_CALIB_OVR = 0,
parameter [3:0] RX_CALIB_VAL = 0,
parameter [2:0] RX_RTERM_VCMSEL = 4,
parameter [0:0] RX_RTERM_PD = 0,
parameter [7:0] RX_EQA_CKP_LF = 8'hA3,
parameter [7:0] RX_EQA_CKP_HF = 8'hA3,
parameter [7:0] RX_EQA_CKP_OFFSET = 8'h01,
parameter [0:0] RX_EN_EQA = 0,
parameter [3:0] RX_EQA_LOCK_CFG = 0,
parameter [4:0] RX_TH_MON1 = 8,
parameter [3:0] RX_EN_EQA_EXT_VALUE = 0,
parameter [4:0] RX_TH_MON2 = 8,
parameter [4:0] RX_TAPW = 8,
parameter [4:0] RX_AFE_OFFSET = 8,
parameter [15:0] RX_EQA_CONFIG = 16'h01C0,
parameter [4:0] RX_AFE_PEAK = 16,
parameter [3:0] RX_AFE_GAIN = 8,
parameter [2:0] RX_AFE_VCMSEL = 4,
parameter [7:0] RX_CDR_CKP = 8'hF8,
parameter [7:0] RX_CDR_CKI = 0,
parameter [6:0] RX_CDR_TRANS_TH = 7'h08,
parameter [7:0] RX_CDR_LOCK_CFG = 8'hD5,
parameter [14:0] RX_CDR_FREQ_ACC = 0,
parameter [15:0] RX_CDR_PHASE_ACC = 0,
parameter [1:0] RX_CDR_SET_ACC_CONFIG = 0,
parameter [0:0] RX_CDR_FORCE_LOCK = 0,
parameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,
parameter [0:0] RX_MCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_MCOMMA_ALIGN = 0,
parameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,
parameter [0:0] RX_PCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_PCOMMA_ALIGN = 0,
parameter [1:0] RX_ALIGN_COMMA_WORD = 0,
parameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,
parameter [1:0] RX_SLIDE_MODE = 0,
parameter [0:0] RX_COMMA_DETECT_EN_OVR = 0,
parameter [0:0] RX_COMMA_DETECT_EN = 0,
parameter [1:0] RX_SLIDE = 0,
parameter [0:0] RX_EYE_MEAS_EN = 0,
parameter [14:0] RX_EYE_MEAS_CFG = 0,
parameter [5:0] RX_MON_PH_OFFSET = 0,
parameter [3:0] RX_EI_BIAS = 0,
parameter [3:0] RX_EI_BW_SEL = 4,
parameter [0:0] RX_EN_EI_DETECTOR_OVR = 0,
parameter [0:0] RX_EN_EI_DETECTOR = 0,
parameter [0:0] RX_DATA_SEL = 0,
parameter [0:0] RX_BUF_BYPASS = 0,
parameter [0:0] RX_CLKCOR_USE = 0,
parameter [5:0] RX_CLKCOR_MIN_LAT = 32,
parameter [5:0] RX_CLKCOR_MAX_LAT = 39,
parameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,
parameter [0:0] RX_PMA_LOOPBACK = 0,
parameter [0:0] RX_PCS_LOOPBACK = 0,
parameter [1:0] RX_DATAPATH_SEL = 3,
parameter [0:0] RX_PRBS_OVR = 0,
parameter [2:0] RX_PRBS_SEL = 0,
parameter [0:0] RX_LOOPBACK_OVR = 0,
parameter [0:0] RX_PRBS_CNT_RESET = 0,
parameter [0:0] RX_POWER_DOWN_OVR = 0,
parameter [0:0] RX_POWER_DOWN_N = 0,
parameter [0:0] RX_RESET_OVR = 0,
parameter [0:0] RX_RESET = 0,
parameter [0:0] RX_PMA_RESET_OVR = 0,
parameter [0:0] RX_PMA_RESET = 0,
parameter [0:0] RX_EQA_RESET_OVR = 0,
parameter [0:0] RX_EQA_RESET = 0,
parameter [0:0] RX_CDR_RESET_OVR = 0,
parameter [0:0] RX_CDR_RESET = 0,
parameter [0:0] RX_PCS_RESET_OVR = 0,
parameter [0:0] RX_PCS_RESET = 0,
parameter [0:0] RX_BUF_RESET_OVR = 0,
parameter [0:0] RX_BUF_RESET = 0,
parameter [0:0] RX_POLARITY_OVR = 0,
parameter [0:0] RX_POLARITY = 0,
parameter [0:0] RX_8B10B_EN_OVR = 0,
parameter [0:0] RX_8B10B_EN = 0,
parameter [7:0] RX_8B10B_BYPASS = 0,
parameter [0:0] RX_BYTE_REALIGN = 0,
parameter [0:0] RX_DBG_EN = 0,
parameter [1:0] RX_DBG_SEL = 0,
parameter [0:0] RX_DBG_MODE = 0,
parameter [5:0] RX_DBG_SRAM_DELAY = 6'h05,
parameter [9:0] RX_DBG_ADDR = 0,
parameter [0:0] RX_DBG_RE = 0,
parameter [0:0] RX_DBG_WE = 0,
parameter [19:0] RX_DBG_DATA = 0,
parameter [4:0] TX_SEL_PRE = 0,
parameter [4:0] TX_SEL_POST = 0,
parameter [4:0] TX_AMP = 15,
parameter [4:0] TX_BRANCH_EN_PRE = 0,
parameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST = 0,
parameter [2:0] TX_TAIL_CASCODE = 4,
parameter [6:0] TX_DC_ENABLE = 63,
parameter [4:0] TX_DC_OFFSET = 0,
parameter [4:0] TX_CM_RAISE = 0,
parameter [4:0] TX_CM_THRESHOLD_0 = 14,
parameter [4:0] TX_CM_THRESHOLD_1 = 16,
parameter [4:0] TX_SEL_PRE_EI = 0,
parameter [4:0] TX_SEL_POST_EI = 0,
parameter [4:0] TX_AMP_EI = 15,
parameter [4:0] TX_BRANCH_EN_PRE_EI = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_EI = 0,
parameter [2:0] TX_TAIL_CASCODE_EI = 4,
parameter [6:0] TX_DC_ENABLE_EI = 63,
parameter [4:0] TX_DC_OFFSET_EI = 0,
parameter [4:0] TX_CM_RAISE_EI = 0,
parameter [4:0] TX_CM_THRESHOLD_0_EI = 14,
parameter [4:0] TX_CM_THRESHOLD_1_EI = 16,
parameter [4:0] TX_SEL_PRE_RXDET = 0,
parameter [4:0] TX_SEL_POST_RXDET = 0,
parameter [4:0] TX_AMP_RXDET = 15,
parameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_RXDET = 0,
parameter [2:0] TX_TAIL_CASCODE_RXDET = 4,
parameter [6:0] TX_DC_ENABLE_RXDET = 63,
parameter [4:0] TX_DC_OFFSET_RXDET = 0,
parameter [4:0] TX_CM_RAISE_RXDET = 0,
parameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14,
parameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16,
parameter [0:0] TX_CALIB_EN = 0,
parameter [0:0] TX_CALIB_OVR = 0,
parameter [3:0] TX_CALIB_VAL = 0,
parameter [7:0] TX_CM_REG_KI = 8'h80,
parameter [0:0] TX_CM_SAR_EN = 0,
parameter [0:0] TX_CM_REG_EN = 1,
parameter [4:0] TX_PMA_RESET_TIME = 3,
parameter [4:0] TX_PCS_RESET_TIME = 3,
parameter [0:0] TX_PCS_RESET_OVR = 0,
parameter [0:0] TX_PCS_RESET = 0,
parameter [0:0] TX_PMA_RESET_OVR = 0,
parameter [0:0] TX_PMA_RESET = 0,
parameter [0:0] TX_RESET_OVR = 0,
parameter [0:0] TX_RESET = 0,
parameter [1:0] TX_PMA_LOOPBACK = 0,
parameter [0:0] TX_PCS_LOOPBACK = 0,
parameter [1:0] TX_DATAPATH_SEL = 3,
parameter [0:0] TX_PRBS_OVR = 0,
parameter [2:0] TX_PRBS_SEL = 0,
parameter [0:0] TX_PRBS_FORCE_ERR = 0,
parameter [0:0] TX_LOOPBACK_OVR = 0,
parameter [0:0] TX_POWER_DOWN_OVR = 0,
parameter [0:0] TX_POWER_DOWN_N = 0,
parameter [0:0] TX_ELEC_IDLE_OVR = 0,
parameter [0:0] TX_ELEC_IDLE = 0,
parameter [0:0] TX_DETECT_RX_OVR = 0,
parameter [0:0] TX_DETECT_RX = 0,
parameter [0:0] TX_POLARITY_OVR = 0,
parameter [0:0] TX_POLARITY = 0,
parameter [0:0] TX_8B10B_EN_OVR = 0,
parameter [0:0] TX_8B10B_EN = 0,
parameter [0:0] TX_DATA_OVR = 0,
parameter [2:0] TX_DATA_CNT = 0,
parameter [0:0] TX_DATA_VALID = 0,
parameter [0:0] PLL_EN_ADPLL_CTRL = 0,
parameter [0:0] PLL_CONFIG_SEL = 0,
parameter [0:0] PLL_SET_OP_LOCK = 0,
parameter [0:0] PLL_ENFORCE_LOCK = 0,
parameter [0:0] PLL_DISABLE_LOCK = 0,
parameter [0:0] PLL_LOCK_WINDOW = 1,
parameter [0:0] PLL_FAST_LOCK = 1,
parameter [0:0] PLL_SYNC_BYPASS = 0,
parameter [0:0] PLL_PFD_SELECT = 0,
parameter [0:0] PLL_REF_BYPASS = 0,
parameter [0:0] PLL_REF_SEL = 0,
parameter [0:0] PLL_REF_RTERM = 1,
parameter [5:0] PLL_FCNTRL = 58,
parameter [5:0] PLL_MAIN_DIVSEL = 27,
parameter [1:0] PLL_OUT_DIVSEL = 0,
parameter [4:0] PLL_CI = 3,
parameter [9:0] PLL_CP = 80,
parameter [3:0] PLL_AO = 0,
parameter [2:0] PLL_SCAP = 0,
parameter [1:0] PLL_FILTER_SHIFT = 2,
parameter [2:0] PLL_SAR_LIMIT = 2,
parameter [10:0] PLL_FT = 512,
parameter [0:0] PLL_OPEN_LOOP = 0,
parameter [0:0] PLL_SCAP_AUTO_CAL = 1,
parameter [2:0] PLL_BISC_MODE = 4,
parameter [3:0] PLL_BISC_TIMER_MAX = 15,
parameter [0:0] PLL_BISC_OPT_DET_IND = 0,
parameter [0:0] PLL_BISC_PFD_SEL = 0,
parameter [0:0] PLL_BISC_DLY_DIR = 0,
parameter [2:0] PLL_BISC_COR_DLY = 1,
parameter [0:0] PLL_BISC_CAL_SIGN = 0,
parameter [0:0] PLL_BISC_CAL_AUTO = 1,
parameter [4:0] PLL_BISC_CP_MIN = 4,
parameter [4:0] PLL_BISC_CP_MAX = 18,
parameter [4:0] PLL_BISC_CP_START = 12,
parameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,
parameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,
parameter [0:0] SERDES_ENABLE = 0,
parameter [0:0] SERDES_AUTO_INIT = 0,
parameter [0:0] SERDES_TESTMODE = 0
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWER_DOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input TX_CLK_I,
input RX_CLK_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWER_DOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input REGFILE_CLK_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output TX_DETECT_RX_DONE_O,
output TX_DETECT_RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESET_DONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESET_DONE_O,
output RX_EI_EN_O,
output RX_CLK_O,
output PLL_CLK_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule
(* blackbox *) (* keep *)
module CC_USR_RSTN (
output USR_RSTN
);
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module CC_PLL #(
parameter REF_CLK = "", // e.g. "10.0"
parameter OUT_CLK = "", // e.g. "50.0"
parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED
parameter LOCK_REQ = 1,
parameter CLK270_DOUB = 0,
parameter CLK180_DOUB = 0,
parameter LOW_JITTER = 1,
parameter CI_FILTER_CONST = 2,
parameter CP_FILTER_CONST = 4
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *)
module CC_PLL_ADV #(
parameter [95:0] PLL_CFG_A = 96'bx,
parameter [95:0] PLL_CFG_B = 96'bx
)(
input CLK_REF, CLK_FEEDBACK, USR_CLK_REF,
input USR_LOCKED_STDY_RST, USR_SEL_A_B,
output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED,
output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT
);
endmodule
(* blackbox *) (* keep *)
module CC_SERDES #(
parameter [4:0] RX_BUF_RESET_TIME = 3,
parameter [4:0] RX_PCS_RESET_TIME = 3,
parameter [4:0] RX_RESET_TIMER_PRESC = 0,
parameter [0:0] RX_RESET_DONE_GATE = 0,
parameter [4:0] RX_CDR_RESET_TIME = 3,
parameter [4:0] RX_EQA_RESET_TIME = 3,
parameter [4:0] RX_PMA_RESET_TIME = 3,
parameter [0:0] RX_WAIT_CDR_LOCK = 1,
parameter [0:0] RX_CALIB_EN = 0,
parameter [0:0] RX_CALIB_OVR = 0,
parameter [3:0] RX_CALIB_VAL = 0,
parameter [2:0] RX_RTERM_VCMSEL = 4,
parameter [0:0] RX_RTERM_PD = 0,
parameter [7:0] RX_EQA_CKP_LF = 8'hA3,
parameter [7:0] RX_EQA_CKP_HF = 8'hA3,
parameter [7:0] RX_EQA_CKP_OFFSET = 8'h01,
parameter [0:0] RX_EN_EQA = 0,
parameter [3:0] RX_EQA_LOCK_CFG = 0,
parameter [4:0] RX_TH_MON1 = 8,
parameter [3:0] RX_EN_EQA_EXT_VALUE = 0,
parameter [4:0] RX_TH_MON2 = 8,
parameter [4:0] RX_TAPW = 8,
parameter [4:0] RX_AFE_OFFSET = 8,
parameter [15:0] RX_EQA_CONFIG = 16'h01C0,
parameter [4:0] RX_AFE_PEAK = 16,
parameter [3:0] RX_AFE_GAIN = 8,
parameter [2:0] RX_AFE_VCMSEL = 4,
parameter [7:0] RX_CDR_CKP = 8'hF8,
parameter [7:0] RX_CDR_CKI = 0,
parameter [6:0] RX_CDR_TRANS_TH = 7'h08,
parameter [7:0] RX_CDR_LOCK_CFG = 8'hD5,
parameter [14:0] RX_CDR_FREQ_ACC = 0,
parameter [15:0] RX_CDR_PHASE_ACC = 0,
parameter [1:0] RX_CDR_SET_ACC_CONFIG = 0,
parameter [0:0] RX_CDR_FORCE_LOCK = 0,
parameter [9:0] RX_ALIGN_MCOMMA_VALUE = 10'h283,
parameter [0:0] RX_MCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_MCOMMA_ALIGN = 0,
parameter [9:0] RX_ALIGN_PCOMMA_VALUE = 10'h17C,
parameter [0:0] RX_PCOMMA_ALIGN_OVR = 0,
parameter [0:0] RX_PCOMMA_ALIGN = 0,
parameter [1:0] RX_ALIGN_COMMA_WORD = 0,
parameter [9:0] RX_ALIGN_COMMA_ENABLE = 10'h3FF,
parameter [1:0] RX_SLIDE_MODE = 0,
parameter [0:0] RX_COMMA_DETECT_EN_OVR = 0,
parameter [0:0] RX_COMMA_DETECT_EN = 0,
parameter [1:0] RX_SLIDE = 0,
parameter [0:0] RX_EYE_MEAS_EN = 0,
parameter [14:0] RX_EYE_MEAS_CFG = 0,
parameter [5:0] RX_MON_PH_OFFSET = 0,
parameter [3:0] RX_EI_BIAS = 0,
parameter [3:0] RX_EI_BW_SEL = 4,
parameter [0:0] RX_EN_EI_DETECTOR_OVR = 0,
parameter [0:0] RX_EN_EI_DETECTOR = 0,
parameter [0:0] RX_DATA_SEL = 0,
parameter [0:0] RX_BUF_BYPASS = 0,
parameter [0:0] RX_CLKCOR_USE = 0,
parameter [5:0] RX_CLKCOR_MIN_LAT = 32,
parameter [5:0] RX_CLKCOR_MAX_LAT = 39,
parameter [9:0] RX_CLKCOR_SEQ_1_0 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_1 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_2 = 10'h1F7,
parameter [9:0] RX_CLKCOR_SEQ_1_3 = 10'h1F7,
parameter [0:0] RX_PMA_LOOPBACK = 0,
parameter [0:0] RX_PCS_LOOPBACK = 0,
parameter [1:0] RX_DATAPATH_SEL = 3,
parameter [0:0] RX_PRBS_OVR = 0,
parameter [2:0] RX_PRBS_SEL = 0,
parameter [0:0] RX_LOOPBACK_OVR = 0,
parameter [0:0] RX_PRBS_CNT_RESET = 0,
parameter [0:0] RX_POWER_DOWN_OVR = 0,
parameter [0:0] RX_POWER_DOWN_N = 0,
parameter [0:0] RX_RESET_OVR = 0,
parameter [0:0] RX_RESET = 0,
parameter [0:0] RX_PMA_RESET_OVR = 0,
parameter [0:0] RX_PMA_RESET = 0,
parameter [0:0] RX_EQA_RESET_OVR = 0,
parameter [0:0] RX_EQA_RESET = 0,
parameter [0:0] RX_CDR_RESET_OVR = 0,
parameter [0:0] RX_CDR_RESET = 0,
parameter [0:0] RX_PCS_RESET_OVR = 0,
parameter [0:0] RX_PCS_RESET = 0,
parameter [0:0] RX_BUF_RESET_OVR = 0,
parameter [0:0] RX_BUF_RESET = 0,
parameter [0:0] RX_POLARITY_OVR = 0,
parameter [0:0] RX_POLARITY = 0,
parameter [0:0] RX_8B10B_EN_OVR = 0,
parameter [0:0] RX_8B10B_EN = 0,
parameter [7:0] RX_8B10B_BYPASS = 0,
parameter [0:0] RX_BYTE_REALIGN = 0,
parameter [0:0] RX_DBG_EN = 0,
parameter [1:0] RX_DBG_SEL = 0,
parameter [0:0] RX_DBG_MODE = 0,
parameter [5:0] RX_DBG_SRAM_DELAY = 6'h05,
parameter [9:0] RX_DBG_ADDR = 0,
parameter [0:0] RX_DBG_RE = 0,
parameter [0:0] RX_DBG_WE = 0,
parameter [19:0] RX_DBG_DATA = 0,
parameter [4:0] TX_SEL_PRE = 0,
parameter [4:0] TX_SEL_POST = 0,
parameter [4:0] TX_AMP = 15,
parameter [4:0] TX_BRANCH_EN_PRE = 0,
parameter [5:0] TX_BRANCH_EN_MAIN = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST = 0,
parameter [2:0] TX_TAIL_CASCODE = 4,
parameter [6:0] TX_DC_ENABLE = 63,
parameter [4:0] TX_DC_OFFSET = 0,
parameter [4:0] TX_CM_RAISE = 0,
parameter [4:0] TX_CM_THRESHOLD_0 = 14,
parameter [4:0] TX_CM_THRESHOLD_1 = 16,
parameter [4:0] TX_SEL_PRE_EI = 0,
parameter [4:0] TX_SEL_POST_EI = 0,
parameter [4:0] TX_AMP_EI = 15,
parameter [4:0] TX_BRANCH_EN_PRE_EI = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_EI = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_EI = 0,
parameter [2:0] TX_TAIL_CASCODE_EI = 4,
parameter [6:0] TX_DC_ENABLE_EI = 63,
parameter [4:0] TX_DC_OFFSET_EI = 0,
parameter [4:0] TX_CM_RAISE_EI = 0,
parameter [4:0] TX_CM_THRESHOLD_0_EI = 14,
parameter [4:0] TX_CM_THRESHOLD_1_EI = 16,
parameter [4:0] TX_SEL_PRE_RXDET = 0,
parameter [4:0] TX_SEL_POST_RXDET = 0,
parameter [4:0] TX_AMP_RXDET = 15,
parameter [4:0] TX_BRANCH_EN_PRE_RXDET = 0,
parameter [5:0] TX_BRANCH_EN_MAIN_RXDET = 6'h3F,
parameter [4:0] TX_BRANCH_EN_POST_RXDET = 0,
parameter [2:0] TX_TAIL_CASCODE_RXDET = 4,
parameter [6:0] TX_DC_ENABLE_RXDET = 63,
parameter [4:0] TX_DC_OFFSET_RXDET = 0,
parameter [4:0] TX_CM_RAISE_RXDET = 0,
parameter [4:0] TX_CM_THRESHOLD_0_RXDET = 14,
parameter [4:0] TX_CM_THRESHOLD_1_RXDET = 16,
parameter [0:0] TX_CALIB_EN = 0,
parameter [0:0] TX_CALIB_OVR = 0,
parameter [3:0] TX_CALIB_VAL = 0,
parameter [7:0] TX_CM_REG_KI = 8'h80,
parameter [0:0] TX_CM_SAR_EN = 0,
parameter [0:0] TX_CM_REG_EN = 1,
parameter [4:0] TX_PMA_RESET_TIME = 3,
parameter [4:0] TX_PCS_RESET_TIME = 3,
parameter [0:0] TX_PCS_RESET_OVR = 0,
parameter [0:0] TX_PCS_RESET = 0,
parameter [0:0] TX_PMA_RESET_OVR = 0,
parameter [0:0] TX_PMA_RESET = 0,
parameter [0:0] TX_RESET_OVR = 0,
parameter [0:0] TX_RESET = 0,
parameter [1:0] TX_PMA_LOOPBACK = 0,
parameter [0:0] TX_PCS_LOOPBACK = 0,
parameter [1:0] TX_DATAPATH_SEL = 3,
parameter [0:0] TX_PRBS_OVR = 0,
parameter [2:0] TX_PRBS_SEL = 0,
parameter [0:0] TX_PRBS_FORCE_ERR = 0,
parameter [0:0] TX_LOOPBACK_OVR = 0,
parameter [0:0] TX_POWER_DOWN_OVR = 0,
parameter [0:0] TX_POWER_DOWN_N = 0,
parameter [0:0] TX_ELEC_IDLE_OVR = 0,
parameter [0:0] TX_ELEC_IDLE = 0,
parameter [0:0] TX_DETECT_RX_OVR = 0,
parameter [0:0] TX_DETECT_RX = 0,
parameter [0:0] TX_POLARITY_OVR = 0,
parameter [0:0] TX_POLARITY = 0,
parameter [0:0] TX_8B10B_EN_OVR = 0,
parameter [0:0] TX_8B10B_EN = 0,
parameter [0:0] TX_DATA_OVR = 0,
parameter [2:0] TX_DATA_CNT = 0,
parameter [0:0] TX_DATA_VALID = 0,
parameter [0:0] PLL_EN_ADPLL_CTRL = 0,
parameter [0:0] PLL_CONFIG_SEL = 0,
parameter [0:0] PLL_SET_OP_LOCK = 0,
parameter [0:0] PLL_ENFORCE_LOCK = 0,
parameter [0:0] PLL_DISABLE_LOCK = 0,
parameter [0:0] PLL_LOCK_WINDOW = 1,
parameter [0:0] PLL_FAST_LOCK = 1,
parameter [0:0] PLL_SYNC_BYPASS = 0,
parameter [0:0] PLL_PFD_SELECT = 0,
parameter [0:0] PLL_REF_BYPASS = 0,
parameter [0:0] PLL_REF_SEL = 0,
parameter [0:0] PLL_REF_RTERM = 1,
parameter [5:0] PLL_FCNTRL = 58,
parameter [5:0] PLL_MAIN_DIVSEL = 27,
parameter [1:0] PLL_OUT_DIVSEL = 0,
parameter [4:0] PLL_CI = 3,
parameter [9:0] PLL_CP = 80,
parameter [3:0] PLL_AO = 0,
parameter [2:0] PLL_SCAP = 0,
parameter [1:0] PLL_FILTER_SHIFT = 2,
parameter [2:0] PLL_SAR_LIMIT = 2,
parameter [10:0] PLL_FT = 512,
parameter [0:0] PLL_OPEN_LOOP = 0,
parameter [0:0] PLL_SCAP_AUTO_CAL = 1,
parameter [2:0] PLL_BISC_MODE = 4,
parameter [3:0] PLL_BISC_TIMER_MAX = 15,
parameter [0:0] PLL_BISC_OPT_DET_IND = 0,
parameter [0:0] PLL_BISC_PFD_SEL = 0,
parameter [0:0] PLL_BISC_DLY_DIR = 0,
parameter [2:0] PLL_BISC_COR_DLY = 1,
parameter [0:0] PLL_BISC_CAL_SIGN = 0,
parameter [0:0] PLL_BISC_CAL_AUTO = 1,
parameter [4:0] PLL_BISC_CP_MIN = 4,
parameter [4:0] PLL_BISC_CP_MAX = 18,
parameter [4:0] PLL_BISC_CP_START = 12,
parameter [4:0] PLL_BISC_DLY_PFD_MON_REF = 0,
parameter [4:0] PLL_BISC_DLY_PFD_MON_DIV = 2,
parameter [0:0] SERDES_ENABLE = 0,
parameter [0:0] SERDES_AUTO_INIT = 0,
parameter [0:0] SERDES_TESTMODE = 0
)(
input [63:0] TX_DATA_I,
input TX_RESET_I,
input TX_PCS_RESET_I,
input TX_PMA_RESET_I,
input PLL_RESET_I,
input TX_POWER_DOWN_N_I,
input TX_POLARITY_I,
input [2:0] TX_PRBS_SEL_I,
input TX_PRBS_FORCE_ERR_I,
input TX_8B10B_EN_I,
input [7:0] TX_8B10B_BYPASS_I,
input [7:0] TX_CHAR_IS_K_I,
input [7:0] TX_CHAR_DISPMODE_I,
input [7:0] TX_CHAR_DISPVAL_I,
input TX_ELEC_IDLE_I,
input TX_DETECT_RX_I,
input [2:0] LOOPBACK_I,
input TX_CLK_I,
input RX_CLK_I,
input RX_RESET_I,
input RX_PMA_RESET_I,
input RX_EQA_RESET_I,
input RX_CDR_RESET_I,
input RX_PCS_RESET_I,
input RX_BUF_RESET_I,
input RX_POWER_DOWN_N_I,
input RX_POLARITY_I,
input [2:0] RX_PRBS_SEL_I,
input RX_PRBS_CNT_RESET_I,
input RX_8B10B_EN_I,
input [7:0] RX_8B10B_BYPASS_I,
input RX_EN_EI_DETECTOR_I,
input RX_COMMA_DETECT_EN_I,
input RX_SLIDE_I,
input RX_MCOMMA_ALIGN_I,
input RX_PCOMMA_ALIGN_I,
input REGFILE_CLK_I,
input REGFILE_WE_I,
input REGFILE_EN_I,
input [7:0] REGFILE_ADDR_I,
input [15:0] REGFILE_DI_I,
input [15:0] REGFILE_MASK_I,
output [63:0] RX_DATA_O,
output [7:0] RX_NOT_IN_TABLE_O,
output [7:0] RX_CHAR_IS_COMMA_O,
output [7:0] RX_CHAR_IS_K_O,
output [7:0] RX_DISP_ERR_O,
output TX_DETECT_RX_DONE_O,
output TX_DETECT_RX_PRESENT_O,
output TX_BUF_ERR_O,
output TX_RESET_DONE_O,
output RX_PRBS_ERR_O,
output RX_BUF_ERR_O,
output RX_BYTE_IS_ALIGNED_O,
output RX_BYTE_REALIGN_O,
output RX_RESET_DONE_O,
output RX_EI_EN_O,
output RX_CLK_O,
output PLL_CLK_O,
output [15:0] REGFILE_DO_O,
output REGFILE_RDY_O
);
endmodule
(* blackbox *) (* keep *)
module CC_CFG_CTRL(
input [7:0] DATA,
input CLK,
input EN,
input RECFG,
input VALID
);
endmodule
(* blackbox *) (* keep *)
module CC_USR_RSTN (
output USR_RSTN
);
endmodule

3684
techlibs/gatemate/cells_sim.v
View file

File diff suppressed because it is too large Load diff

3
techlibs/gatemate/gatemate_foldinv.cc
View file

@ -211,9 +211,8 @@ struct GatemateFoldInvPass : public Pass {
for (Module *module : design->selected_modules()) {
FoldInvWorker worker(module);
worker();
}
}
}
} GatemateFoldInvPass;
PRIVATE_NAMESPACE_END

90
techlibs/gatemate/lut_map.v
View file

@ -1,45 +1,45 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
CC_LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]));
end
else if (WIDTH == 2) begin
CC_LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]));
end
else if (WIDTH == 3) begin
CC_LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]));
end
else if (WIDTH == 4) begin
CC_LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end
else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule

112
techlibs/gatemate/mux_map.v
View file

@ -1,56 +1,56 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
CC_MX8 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.D4(E), .D5(F), .D6(G), .D7(H),
.S0(S), .S1(T), .S2(U),
.Y(Y)
);
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
CC_MX4 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.S0(S), .S1(T),
.Y(Y)
);
endmodule
/*
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(S),
.Y(Y)
);
endmodule
*/
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
CC_MX8 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.D4(E), .D5(F), .D6(G), .D7(H),
.S0(S), .S1(T), .S2(U),
.Y(Y)
);
endmodule
module \$_MUX4_ (A, B, C, D, S, T, Y);
input A, B, C, D, S, T;
output Y;
CC_MX4 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .D2(C), .D3(D),
.S0(S), .S1(T),
.Y(Y)
);
endmodule
/*
module \$_MUX_ (A, B, S, Y);
input A, B, S;
output Y;
CC_MX2 _TECHMAP_REPLACE_ (
.D0(A), .D1(B), .S0(S),
.Y(Y)
);
endmodule
*/

102
techlibs/gatemate/reg_map.v
View file

@ -1,51 +1,51 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DFF #(
.CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"),
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
module \$_DLATCH_xxx_ (input E, R, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
CC_DLT #(
.G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"),
.INIT(_TECHMAP_WIREINIT_Q_)
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule

780
techlibs/gatemate/synth_gatemate.cc
View file

@ -1,390 +1,390 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthGateMatePass : public ScriptPass
{
SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_gatemate [options]\n");
log("\n");
log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module.\n");
log("\n");
log(" -vlog <file>\n");
log(" write the design to the specified verilog file. Writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). An empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis.\n");
log("\n");
log(" -scopename\n");
log(" create 'scopename' attributes when flattening the netlist.\n");
log("\n");
log(" -nobram\n");
log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
log("\n");
log(" -noaddf\n");
log(" do not use CC_ADDF full adder cells in output netlist.\n");
log("\n");
log(" -nomult\n");
log(" do not use CC_MULT multiplier cells in output netlist.\n");
log("\n");
log(" -nomx8, -nomx4\n");
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
log("\n");
log(" -luttree\n");
log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n");
log(" legacy p_r.\n");
log("\n");
log(" -dff\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -abc_new\n");
log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion.\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, vlog_file, json_file;
bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new;
void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
json_file = "";
noflatten = false;
scopename = false;
nobram = false;
noaddf = false;
nomult = false;
nomx4 = false;
nomx8 = false;
luttree = false;
dff = false;
retime = false;
noiopad = false;
noclkbuf = false;
abc_new = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
vlog_file = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
noflatten = true;
continue;
}
if (args[argidx] == "-scopename") {
scopename = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-noaddf") {
noaddf = true;
continue;
}
if (args[argidx] == "-nomult") {
nomult = true;
continue;
}
if (args[argidx] == "-nomx4") {
nomx4 = true;
continue;
}
if (args[argidx] == "-nomx8") {
nomx8 = true;
continue;
}
if (args[argidx] == "-luttree") {
luttree = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
if (args[argidx] == "-abc_new") {
abc_new = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection()) {
log_cmd_error("This command only operates on fully selected designs!\n");
}
log_header(design, "Executing SYNTH_GATEMATE pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("prepare"))
{
run("proc");
if (!noflatten) {
run("check");
std::string flatten_args = scopename ? " -scopename" : "";
run("flatten" + flatten_args);
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
run("muxpack");
run("share");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
}
if (check_label("map_mult", "(skip if '-nomult')") && !nomult)
{
run("techmap -map +/gatemate/mul_map.v");
}
if (check_label("coarse"))
{
run("alumacc");
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
{
run("memory_libmap -lib +/gatemate/brams.txt");
run("techmap -map +/gatemate/brams_map.v");
}
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
std::string techmap_args = "";
if (!noaddf) {
techmap_args += " -map +/gatemate/arith_map.v";
}
run("techmap -map +/techmap.v " + techmap_args);
run("opt -fast");
if (retime) {
run("abc -dff -D 1", "(only if -retime)");
}
}
if (check_label("map_io", "(skip if '-noiopad')") && !noiopad)
{
run("iopadmap -bits "
"-inpad CC_IBUF Y:I "
"-outpad CC_OBUF A:O "
"-toutpad CC_TOBUF ~T:A:O "
"-tinoutpad CC_IOBUF ~T:Y:A:IO"
);
run("clean");
}
if (check_label("map_regs"))
{
run("opt_clean");
run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("opt_clean");
}
if (check_label("map_muxs"))
{
std::string muxcover_args;
if (!nomx4) {
muxcover_args += stringf(" -mux4");
}
if (!nomx8) {
muxcover_args += stringf(" -mux8");
}
run("muxcover " + muxcover_args);
run("opt -full");
run("simplemap");
run("techmap -map +/gatemate/mux_map.v");
}
if (check_label("map_luts"))
{
if (luttree || help_mode) {
std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib";
if (dff) {
abc_args += " -dff";
}
if (abc_new) {
run("abc_new " + abc_args, "(with -luttree and -abc_new)");
} else {
run("abc " + abc_args, "(with -luttree, without -abc_new)");
}
run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
run("gatemate_foldinv", "(with -luttree)");
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
}
if (!luttree || help_mode) {
std::string abc_args = " -dress -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(without -luttree)");
}
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/gatemate/lut_map.v");
run("clean");
}
if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf)
{
run("clkbufmap -buf CC_BUFG O:I");
run("clean");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat -width");
run("check -noinit");
run("blackbox =A:whitebox");
}
if (check_label("vlog"))
{
run("opt_clean -purge");
if (!vlog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file));
}
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode) {
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
}
} SynthGateMatePass;
PRIVATE_NAMESPACE_END
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/register.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"
#include "kernel/log.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthGateMatePass : public ScriptPass
{
SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" synth_gatemate [options]\n");
log("\n");
log("This command runs synthesis for Cologne Chip AG GateMate FPGAs.\n");
log("\n");
log(" -top <module>\n");
log(" use the specified module as top module.\n");
log("\n");
log(" -vlog <file>\n");
log(" write the design to the specified verilog file. Writing of an output\n");
log(" file is omitted if this parameter is not specified.\n");
log("\n");
log(" -json <file>\n");
log(" write the design to the specified JSON file. Writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). An empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
log(" synonymous to the end of the command list.\n");
log("\n");
log(" -noflatten\n");
log(" do not flatten design before synthesis.\n");
log("\n");
log(" -scopename\n");
log(" create 'scopename' attributes when flattening the netlist.\n");
log("\n");
log(" -nobram\n");
log(" do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.\n");
log("\n");
log(" -noaddf\n");
log(" do not use CC_ADDF full adder cells in output netlist.\n");
log("\n");
log(" -nomult\n");
log(" do not use CC_MULT multiplier cells in output netlist.\n");
log("\n");
log(" -nomx8, -nomx4\n");
log(" do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
log("\n");
log(" -luttree\n");
log(" use LUT tree mapping for output to nextpnr. Do not use this if targeting\n");
log(" legacy p_r.\n");
log("\n");
log(" -dff\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -retime\n");
log(" run 'abc' with '-dff -D 1' options\n");
log("\n");
log(" -abc_new\n");
log(" use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n");
log("\n");
log(" -noiopad\n");
log(" disable I/O buffer insertion (useful for hierarchical or \n");
log(" out-of-context flows).\n");
log("\n");
log(" -noclkbuf\n");
log(" disable automatic clock buffer insertion.\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
help_script();
log("\n");
}
string top_opt, vlog_file, json_file;
bool noflatten, scopename, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new;
void clear_flags() override
{
top_opt = "-auto-top";
vlog_file = "";
json_file = "";
noflatten = false;
scopename = false;
nobram = false;
noaddf = false;
nomult = false;
nomx4 = false;
nomx8 = false;
luttree = false;
dff = false;
retime = false;
noiopad = false;
noclkbuf = false;
abc_new = false;
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
string run_from, run_to;
clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_opt = "-top " + args[++argidx];
continue;
}
if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
vlog_file = args[++argidx];
continue;
}
if (args[argidx] == "-json" && argidx+1 < args.size()) {
json_file = args[++argidx];
continue;
}
if (args[argidx] == "-run" && argidx+1 < args.size()) {
size_t pos = args[argidx+1].find(':');
if (pos == std::string::npos)
break;
run_from = args[++argidx].substr(0, pos);
run_to = args[argidx].substr(pos+1);
continue;
}
if (args[argidx] == "-noflatten") {
noflatten = true;
continue;
}
if (args[argidx] == "-scopename") {
scopename = true;
continue;
}
if (args[argidx] == "-nobram") {
nobram = true;
continue;
}
if (args[argidx] == "-noaddf") {
noaddf = true;
continue;
}
if (args[argidx] == "-nomult") {
nomult = true;
continue;
}
if (args[argidx] == "-nomx4") {
nomx4 = true;
continue;
}
if (args[argidx] == "-nomx8") {
nomx8 = true;
continue;
}
if (args[argidx] == "-luttree") {
luttree = true;
continue;
}
if (args[argidx] == "-dff") {
dff = true;
continue;
}
if (args[argidx] == "-retime") {
retime = true;
continue;
}
if (args[argidx] == "-noiopad") {
noiopad = true;
continue;
}
if (args[argidx] == "-noclkbuf") {
noclkbuf = true;
continue;
}
if (args[argidx] == "-abc_new") {
abc_new = true;
continue;
}
break;
}
extra_args(args, argidx, design);
if (!design->full_selection()) {
log_cmd_error("This command only operates on fully selected designs!\n");
}
log_header(design, "Executing SYNTH_GATEMATE pass.\n");
log_push();
run_script(design, run_from, run_to);
log_pop();
}
void script() override
{
if (check_label("begin"))
{
run("read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
}
if (check_label("prepare"))
{
run("proc");
if (!noflatten) {
run("check");
std::string flatten_args = scopename ? " -scopename" : "";
run("flatten" + flatten_args);
}
run("tribuf -logic");
run("deminout");
run("opt_expr");
run("opt_clean");
run("check");
run("opt -nodffe -nosdff");
run("fsm");
run("opt");
run("wreduce");
run("peepopt");
run("opt_clean");
run("muxpack");
run("share");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
run("opt_clean");
}
if (check_label("map_mult", "(skip if '-nomult')") && !nomult)
{
run("techmap -map +/gatemate/mul_map.v");
}
if (check_label("coarse"))
{
run("alumacc");
run("opt");
run("memory -nomap");
run("opt_clean");
}
if (check_label("map_bram", "(skip if '-nobram')") && !nobram)
{
run("memory_libmap -lib +/gatemate/brams.txt");
run("techmap -map +/gatemate/brams_map.v");
}
if (check_label("map_ffram"))
{
run("opt -fast -mux_undef -undriven -fine");
run("memory_map");
run("opt -undriven -fine");
}
if (check_label("map_gates"))
{
std::string techmap_args = "";
if (!noaddf) {
techmap_args += " -map +/gatemate/arith_map.v";
}
run("techmap -map +/techmap.v " + techmap_args);
run("opt -fast");
if (retime) {
run("abc -dff -D 1", "(only if -retime)");
}
}
if (check_label("map_io", "(skip if '-noiopad')") && !noiopad)
{
run("iopadmap -bits "
"-inpad CC_IBUF Y:I "
"-outpad CC_OBUF A:O "
"-toutpad CC_TOBUF ~T:A:O "
"-tinoutpad CC_IOBUF ~T:Y:A:IO"
);
run("clean");
}
if (check_label("map_regs"))
{
run("opt_clean");
run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01");
run("techmap -map +/gatemate/reg_map.v");
run("opt_expr -mux_undef");
run("simplemap");
run("opt_clean");
}
if (check_label("map_muxs"))
{
std::string muxcover_args;
if (!nomx4) {
muxcover_args += stringf(" -mux4");
}
if (!nomx8) {
muxcover_args += stringf(" -mux8");
}
run("muxcover " + muxcover_args);
run("opt -full");
run("simplemap");
run("techmap -map +/gatemate/mux_map.v");
}
if (check_label("map_luts"))
{
if (luttree || help_mode) {
std::string abc_args = " -genlib +/gatemate/lut_tree_cells.genlib";
if (dff) {
abc_args += " -dff";
}
if (abc_new) {
run("abc_new " + abc_args, "(with -luttree and -abc_new)");
} else {
run("abc " + abc_args, "(with -luttree, without -abc_new)");
}
run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
run("gatemate_foldinv", "(with -luttree)");
run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
}
if (!luttree || help_mode) {
std::string abc_args = " -dress -lut 4";
if (dff) {
abc_args += " -dff";
}
run("abc " + abc_args, "(without -luttree)");
}
run("clean");
}
if (check_label("map_cells"))
{
run("techmap -map +/gatemate/lut_map.v");
run("clean");
}
if (check_label("map_bufg", "(skip if '-noclkbuf')") && !noclkbuf)
{
run("clkbufmap -buf CC_BUFG O:I");
run("clean");
}
if (check_label("check"))
{
run("hierarchy -check");
run("stat -width");
run("check -noinit");
run("blackbox =A:whitebox");
}
if (check_label("vlog"))
{
run("opt_clean -purge");
if (!vlog_file.empty() || help_mode) {
run(stringf("write_verilog -noattr %s", help_mode ? "<file-name>" : vlog_file));
}
}
if (check_label("json"))
{
if (!json_file.empty() || help_mode) {
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file));
}
}
}
} SynthGateMatePass;
PRIVATE_NAMESPACE_END

1
techlibs/gowin/adc.v
View file

@ -257,4 +257,3 @@ module ADCA (
parameter CSR_OFFSET = -12'd1180; // Parameter 2, signed number, temperature mode - 1560~- 760, typical value - 1180; Voltage mode - 410~410, typical value 0
endmodule

1
techlibs/gowin/arith_map.v
View file

@ -64,4 +64,3 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
end endgenerate
assign X = AA ^ BB ^ {Y_WIDTH{BI}};
endmodule

26
techlibs/gowin/cells_sim.v
View file

@ -25,7 +25,7 @@ module LUT3(output F, input I0, I1, I2);
(I0 => F) = (1054, 1486);
(I1 => F) = (867, 1184);
(I2 => F) = (555, 902);
endspecify
endspecify
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign F = I0 ? s1[1] : s1[0];
@ -39,7 +39,7 @@ module LUT4(output F, input I0, I1, I2, I3);
(I1 => F) = (1053, 1583);
(I2 => F) = (867, 1184);
(I3 => F) = (555, 902);
endspecify
endspecify
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
@ -54,7 +54,7 @@ module __APICULA_LUT5(output F, input I0, I1, I2, I3, M0);
(I2 => F) = (995, 1371);
(I3 => F) = (808, 1116);
(M0 => F) = (486, 680);
endspecify
endspecify
endmodule
(* abc9_lut=4 *)
@ -66,7 +66,7 @@ module __APICULA_LUT6(output F, input I0, I1, I2, I3, M0, M1);
(I3 => F) = (808 + 136, 1116 + 255);
(M0 => F) = (486 + 136, 680 + 255);
(M1 => F) = (478, 723);
endspecify
endspecify
endmodule
(* abc9_lut=8 *)
@ -79,7 +79,7 @@ module __APICULA_LUT7(output F, input I0, I1, I2, I3, M0, M1, M2);
(M0 => F) = (486 + 136 + 136, 680 + 255 + 255);
(M1 => F) = (478 + 136, 723 + 255);
(M2 => F) = (478, 723);
endspecify
endspecify
endmodule
(* abc9_lut=16 *)
@ -93,7 +93,7 @@ module __APICULA_LUT8(output F, input I0, I1, I2, I3, M0, M1, M2, M3);
(M1 => F) = (478 + 136 + 136, 723 + 255 + 255);
(M2 => F) = (478 + 136, 723 + 255);
(M3 => F) = (478, 723);
endspecify
endspecify
endmodule
module MUX2 (O, I0, I1, S0);
@ -212,7 +212,7 @@ module DFFS (output reg Q, input D, CLK, SET);
if (SET)
Q <= 1'b1;
else
Q <= D;
Q <= D;
end
endmodule // DFFS (positive clock edge; synchronous set)
@ -388,7 +388,7 @@ endmodule // DFFNE (negative clock edge; clock enable)
module DFFNS (output reg Q, input D, CLK, SET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
(negedge CLK => (Q : D)) = (480, 660);
$setup(D, negedge CLK, 576);
@ -399,7 +399,7 @@ module DFFNS (output reg Q, input D, CLK, SET);
if (SET)
Q <= 1'b1;
else
Q <= D;
Q <= D;
end
endmodule // DFFNS (negative clock edge; synchronous set)
@ -485,7 +485,7 @@ endmodule // DFFNP (negative clock edge; asynchronous preset)
module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
parameter [0:0] INIT = 1'b1;
initial Q = INIT;
specify
if (CE) (negedge CLK => (Q : D)) = (480, 660);
(PRESET => Q) = (1800, 2679);
@ -793,7 +793,7 @@ module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q);
parameter LSREN = "true";
endmodule
module OSER16(D15, D14, D13, D12, D11, D10,
module OSER16(D15, D14, D13, D12, D11, D10,
D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK,
RESET, Q);
output Q;
@ -918,7 +918,7 @@ RESET, CALIB, D);
parameter LSREN = "true";
endmodule
module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
module IDES16(Q15, Q14, Q13, Q12, Q11, Q10,
Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
RESET, CALIB, D);
input D;
@ -2151,5 +2151,3 @@ module EMCU (
);
endmodule

1
techlibs/gowin/cells_xtra.py
View file

@ -103,4 +103,3 @@ if __name__ == '__main__':
with open(f'adc.v', 'r') as fin:
for l in fin:
fout.write(l);

228
techlibs/gowin/cells_xtra_gw1n.v
View file

@ -36,7 +36,7 @@ endmodule
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
input SETN;
@ -47,9 +47,9 @@ endmodule
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
input D, CLK, RESET, MCLK;
output LAG, LEAD;
endmodule
@ -63,10 +63,10 @@ endmodule
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -132,9 +132,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [31:0] DO;
@ -142,11 +142,11 @@ endmodule
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -211,9 +211,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [35:0] DO;
@ -221,9 +221,9 @@ endmodule
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -289,18 +289,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [31:0] DO;
endmodule
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -365,20 +365,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [35:0] DO;
endmodule
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -444,8 +444,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSELA, BLKSELB;
@ -454,13 +454,13 @@ endmodule
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -525,8 +525,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [35:0] DI;
@ -535,15 +535,15 @@ endmodule
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -609,9 +609,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [15:0] DIA, DIB;
@ -620,16 +620,16 @@ endmodule
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -694,9 +694,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [17:0] DIA, DIB;
input [2:0] BLKSELA, BLKSELB;
@ -712,11 +712,11 @@ input CE,CLK,RESET;
input [17:0] SI,SBI;
output [17:0] SO,SBO;
output [17:0] DOUT;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -728,11 +728,11 @@ input CE,CLK,RESET;
input [8:0] SI,SBI;
output [8:0] SO,SBO;
output [8:0] DOUT;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -752,8 +752,8 @@ parameter OUT_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
@ -773,7 +773,7 @@ parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
@ -791,7 +791,7 @@ parameter OUT1_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
@ -814,9 +814,9 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
@ -836,7 +836,7 @@ input ACCLOAD;
output [53:0] DOUT;
output [54:0] CASO;
output [17:0] SOA, SOB;
parameter A0REG = 1'b0;
parameter A0REG = 1'b0;
parameter A1REG = 1'b0;
parameter B0REG = 1'b0;
parameter B1REG = 1'b0;
@ -851,7 +851,7 @@ parameter ACCLOAD_REG1 = 1'b0;
parameter BSIGN0_REG = 1'b0;
parameter BSIGN1_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
@ -875,12 +875,12 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
parameter PIPE_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
@ -891,13 +891,13 @@ input [54:0] CASI;
input CLK, CE, RESET;
output [53:0] DOUT;
output [54:0] CASO;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
@ -918,41 +918,41 @@ endmodule
module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
input CLKIN;
input CLKFB;
input RESET;
input RESET_P;
input RESET;
input RESET_P;
input RESET_I;
input RESET_S;
input [5:0] FBDSEL;
input [5:0] FBDSEL;
input [5:0] IDSEL;
input [5:0] ODSEL;
input [3:0] PSDA,FDLY;
input [3:0] PSDA,FDLY;
input [3:0] DUTYDA;
output CLKOUT;
output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0";
parameter FCLKIN = "100.0";
parameter DYN_IDIV_SEL= "false";
parameter IDIV_SEL = 0;
parameter IDIV_SEL = 0;
parameter DYN_FBDIV_SEL= "false";
parameter FBDIV_SEL = 0;
parameter FBDIV_SEL = 0;
parameter DYN_ODIV_SEL= "false";
parameter ODIV_SEL = 8;
parameter ODIV_SEL = 8;
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false";
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW1N-4";
endmodule
@ -1034,8 +1034,8 @@ input HCLKIN;
input RESETN;
input CALIB;
output CLKOUT;
parameter DIV_MODE = "2";
parameter GSREN = "false";
parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN(CLKIN, CE, CLKOUT);
@ -1049,9 +1049,9 @@ input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
output CLKOUT;
output FLAG;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT);
@ -1084,7 +1084,7 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule
module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
@ -1113,7 +1113,7 @@ module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
parameter DCS_MODE = "RISING";
endmodule
module DQCE(CLKIN, CE, CLKOUT);
@ -1123,7 +1123,7 @@ output CLKOUT;
endmodule
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule
@ -1153,7 +1153,7 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule
module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
@ -1175,5 +1175,5 @@ parameter IDLE = 4'd0,
PRO_S4 = 4'd9,
PRO_S5 = 4'd10,
RD_S1 = 4'd11,
RD_S2 = 4'd12;
RD_S2 = 4'd12;
endmodule

266
techlibs/gowin/cells_xtra_gw2a.v
View file

@ -36,8 +36,8 @@ endmodule
module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -47,10 +47,10 @@ endmodule
module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1;
input TX, PCLK, TCLK, RESET;
output Q0, Q1;
@ -58,8 +58,8 @@ endmodule
module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -69,8 +69,8 @@ endmodule
module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
parameter GSREN = "false";
parameter LSREN = "true";
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -80,11 +80,11 @@ endmodule
module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1, D2, D3;
input TX0, TX1;
input PCLK, FCLK, TCLK, RESET;
@ -93,11 +93,11 @@ endmodule
module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1, D2, D3, D4, D5, D6, D7;
input TX0, TX1, TX2, TX3;
input PCLK, FCLK, TCLK, RESET;
@ -106,7 +106,7 @@ endmodule
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
input SETN;
@ -117,9 +117,9 @@ endmodule
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
input D, CLK, RESET, MCLK;
output LAG, LEAD;
endmodule
@ -133,10 +133,10 @@ endmodule
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -202,9 +202,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [31:0] DO;
@ -212,11 +212,11 @@ endmodule
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -281,9 +281,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input WRE;
input OCE;
input RESET;
input WRE;
input [13:0] AD;
input [2:0] BLKSEL;
output [35:0] DO;
@ -291,9 +291,9 @@ endmodule
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -359,18 +359,18 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [31:0] DO;
endmodule
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -435,20 +435,20 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLK, CE;
input OCE;
input RESET;
input OCE;
input RESET;
input [13:0] AD;
output [35:0] DO;
endmodule
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -514,8 +514,8 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [31:0] DI;
input [2:0] BLKSELA, BLKSELB;
@ -524,13 +524,13 @@ endmodule
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -595,8 +595,8 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCE;
input RESETA, RESETB;
input OCE;
input RESETA, RESETB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [35:0] DI;
@ -605,15 +605,15 @@ endmodule
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 16;
parameter BIT_WIDTH_1 = 16;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@ -679,9 +679,9 @@ parameter INIT_RAM_3D = 256'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [2:0] BLKSELA, BLKSELB;
input [15:0] DIA, DIB;
@ -690,16 +690,16 @@ endmodule
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
parameter WRITE_MODE1 = 2'b00;
parameter BIT_WIDTH_0 = 18;
parameter BIT_WIDTH_1 = 18;
parameter BLK_SEL_0 = 3'b000;
parameter BLK_SEL_1 = 3'b000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter RESET_MODE = "SYNC";
parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
@ -764,9 +764,9 @@ parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000
parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000;
input CLKA, CEA, CLKB, CEB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input OCEA, OCEB;
input RESETA, RESETB;
input WREA, WREB;
input [13:0] ADA, ADB;
input [17:0] DIA, DIB;
input [2:0] BLKSELA, BLKSELB;
@ -782,11 +782,11 @@ input CE,CLK,RESET;
input [17:0] SI,SBI;
output [17:0] SO,SBO;
output [17:0] DOUT;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -798,11 +798,11 @@ input CE,CLK,RESET;
input [8:0] SI,SBI;
output [8:0] SO,SBO;
output [8:0] DOUT;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ADD_SUB = 1'b0;
parameter PADD_RESET_MODE = "SYNC";
parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
@ -822,8 +822,8 @@ parameter OUT_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
@ -843,7 +843,7 @@ parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
@ -861,7 +861,7 @@ parameter OUT1_REG = 1'b0;
parameter PIPE_REG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
@ -884,9 +884,9 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
@ -906,7 +906,7 @@ input ACCLOAD;
output [53:0] DOUT;
output [54:0] CASO;
output [17:0] SOA, SOB;
parameter A0REG = 1'b0;
parameter A0REG = 1'b0;
parameter A1REG = 1'b0;
parameter B0REG = 1'b0;
parameter B1REG = 1'b0;
@ -921,7 +921,7 @@ parameter ACCLOAD_REG1 = 1'b0;
parameter BSIGN0_REG = 1'b0;
parameter BSIGN1_REG = 1'b0;
parameter SOA_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
@ -945,12 +945,12 @@ parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG0 = 1'b0;
parameter ACCLOAD_REG1 = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
parameter MULT_RESET_MODE = "SYNC";
parameter PIPE_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
@ -961,13 +961,13 @@ input [54:0] CASI;
input CLK, CE, RESET;
output [53:0] DOUT;
output [54:0] CASO;
parameter AREG = 1'b0;
parameter AREG = 1'b0;
parameter BREG = 1'b0;
parameter ASIGN_REG = 1'b0;
parameter BSIGN_REG = 1'b0;
parameter ACCLOAD_REG = 1'b0;
parameter OUT_REG = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter B_ADD_SUB = 1'b0;
parameter C_ADD_SUB = 1'b0;
parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
@ -1002,27 +1002,27 @@ output LOCK;
output CLKOUTP;
output CLKOUTD;
output CLKOUTD3;
parameter FCLKIN = "100.0";
parameter FCLKIN = "100.0";
parameter DYN_IDIV_SEL= "false";
parameter IDIV_SEL = 0;
parameter IDIV_SEL = 0;
parameter DYN_FBDIV_SEL= "false";
parameter FBDIV_SEL = 0;
parameter FBDIV_SEL = 0;
parameter DYN_ODIV_SEL= "false";
parameter ODIV_SEL = 8;
parameter ODIV_SEL = 8;
parameter PSDA_SEL= "0000";
parameter DYN_DA_EN = "false";
parameter DUTYDA_SEL= "1000";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter CLKOUT_FT_DIR = 1'b1;
parameter CLKOUTP_FT_DIR = 1'b1;
parameter CLKOUT_DLY_STEP = 0;
parameter CLKOUTP_DLY_STEP = 0;
parameter CLKFB_SEL = "internal";
parameter CLKOUT_BYPASS = "false";
parameter CLKOUTP_BYPASS = "false";
parameter CLKOUTD_BYPASS = "false";
parameter DYN_SDIV_SEL = 2;
parameter CLKOUTD_SRC = "CLKOUT";
parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW2A-18";
endmodule
@ -1063,8 +1063,8 @@ input HCLKIN;
input RESETN;
input CALIB;
output CLKOUT;
parameter DIV_MODE = "2";
parameter GSREN = "false";
parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN(CLKIN, CE, CLKOUT);
@ -1080,14 +1080,14 @@ input [2:0] RCLKSEL;
input [7:0] DLLSTEP;
input [7:0] WSTEP;
input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
output DQSR90, DQSW0, DQSW270;
output DQSR90, DQSW0, DQSW270;
output [2:0] RPOINT, WPOINT;
output RVALID,RBURST, RFLAG, WFLAG;
parameter FIFO_MODE_SEL = 1'b0;
parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
parameter GSREN = "false";
parameter FIFO_MODE_SEL = 1'b0;
parameter RD_PNTR = 3'b000;
parameter DQS_MODE = "X1";
parameter HWL = "false";
parameter GSREN = "false";
endmodule
module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
@ -1096,16 +1096,16 @@ input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
output CLKOUT;
output FLAG;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
parameter DLL_INSEL = 1'b1;
parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
parameter DCS_MODE = "RISING";
endmodule
module DQCE(CLKIN, CE, CLKOUT);
@ -1115,7 +1115,7 @@ output CLKOUT;
endmodule
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule

1837
techlibs/gowin/cells_xtra_gw5a.v
View file

File diff suppressed because it is too large Load diff

1
techlibs/ice40/arith_map.v
View file

@ -72,4 +72,3 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
assign X = AA ^ BB;
endmodule

4
techlibs/ice40/ice40_dsp.pmg
View file

@ -33,7 +33,7 @@ code sigA sigB sigH
return sig.extract(0, i);
};
auto unextend_unsigned = [](const SigSpec &sig) {
int i;
int i;
for (i = GetSize(sig)-1; i > 0; i--)
if (sig[i] != SigBit(State::S0))
break;
@ -61,7 +61,7 @@ code sigA sigB sigH
if (i == 0)
reject;
for (int j = 0, wire_width = 0; j <= i; j++)
for (int j = 0, wire_width = 0; j <= i; j++)
if (nusers(O[j]) == 0)
wire_width++;
else {

1
techlibs/ice40/tests/test_bram.sh
View file

@ -16,4 +16,3 @@ for dbits in 2 4 8 16 24 32; do
if grep -H ERROR ${id}_tb.txt; then false; fi
done; done
echo OK

1
techlibs/intel/CMakeLists.txt
View file

@ -40,6 +40,7 @@ yosys_pass(synth_intel
max10/cells_sim.v
max10/cells_map.v
max10/dsp_map.v
cyclone10lp/cells_sim.v
cyclone10lp/cells_map.v

1
techlibs/intel/common/brams_map_m9k.v
View file

@ -90,4 +90,3 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.addressstall_b(1'b0));
endmodule

2
techlibs/intel/cyclone10lp/cells_map.v
View file

@ -71,5 +71,3 @@ module \$lut (A, Y);
endgenerate
endmodule

2
techlibs/intel/cycloneiv/cells_map.v
View file

@ -55,5 +55,3 @@ module \$lut (A, Y);
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

2
techlibs/intel/cycloneiv/cells_sim.v
View file

@ -295,5 +295,3 @@ module cycloneiv_pll
output icdrclk;
endmodule // cycloneive_pll

2
techlibs/intel/cycloneive/cells_map.v
View file

@ -71,5 +71,3 @@ module \$lut (A, Y);
endgenerate
endmodule

2
techlibs/intel/max10/cells_map.v
View file

@ -55,5 +55,3 @@ module \$lut (A, Y);
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule //

1
techlibs/intel/max10/dsp_map.v
View file

@ -70,4 +70,3 @@ module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
.dataout (Y)
);
endmodule

3
techlibs/intel/synth_intel.cc
View file

@ -176,6 +176,9 @@ struct SynthIntelPass : public ScriptPass {
family_opt != "cyclone10lp")
log_cmd_error("Invalid or no family specified: '%s'\n", family_opt);
if (family_opt != "max10")
nodsp = true;
log_header(design, "Executing SYNTH_INTEL pass.\n");
log_push();

4
techlibs/intel_alm/common/abc9_map.v
View file

@ -1,5 +1,5 @@
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-clear as boxes, this is because ABC9
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-clear as boxes, this is because ABC9
// doesn't support asynchronous-clear flops in sequential synthesis.
module MISTRAL_FF(

2
techlibs/intel_alm/common/lutram_mlab.txt
View file

@ -15,4 +15,4 @@ endbram
match MISTRAL_MLAB
min efficiency 5
make_outreg
endmatch
endmatch

82
techlibs/intel_alm/common/megafunction_bb.v
View file

@ -12,81 +12,81 @@ module altera_pll
parameter operation_mode = "internal feedback",
parameter deserialization_factor = 4,
parameter data_rate = 0,
parameter sim_additional_refclk_cycles_to_lock = 0,
parameter output_clock_frequency0 = "0 ps",
parameter phase_shift0 = "0 ps",
parameter duty_cycle0 = 50,
parameter output_clock_frequency1 = "0 ps",
parameter phase_shift1 = "0 ps",
parameter duty_cycle1 = 50,
parameter output_clock_frequency2 = "0 ps",
parameter phase_shift2 = "0 ps",
parameter duty_cycle2 = 50,
parameter output_clock_frequency3 = "0 ps",
parameter phase_shift3 = "0 ps",
parameter duty_cycle3 = 50,
parameter output_clock_frequency4 = "0 ps",
parameter phase_shift4 = "0 ps",
parameter duty_cycle4 = 50,
parameter output_clock_frequency5 = "0 ps",
parameter phase_shift5 = "0 ps",
parameter duty_cycle5 = 50,
parameter output_clock_frequency6 = "0 ps",
parameter phase_shift6 = "0 ps",
parameter duty_cycle6 = 50,
parameter output_clock_frequency7 = "0 ps",
parameter phase_shift7 = "0 ps",
parameter duty_cycle7 = 50,
parameter output_clock_frequency8 = "0 ps",
parameter phase_shift8 = "0 ps",
parameter duty_cycle8 = 50,
parameter output_clock_frequency9 = "0 ps",
parameter phase_shift9 = "0 ps",
parameter duty_cycle9 = 50,
parameter duty_cycle9 = 50,
parameter output_clock_frequency10 = "0 ps",
parameter phase_shift10 = "0 ps",
parameter duty_cycle10 = 50,
parameter output_clock_frequency11 = "0 ps",
parameter phase_shift11 = "0 ps",
parameter duty_cycle11 = 50,
parameter output_clock_frequency12 = "0 ps",
parameter phase_shift12 = "0 ps",
parameter duty_cycle12 = 50,
parameter output_clock_frequency13 = "0 ps",
parameter phase_shift13 = "0 ps",
parameter duty_cycle13 = 50,
parameter output_clock_frequency14 = "0 ps",
parameter phase_shift14 = "0 ps",
parameter duty_cycle14 = 50,
parameter output_clock_frequency15 = "0 ps",
parameter phase_shift15 = "0 ps",
parameter duty_cycle15 = 50,
parameter output_clock_frequency16 = "0 ps",
parameter phase_shift16 = "0 ps",
parameter duty_cycle16 = 50,
parameter output_clock_frequency17 = "0 ps",
parameter phase_shift17 = "0 ps",
parameter duty_cycle17 = 50,
parameter clock_name_0 = "",
parameter clock_name_1 = "",
parameter clock_name_2 = "",
@ -115,126 +115,126 @@ module altera_pll
parameter n_cnt_lo_div = 1,
parameter n_cnt_bypass_en = "false",
parameter n_cnt_odd_div_duty_en = "false",
parameter c_cnt_hi_div0 = 1,
parameter c_cnt_hi_div0 = 1,
parameter c_cnt_lo_div0 = 1,
parameter c_cnt_bypass_en0 = "false",
parameter c_cnt_in_src0 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en0 = "false",
parameter c_cnt_prst0 = 1,
parameter c_cnt_ph_mux_prst0 = 0,
parameter c_cnt_hi_div1 = 1,
parameter c_cnt_hi_div1 = 1,
parameter c_cnt_lo_div1 = 1,
parameter c_cnt_bypass_en1 = "false",
parameter c_cnt_in_src1 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en1 = "false",
parameter c_cnt_prst1 = 1,
parameter c_cnt_ph_mux_prst1 = 0,
parameter c_cnt_hi_div2 = 1,
parameter c_cnt_hi_div2 = 1,
parameter c_cnt_lo_div2 = 1,
parameter c_cnt_bypass_en2 = "false",
parameter c_cnt_in_src2 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en2 = "false",
parameter c_cnt_prst2 = 1,
parameter c_cnt_ph_mux_prst2 = 0,
parameter c_cnt_hi_div3 = 1,
parameter c_cnt_hi_div3 = 1,
parameter c_cnt_lo_div3 = 1,
parameter c_cnt_bypass_en3 = "false",
parameter c_cnt_in_src3 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en3 = "false",
parameter c_cnt_prst3 = 1,
parameter c_cnt_ph_mux_prst3 = 0,
parameter c_cnt_hi_div4 = 1,
parameter c_cnt_hi_div4 = 1,
parameter c_cnt_lo_div4 = 1,
parameter c_cnt_bypass_en4 = "false",
parameter c_cnt_in_src4 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en4 = "false",
parameter c_cnt_prst4 = 1,
parameter c_cnt_ph_mux_prst4 = 0,
parameter c_cnt_hi_div5 = 1,
parameter c_cnt_hi_div5 = 1,
parameter c_cnt_lo_div5 = 1,
parameter c_cnt_bypass_en5 = "false",
parameter c_cnt_in_src5 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en5 = "false",
parameter c_cnt_prst5 = 1,
parameter c_cnt_ph_mux_prst5 = 0,
parameter c_cnt_hi_div6 = 1,
parameter c_cnt_hi_div6 = 1,
parameter c_cnt_lo_div6 = 1,
parameter c_cnt_bypass_en6 = "false",
parameter c_cnt_in_src6 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en6 = "false",
parameter c_cnt_prst6 = 1,
parameter c_cnt_ph_mux_prst6 = 0,
parameter c_cnt_hi_div7 = 1,
parameter c_cnt_hi_div7 = 1,
parameter c_cnt_lo_div7 = 1,
parameter c_cnt_bypass_en7 = "false",
parameter c_cnt_in_src7 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en7 = "false",
parameter c_cnt_prst7 = 1,
parameter c_cnt_ph_mux_prst7 = 0,
parameter c_cnt_hi_div8 = 1,
parameter c_cnt_hi_div8 = 1,
parameter c_cnt_lo_div8 = 1,
parameter c_cnt_bypass_en8 = "false",
parameter c_cnt_in_src8 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en8 = "false",
parameter c_cnt_prst8 = 1,
parameter c_cnt_ph_mux_prst8 = 0,
parameter c_cnt_hi_div9 = 1,
parameter c_cnt_hi_div9 = 1,
parameter c_cnt_lo_div9 = 1,
parameter c_cnt_bypass_en9 = "false",
parameter c_cnt_in_src9 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en9 = "false",
parameter c_cnt_prst9 = 1,
parameter c_cnt_ph_mux_prst9 = 0,
parameter c_cnt_hi_div10 = 1,
parameter c_cnt_hi_div10 = 1,
parameter c_cnt_lo_div10 = 1,
parameter c_cnt_bypass_en10 = "false",
parameter c_cnt_in_src10 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en10 = "false",
parameter c_cnt_prst10 = 1,
parameter c_cnt_ph_mux_prst10 = 0,
parameter c_cnt_hi_div11 = 1,
parameter c_cnt_hi_div11 = 1,
parameter c_cnt_lo_div11 = 1,
parameter c_cnt_bypass_en11 = "false",
parameter c_cnt_in_src11 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en11 = "false",
parameter c_cnt_prst11 = 1,
parameter c_cnt_ph_mux_prst11 = 0,
parameter c_cnt_hi_div12 = 1,
parameter c_cnt_hi_div12 = 1,
parameter c_cnt_lo_div12 = 1,
parameter c_cnt_bypass_en12 = "false",
parameter c_cnt_in_src12 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en12 = "false",
parameter c_cnt_prst12 = 1,
parameter c_cnt_ph_mux_prst12 = 0,
parameter c_cnt_hi_div13 = 1,
parameter c_cnt_hi_div13 = 1,
parameter c_cnt_lo_div13 = 1,
parameter c_cnt_bypass_en13 = "false",
parameter c_cnt_in_src13 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en13 = "false",
parameter c_cnt_prst13 = 1,
parameter c_cnt_ph_mux_prst13 = 0,
parameter c_cnt_hi_div14 = 1,
parameter c_cnt_hi_div14 = 1,
parameter c_cnt_lo_div14 = 1,
parameter c_cnt_bypass_en14 = "false",
parameter c_cnt_in_src14 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en14 = "false",
parameter c_cnt_prst14 = 1,
parameter c_cnt_ph_mux_prst14 = 0,
parameter c_cnt_hi_div15 = 1,
parameter c_cnt_hi_div15 = 1,
parameter c_cnt_lo_div15 = 1,
parameter c_cnt_bypass_en15 = "false",
parameter c_cnt_in_src15 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en15 = "false",
parameter c_cnt_prst15 = 1,
parameter c_cnt_ph_mux_prst15 = 0,
parameter c_cnt_hi_div16 = 1,
parameter c_cnt_hi_div16 = 1,
parameter c_cnt_lo_div16 = 1,
parameter c_cnt_bypass_en16 = "false",
parameter c_cnt_in_src16 = "ph_mux_clk",
parameter c_cnt_odd_div_duty_en16 = "false",
parameter c_cnt_prst16 = 1,
parameter c_cnt_ph_mux_prst16 = 0,
parameter c_cnt_hi_div17 = 1,
parameter c_cnt_hi_div17 = 1,
parameter c_cnt_lo_div17 = 1,
parameter c_cnt_bypass_en17 = "false",
parameter c_cnt_in_src17 = "ph_mux_clk",
@ -260,9 +260,9 @@ module altera_pll
parameter pll_clkin_1_src = "clk_0",
parameter pll_clk_loss_sw_en = "false",
parameter pll_auto_clk_sw_en = "false",
parameter pll_manu_clk_sw_en = "false",
parameter pll_manu_clk_sw_en = "false",
parameter pll_clk_sw_dly = 0,
parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
parameter pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
parameter pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss"
) (
//input
@ -279,7 +279,7 @@ module altera_pll
input extswitch,
input adjpllin,
input cclk,
//output
output [ number_of_clocks -1 : 0] outclk,
output fboutclk,

2
techlibs/intel_alm/common/misc_sim.v
View file

@ -18,4 +18,4 @@ module MISTRAL_CLKBUF (
(* clkbuf_driver *) output Q
);
assign Q = A;
endmodule
endmodule

1
techlibs/lattice/cells_bb_ecp5.v
View file

@ -2030,4 +2030,3 @@ module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_
input D_REFCLKI;
output D_FFS_PLOL;
endmodule

1
techlibs/lattice/cells_bb_nexus.v
View file

@ -10589,4 +10589,3 @@ module PCLKDIVSP(CLKIN, CLKOUT, LSRPDIV);
output CLKOUT;
input LSRPDIV;
endmodule

1
techlibs/lattice/cells_bb_xo2.v
View file

@ -579,4 +579,3 @@ endmodule
module TSALL(TSALL);
input TSALL;
endmodule

1
techlibs/lattice/cells_bb_xo3.v
View file

@ -579,4 +579,3 @@ endmodule
module TSALL(TSALL);
input TSALL;
endmodule

1
techlibs/lattice/cells_bb_xo3d.v
View file

@ -580,4 +580,3 @@ endmodule
module TSALL(TSALL);
input TSALL;
endmodule

4
techlibs/lattice/cells_sim_nexus.v
View file

@ -446,7 +446,7 @@ module OXIDE_DSP_SIM #(
input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,
output wire [Z_WIDTH-1:0] Z
);
localparam M_WIDTH = (A_WIDTH+B_WIDTH);
/******** REGISTERS ********/
@ -511,7 +511,7 @@ module OXIDE_DSP_SIM #(
if (ADDSUB_USED) begin
assign pipe_d = mult_m;
assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
end else begin
assign z_d = mult_m;
end

6
techlibs/lattice/dsp_map_nexus.v
View file

@ -94,10 +94,10 @@ module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [
.REGINPUTC("BYPASS"),
.REGOUTPUT("BYPASS")
) _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.A(A),
.B(B),
.C({6'b0, C}),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.SIGNED(A_SIGNED ? 1'b1 : 1'b0),
.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
.Z(Y)
);

6
techlibs/lattice/lattice_dsp_nexus.cc
View file

@ -25,12 +25,12 @@ struct LatticeDspNexusPass : public Pass {
for (auto module : design->selected_modules()) {
lattice_dsp_nexus_pm pm(module, module->cells());
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac9_4lane();
pm.run_nexus_mac18();
pm.run_nexus_preadd18();
}
}
} LatticeDspNexusPass;
PRIVATE_NAMESPACE_END
PRIVATE_NAMESPACE_END

10
techlibs/lattice/lattice_dsp_nexus.pmg
View file

@ -38,7 +38,7 @@ code
mac->setPort(\B, port(mul, \B));
mac->setPort(\C, port(add, add_C));
mac->setPort(\Y, port(add, \Y));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\A_SIGNED, mul->getParam(\A_SIGNED));
mac->setParam(\SUBTRACT, add->type == $sub ? State::S1 : State::S0);
autoremove(mul);
@ -178,9 +178,9 @@ code
{
Cell *mac = module->addCell(NEW_ID, "$__NX_MAC9X9WIDE_4LANE");
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
auto ext9 = [&](SigSpec s) {
s.extend_u0(9, is_signed);
return s;
};
@ -205,4 +205,4 @@ code
}
accept;
endcode
endcode

4
techlibs/lattice/lattice_gsr.cc
View file

@ -83,12 +83,12 @@ struct LatticeGsrPass : public Pass {
{
if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO")
continue;
bool gsren = found_gsr;
if (cell->get_bool_attribute(ID(nogsr)))
gsren = false;
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
}
if (!found_gsr)

36
techlibs/microchip/LSRAM.txt
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -28,9 +28,9 @@ ram block $__LSRAM_TDP_ {
init any;
# port A and port B are allowed to have different widths, but they MUST have
# WIDTH values of the same set.
# WIDTH values of the same set.
# Example: Port A has a Data Width of 1. Then Port B's Data Width must be either
# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).
# 1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).
# WIDTH_1 = {1, 2, 4, 8, 16}
# WIDTH_2 = {5, 10, 20}
@ -38,7 +38,7 @@ ram block $__LSRAM_TDP_ {
# "byte" must be larger than width, or width must be a multipler of "byte"
# if "byte" > WIDTH, a single enable wire is inferred
# otherwise, WIDTH/byte number of enable wires are inferred
#
#
# WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire
# WIDTH = {16, 20} requires 2 enable wire
@ -58,7 +58,7 @@ ram block $__LSRAM_TDP_ {
byte 8;
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width| Address bits
# 5 | 12
# 10 | 11
@ -72,14 +72,14 @@ ram block $__LSRAM_TDP_ {
widths 5 10 20 per_port;
byte 10;
}
port srsw "A" "B" {
# read & write width must be same
width tied;
# clock polarity is rising
clock posedge;
@ -101,8 +101,8 @@ ram block $__LSRAM_TDP_ {
rdwr no_change;
# Write transparency:
# For write ports, define behaviour when another synchronous read port
# reads from the same memory cell that said write port is writing to at the same time.
# For write ports, define behaviour when another synchronous read port
# reads from the same memory cell that said write port is writing to at the same time.
wrtrans all old;
}
portoption "WRITE_MODE" "WRITE_FIRST" {
@ -123,9 +123,9 @@ ram block $__LSRAM_TDP_ {
# two-port configuration
ram block $__LSRAM_SDP_ {
# since two-port configuration is dedicated for wide-read/write,
# we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs
# we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs
# inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should
# be less than 2 TDP.
cost 129;
@ -147,10 +147,10 @@ ram block $__LSRAM_SDP_ {
# width = 32, byte-write size is 8, ignore other widths
byte 8;
}
option "WIDTH_CONFIG" "ALIGN" {
# Data-Width| Address bits
# 5 | 12
# 10 | 11
@ -166,7 +166,7 @@ ram block $__LSRAM_SDP_ {
port sw "W" {
# only consider wide write
option "WIDTH_CONFIG" "REGULAR" width 32;
option "WIDTH_CONFIG" "ALIGN" width 40;
@ -174,7 +174,7 @@ ram block $__LSRAM_SDP_ {
# only simple write supported for two-port mode
wrtrans all old;
optional;
}
port sr "R" {

16
techlibs/microchip/LSRAM_map.v
View file

@ -71,7 +71,7 @@ parameter PORT_A_WR_USED = 0;
wire [2:0] A_BLK_SEL = (PORT_A_RD_USED == 1 || PORT_A_WR_USED == 1) ? 3'b111 : 3'b000;
wire [2:0] B_BLK_SEL = (PORT_B_RD_USED == 1 || PORT_B_WR_USED == 1) ? 3'b111 : 3'b000;
// wires for write data
// wires for write data
generate
wire [19:0] A_write_data;
wire [19:0] B_write_data;
@ -115,9 +115,9 @@ wire [2:0] B_width = (PORT_B_WIDTH == 1) ? 3'b000 :
(PORT_B_WIDTH == 8 || PORT_B_WIDTH == 10) ? 3'b011 : 3'b100;
// write modes
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
wire [1:0] A_write_mode = PORT_A_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_A_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
wire [1:0] B_write_mode = PORT_B_OPTION_WRITE_MODE == "NO_CHANGE" ? 2'b00 :
PORT_B_OPTION_WRITE_MODE == "WRITE_FIRST" ? 2'b01 : 2'b10;
RAM1K20 #(
@ -155,7 +155,7 @@ RAM1K20 #(
.B_DOUT_ARST_N(1'b1),
// Disable ECC for TDP
.ECC_EN(1'b0),
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
@ -212,7 +212,7 @@ generate
wire [1:0] A_write_EN;
wire [1:0] B_write_EN;
// write port (A provides MSB)
// write port (A provides MSB)
if (PORT_W_WIDTH == 32) begin
assign B_write_data[3:0] = PORT_W_WR_DATA[3:0];
@ -232,7 +232,7 @@ generate
assign A_write_data[9] = 1'b0;
assign A_write_data[14] = 1'b0;
assign A_write_data[19] = 1'b0;
end else if (PORT_W_WIDTH == 40) begin
assign B_write_data = PORT_W_WR_DATA[19:0];
assign A_write_data = PORT_W_WR_DATA[39:20];
@ -265,7 +265,7 @@ endgenerate
wire [2:0] A_width = (PORT_R_WIDTH == 1) ? 3'b000 :
(PORT_R_WIDTH == 2) ? 3'b001 :
(PORT_R_WIDTH == 4 || PORT_R_WIDTH == 5) ? 3'b010 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 8 || PORT_R_WIDTH == 10) ? 3'b011 :
(PORT_R_WIDTH == 16 || PORT_R_WIDTH == 20) ? 3'b100 : 3'b101;
wire [2:0] B_width = (PORT_W_WIDTH == 1) ? 3'b000 :
(PORT_W_WIDTH == 2) ? 3'b001 :
@ -311,7 +311,7 @@ RAM1K20 #(
.B_DOUT_ARST_N(1'b1),
// Disable ECC for SDP
.ECC_EN(1'b0),
.ECC_EN(1'b0),
.ECC_BYPASS(1'b1),
.BUSY_FB(1'b0)
);

3
techlibs/microchip/arith_map.v
View file

@ -48,7 +48,7 @@ module \$__microchip_XOR8_ (A, Y);
XOR8 _TECHMAP_REPLACE_.XOR8 (.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .G(A[6]), .H(A[7]), .Y(Y));
endmodule
(* techmap_celltype = "$alu" *)
@ -102,4 +102,3 @@ module \$__SF2_ALU (A, B, CI, BI, X, Y, CO);
);
end endgenerate
endmodule

2
techlibs/microchip/brams_defs.vh
View file

@ -66,4 +66,4 @@ function [63:0] slice_init_uSRAM;
integer i;
for (i = 0; i < 64; i = i + 1)
slice_init_uSRAM[i] = INIT[(slice_idx * 64 + i)];
endfunction
endfunction

1
techlibs/microchip/cells_map.v
View file

@ -101,4 +101,3 @@ module \$lut (A, Y);
endgenerate
endmodule
`endif

16
techlibs/microchip/cells_sim.v
View file

@ -155,7 +155,7 @@ endmodule
// sequential elements
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
// MICROCHIP_SYNC_SET_DFF and MICROCHIP_SYNC_RESET_DFF are intermediate cell types to implement the simplification idiom for abc9 flow
// see: https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/abc_flow.html
(* abc9_flop, lib_whitebox *)
@ -196,7 +196,7 @@ module MICROCHIP_SYNC_RESET_DFF(
always @(posedge CLK) begin
if (En == 1) begin
if (Reset == 0)
if (Reset == 0)
Q <= 0;
else
Q <= D;
@ -258,7 +258,7 @@ module ARI1 (
(* abc9_carry *)
output FCO,
input A, B, C, D,
input A, B, C, D,
output Y, S
);
parameter [19:0] INIT = 20'h0;
@ -271,9 +271,9 @@ module ARI1 (
wire G = INIT[16] ? (INIT[17] ? F1 : F0) : INIT[17];
wire P = INIT[19] ? 1'b1 : (INIT[18] ? Yout : 1'b0);
assign FCO = P ? FCI : G;
specify
//pin to pin path delay
//pin to pin path delay
(A => Y ) = 472;
(B => Y ) = 407;
(C => Y ) = 238;
@ -647,7 +647,7 @@ module RAM1K20 (
input B_DOUT_EN,
input B_DOUT_SRST_N,
input B_DOUT_ARST_N,
input ECC_EN,
input ECC_EN,
input ECC_BYPASS,
output SB_CORRECT,
output DB_DETECT,
@ -684,7 +684,7 @@ module RAM64x12 (
input R_ADDR_EN,
input R_ADDR_SL_N,
input R_ADDR_SD,
input R_ADDR_AL_N,
input R_ADDR_AL_N,
input R_ADDR_AD_N,
input BLK_EN,
output [11:0] R_DATA,
@ -716,4 +716,4 @@ parameter INIT9 = 64'h0;
parameter INIT10 = 64'h0;
parameter INIT11 = 64'h0;
endmodule
endmodule

24
techlibs/microchip/microchip_dsp.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -16,12 +16,12 @@
// This file describes the main pattern matcher setup (of three total) that
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// ( 1) Starting from a DSP cell. Capture DSP configurations as states
// ( 2) Match for pre-adder
// ( 3) Match for post-adder
// ( 4) Match register 'A', 'B', 'D', 'P'
// ( 4) Match register 'A', 'B', 'D', 'P'
// ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder.
// This indicates an accumulator situation like the ASCII diagram below:
// +--------------------------------+
@ -110,21 +110,21 @@ code bypassA bypassB bypassC bypassD bypassPASUB bypassP
endcode
// (2) Match for pre-adder
//
//
code sigA sigB sigD preAdderStatic moveBtoA
subpattern(preAddMatching);
preAdderStatic = u_preAdderStatic;
moveBtoA = false;
if (preAdderStatic) {
if (port(preAdderStatic, \Y) == sigA)
{
//used for packing
moveBtoA = true;
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
// we basically swap it.
sigA = sigB;
}
@ -144,7 +144,7 @@ code postAdderStatic sigP sigC
if (postAdderStatic) {
//sigC will be whichever input to the postAdder that is NOT from the multiplier
// u_postAddAB is the input to the postAdder from the multiplier
// u_postAddAB is the input to the postAdder from the multiplier
sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A);
sigP = port(postAdderStatic, \Y);
}
@ -269,7 +269,7 @@ code
if (postAdd)
{
if (postAdd->type.in($sub) && postAddAB == \A) {
// if $sub, the multiplier output must match to $sub.B, otherwise no match
// if $sub, the multiplier output must match to $sub.B, otherwise no match
} else {
u_postAddAB = postAddAB;
u_postAdderStatic = postAdd;
@ -286,11 +286,11 @@ endcode
subpattern preAddMatching
arg sigA sigB sigD bypassB bypassD bypassPASUB
code
code
u_preAdderStatic = nullptr;
// Ensure that preAdder not already used
// Assume we can inspect port D to see if its all zeros.
// Assume we can inspect port D to see if its all zeros.
if (!(sigD.empty() || sigD.is_fully_zero())) reject;
if (!bypassB.is_fully_ones()) reject;
if (!bypassD.is_fully_ones()) reject;

6
techlibs/microchip/microchip_dsp_CREG.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -164,5 +164,5 @@ code argQ
argQ = Q;
dffD.replace(argQ, D);
}
endcode

20
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -1,7 +1,7 @@
// ISC License
//
//
// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
@ -18,10 +18,10 @@
// This file describes the third of three pattern matcher setups that
// forms the `microchip_dsp` pass described in microchip_dsp.cc
// At a high level, it works as follows:
// (1) Starting from a DSP cell that
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
// (b) doesn't already use the 'PCOUT' port
// (2) Match another DSP cell that
// (2) Match another DSP cell that
// (a) does not have the CREG enabled,
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
@ -72,7 +72,7 @@ code
};
endcode
// (1) Starting from a DSP cell that
// (1) Starting from a DSP cell that
// (a) CDIN_FDBK_SEL is set to default "00"
// (b) doesn't already use the 'PCOUT' port
match first
@ -133,7 +133,7 @@ finally
{
dsp_pcin->setPort(\ARSHFT17, State::S1);
}
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
@ -154,7 +154,7 @@ subpattern tail
arg first
arg next
// (2) Match another DSP cell that
// (2) Match another DSP cell that
// (a) does not have the CREG enabled,
// (b) 'C' port is driven by the 'P' output of the previous DSP cell
// (c) has its 'PCIN' port unused
@ -213,7 +213,7 @@ code
chain.emplace_back(next, shift);
visited.insert(next);
SigSpec sigC = unextend(port(next, \C));
// Make sure driverDSP.P === DSP.C
@ -231,6 +231,6 @@ finally
visited.erase(next);
chain.pop_back();
}
endcode
endcode

10
techlibs/microchip/polarfire_dsp_map.v
View file

@ -27,9 +27,9 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
// For pin descriptions, see Section 9 of PolarFire FPGA Macro Library Guide:
// https://coredocs.s3.amazonaws.com/Libero/2021_2/Tool/pf_mlg.pdf
MACC_PA _TECHMAP_REPLACE_ (
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.DOTP(1'b0),
.SIMD(1'b0),
.OVFL_CARRYOUT_SEL(1'b0),
.AL_N(1'b1),
.A(A),
@ -47,7 +47,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
.D_ARST_N(1'b1),
.D_SRST_N(1'b1),
.D_EN(1'b1),
.CARRYIN(1'b0),
.C(48'b0),
.C_BYPASS(1'b1),
@ -55,7 +55,7 @@ module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
.C_SRST_N(1'b1),
.C_EN(1'b1),
.P(P_48),
.P_BYPASS(1'b1),

12
techlibs/microchip/uSRAM.txt
View file

@ -1,11 +1,11 @@
# ISC License
#
#
# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@ -30,10 +30,10 @@ ram block $__uSRAM_AR_ {
port sw "W" {
clock posedge;
# collision not supported, but write takes precedence and read data is invalid while writing to
# collision not supported, but write takes precedence and read data is invalid while writing to
# the same address
wrtrans all new;
optional;
}
port ar "R" {
@ -57,7 +57,7 @@ widths 12 per_port;
# collision not supported
wrtrans all new;
optional;
}
port sr "R" {

5
techlibs/microchip/uSRAM_map.v
View file

@ -48,7 +48,7 @@ RAM64x12 #(
.R_ADDR_EN(1'b0),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),
@ -103,7 +103,7 @@ RAM64x12 #(
.R_ADDR_EN(PORT_R_RD_EN),
.R_ADDR_SL_N(1'b1),
.R_ADDR_SD(1'b0),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AL_N(1'b1),
.R_ADDR_AD_N(1'b0),
.BLK_EN(PORT_R_USED ? 1'b1 : 1'b0),
.R_DATA(PORT_R_RD_DATA),
@ -123,4 +123,3 @@ RAM64x12 #(
);
endmodule

2
techlibs/nanoxplore/brams.txt
View file

@ -47,4 +47,4 @@ ram block $__NX_RAM_ {
rdwr no_change;
rdinit none;
}
}
}

2
techlibs/nanoxplore/brams_init.vh
View file

@ -3,7 +3,7 @@ function [409600-1:0] bram_init_to_string;
input integer blocks;
input integer width;
reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
reg [24-1:0] temp2;
reg [24-1:0] temp2;
integer i;
integer j;
begin

1
techlibs/nanoxplore/cells_bb_l.v
View file

@ -2153,4 +2153,3 @@ module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2,
parameter sel_clkw_rx1 = 2'b00;
parameter sel_clkw_rx2 = 2'b00;
endmodule

1
techlibs/nanoxplore/cells_bb_m.v
View file

@ -1524,4 +1524,3 @@ module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG,
parameter data_size = 5;
parameter location = "";
endmodule

8
techlibs/nanoxplore/cells_sim_u.v
View file

@ -172,15 +172,15 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
end
wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28,
O27, O26, O25, O24, O23, O22, O21, O20, O19,
wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28,
O27, O26, O25, O24, O23, O22, O21, O20, O19,
O18, O17, O16, O15, O14, O13, O12, O11, O10,
O9, O8, O7, O6, O5, O4, O3, O2, O1 };
wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28,
I27, I26, I25, I24, I23, I22, I21, I20, I19,
I18, I17, I16, I15, I14, I13, I12, I11, I10,
I9, I8, I7, I6, I5, I4, I3, I2, I1 };
generate
generate
if (mode==0) begin
assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
end
@ -196,7 +196,7 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14
else if (mode==4) begin
assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
end
else
else
$error("Unknown NX_RFB_U mode");
endgenerate

1
techlibs/nanoxplore/cells_wrap.v
View file

@ -198,4 +198,3 @@ module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS
);
endmodule

8
techlibs/nanoxplore/nx_carry.cc
View file

@ -52,7 +52,7 @@ static void nx_carry_chain(Module *module)
{
if (cell->type == ID(NX_CY_1BIT)) {
if (cell->getParam(ID(first)).as_int() == 0) continue;
vector<Cell*> chain;
Cell *current = cell;
chain.push_back(current);
@ -124,8 +124,8 @@ static void nx_carry_chain(Module *module)
}
cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
if (c.second.at(i)->hasPort(ID(S)))
if (c.second.at(i)->hasPort(ID(S)))
cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S)));
j = (j + 1) % 4;
@ -148,7 +148,7 @@ struct NXCarryPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing NX_CARRY pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{

2
techlibs/nanoxplore/rf_rams_map_l.v
View file

@ -2,7 +2,7 @@ module $__NX_RFB_L_ (
input PORT_W_CLK,
input PORT_W_WR_EN,
input [5:0] PORT_W_ADDR,
input [15:0] PORT_W_WR_DATA,
input [15:0] PORT_W_WR_DATA,
input PORT_R_CLK,
input PORT_R_RD_EN,
input [5:0] PORT_R_ADDR,

2
techlibs/nanoxplore/rf_rams_map_m.v
View file

@ -2,7 +2,7 @@ module $__NX_RFB_M_ (
input PORT_W_CLK,
input PORT_W_WR_EN,
input [5:0] PORT_W_ADDR,
input [15:0] PORT_W_WR_DATA,
input [15:0] PORT_W_WR_DATA,
input PORT_R_CLK,
input PORT_R_RD_EN,
input [5:0] PORT_R_ADDR,

2
techlibs/nanoxplore/rf_rams_map_u.v
View file

@ -342,4 +342,4 @@ module $__NX_XRFB_2R_1W_ (
.WE(PORT_W_WR_EN),
.WEA(1'b0)
);
endmodule
endmodule

6
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -1,8 +1,8 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com>
* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
* Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com>
* Copyright (C) 2024 Miodrag Milanovic <micko@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -231,7 +231,7 @@ struct SynthNanoXplorePass : public ScriptPass
postfix = "_m";
} else if (family == "large") {
postfix = "_l";
} else
} else
log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family);
if (!design->full_selection())

4
techlibs/quicklogic/pp3/abc9_map.v
View file

@ -1,5 +1,5 @@
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
// This file exists to map purely-synchronous flops to ABC9 flops, while
// mapping flops with asynchronous-set/clear as boxes, this is because ABC9
// doesn't support asynchronous-set/clear flops in sequential synthesis.
module dffepc (

2
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -180,7 +180,7 @@ struct QlBramMergeWorker {
};
struct QlBramMergePass : public Pass {
QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {}
void help() override

8
techlibs/quicklogic/ql_bram_types.cc
View file

@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
struct QlBramTypesPass : public Pass {
QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {}
void help() override
@ -81,7 +81,7 @@ struct QlBramTypesPass : public Pass {
{
if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS)))
continue;
RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS));
bool split = mode_bits.extract(80).as_bool();
@ -139,7 +139,7 @@ struct QlBramTypesPass : public Pass {
type += "SYNC_";
else
type += "ASYNC_";
} else
} else
type += "_BRAM_";
if (split) {
@ -162,4 +162,4 @@ struct QlBramTypesPass : public Pass {
} QlBramMergePass;
PRIVATE_NAMESPACE_END
PRIVATE_NAMESPACE_END

1
techlibs/quicklogic/qlf_k6n10f/arith_map.v
View file

@ -96,4 +96,3 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
assign X = S;
endmodule

2
techlibs/quicklogic/qlf_k6n10f/brams_map.v
View file

@ -4285,4 +4285,4 @@ module BRAM2x18_AFIFO (
.FLUSH2_i(Async_Flush2)
);
endmodule
endmodule

2
techlibs/quicklogic/qlf_k6n10f/brams_sim.v
View file

@ -10946,4 +10946,4 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split (
endspecify
`endif
endmodule
endmodule

1
techlibs/quicklogic/qlf_k6n10f/cells_sim.v
View file

@ -372,4 +372,3 @@ module latchnsre (
endspecify
endmodule

1
techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v
View file

@ -262,4 +262,3 @@ module dsp_t1_10x9x32_cfg_params (
assign dly_b_o = dly_b_o[8:0];
endmodule

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