Merge branch 'main' into nella/latch-toggle

docs/source/code_examples/fifo/Makefile

@@ -2,7 +2,7 @@ include ../../../common.mk
 
 DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
 DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
-MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates 
+MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
 MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
 
 DOTS := $(addsuffix .dot,$(DOT_NAMES))

docs/source/code_examples/fifo/fifo.v

@@ -1,5 +1,5 @@
 // address generator/counter
-module addr_gen 
+module addr_gen
 #(  parameter MAX_DATA=256,
 	localparam AWIDTH = $clog2(MAX_DATA)
 ) ( input en, clk, rst,
@@ -21,7 +21,7 @@ module addr_gen
 endmodule //addr_gen
 
 // Define our top level fifo entity
-module fifo 
+module fifo
 #(  parameter MAX_DATA=256,
 	localparam AWIDTH = $clog2(MAX_DATA)
 ) ( input wen, ren, clk, rst,

docs/source/code_examples/fifo/fifo.ys

@@ -2,7 +2,7 @@
 # throw in some extra text to match what we expect if we were opening an
 # interactive terminal
 log $ yosys fifo.v
-log 
+log
 log -- Parsing `fifo.v' using frontend ` -vlog2k' --
 read_verilog -defer fifo.v
 

docs/source/code_examples/intro/mycells.v

@@ -20,4 +20,3 @@ output reg Q;
 always @(posedge C)
 	Q <= D;
 endmodule
-

docs/source/code_examples/macc/Makefile

@@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 .PHONY: clean
 clean:
 	@rm -f *.dot
-

docs/source/code_examples/macc/macc_xilinx_test.ys

@@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2
 
 design -load __macc_xilinx_xmap
 show -prefix macc_xilinx_xmap -format dot -notitle
-

docs/source/code_examples/macro_commands/synth_ice40.ys

@@ -54,7 +54,7 @@ map_gates:
     ice40_wrapcarry
     techmap
     opt -fast
-    abc -dff -D 1 
+    abc -dff -D 1
     ice40_opt
 
 map_ffs:
@@ -89,4 +89,3 @@ check:
     stat
     check -noinit
     blackbox =A:whitebox
-        

docs/source/code_examples/opt/opt_expr.ys

@@ -3,7 +3,7 @@ read_verilog <<EOT
 module uut(
     input a,
     output y, z
-);  
+);
     assign y = a == a;
     assign z = a != a;
 endmodule

docs/source/code_examples/opt/opt_merge.ys

@@ -15,4 +15,3 @@ opt_merge after
 clean
 
 show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/opt/opt_muxtree.ys

@@ -3,7 +3,7 @@ read_verilog <<EOT
 module uut(
     input a, b, c, d,
     output y
-);  
+);
     assign y = a ? (a ? b : c) : d;
 endmodule
 
@@ -14,4 +14,3 @@ opt_muxtree after
 clean
 
 show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut
-

docs/source/code_examples/scrambler/scrambler.ys

@@ -19,4 +19,3 @@ eval -set in 1 -show out
 eval -set in 270369 -show out
 
 sat -set out 632435482
-

docs/source/code_examples/show/cmos.ys

@@ -2,7 +2,7 @@
 read_verilog cmos.v
 prep -top cmos_demo
 techmap
-abc -liberty ../intro/mycells.lib;; 
+abc -liberty ../intro/mycells.lib;;
 show -format dot -prefix cmos_00
 
 # reset
@@ -13,5 +13,5 @@ read_verilog cmos.v
 prep -top cmos_demo
 techmap
 splitnets -ports
-abc -liberty ../intro/mycells.lib;; 
+abc -liberty ../intro/mycells.lib;;
 show -lib ../intro/mycells.v -format dot -prefix cmos_01

docs/source/code_examples/synth_flow/Makefile

@@ -17,4 +17,3 @@ examples:
 .PHONY: clean
 clean:
 	@rm -f *.dot
-