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6
docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst
View file

@ -279,9 +279,9 @@ This document was originally published in April 2015:
in line 13 provides a mini synthesis-script to be used to process this cell.
.. code-block:: c
:caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled
using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a
-mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx``
:caption: Test program for the Amber23 CPU (Sieve of Eratosthenes). Compiled
using GCC 4.6.3 for ARM with ``-Os -marm -march=armv2a
-mno-thumb-interwork -ffreestanding``, linked with ``--fix-v4bx``
set and booted with a custom setup routine written in ARM assembler.
:name: sieve

2
docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
View file

@ -18,7 +18,7 @@ be used to convert Verilog designs with simple assertions to BTOR format.
Download
========
This document was originally published in November 2013:
This document was originally published in November 2013:
:download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
..

1
docs/source/appendix/env_vars.rst
View file

@ -29,4 +29,3 @@ Yosys environment variables
``YOSYS_ABORT_ON_LOG_ERROR``
Can be used for debugging Yosys internals. Setting it to 1 causes abort() to
be called when Yosys terminates with an error message.

4
docs/source/appendix/primer.rst
View file

@ -601,7 +601,7 @@ Let's consider the following BNF (in Bison syntax):
:class: width-helper invert-helper
:name: fig:Basics_parsetree
Example parse tree for the Verilog expression
Example parse tree for the Verilog expression
:verilog:`assign foo = bar + 42;`
The parser converts the token list to the parse tree in :numref:`Fig. %s
@ -630,7 +630,7 @@ three-address-code intermediate representation. :cite:p:`Dragonbook`
:class: width-helper invert-helper
:name: fig:Basics_ast
Example abstract syntax tree for the Verilog expression
Example abstract syntax tree for the Verilog expression
:verilog:`assign foo = bar + 42;`

32
docs/source/appendix/rtlil_text.rst
View file

@ -136,11 +136,11 @@ wires, memories, cells, processes, and connections.
<module> ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
<module-stmt> ::= module <id> <eol>
<module-body> ::= (<param-stmt>
<module-body> ::= (<param-stmt>
| <conn-stmt>
| <wire>
| <memory>
| <cell>
| <wire>
| <memory>
| <cell>
| <process>)*
<param-stmt> ::= parameter <id> <constant>? <eol>
<constant> ::= <value> | <integer> | <string>
@ -170,9 +170,9 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.
.. code:: BNF
<sigspec> ::= <constant>
<sigspec> ::= <constant>
| <wire-id>
| <sigspec> [ <integer> (:<integer>)? ]
| <sigspec> [ <integer> (:<integer>)? ]
| { <sigspec>* }
When a ``<wire-id>`` is specified, the wire must have been previously declared.
@ -202,12 +202,12 @@ See :ref:`sec:rtlil_cell_wire` for an overview of wires.
<wire> ::= <attr-stmt>* <wire-stmt>
<wire-stmt> ::= wire <wire-option>* <wire-id> <eol>
<wire-id> ::= <id>
<wire-option> ::= width <integer>
| offset <integer>
| input <integer>
| output <integer>
| inout <integer>
| upto
<wire-option> ::= width <integer>
| offset <integer>
| input <integer>
| output <integer>
| inout <integer>
| upto
| signed
Memories
@ -223,8 +223,8 @@ See :ref:`sec:rtlil_memory` for an overview of memory cells, and
<memory> ::= <attr-stmt>* <memory-stmt>
<memory-stmt> ::= memory <memory-option>* <id> <eol>
<memory-option> ::= width <integer>
| size <integer>
<memory-option> ::= width <integer>
| size <integer>
| offset <integer>
Cells
@ -299,9 +299,9 @@ be:
.. code:: BNF
<sync> ::= <sync-stmt> <update-stmt>*
<sync-stmt> ::= sync <sync-type> <sigspec> <eol>
<sync-stmt> ::= sync <sync-type> <sigspec> <eol>
| sync global <eol>
| sync init <eol>
| sync init <eol>
| sync always <eol>
<sync-type> ::= low | high | posedge | negedge | edge
<update-stmt> ::= update <dest-sigspec> <src-sigspec> <eol>

4
docs/source/cell/word_logic.rst
View file

@ -29,7 +29,7 @@ There are 2 products to be summed, so ``\DEPTH`` shall be 2.
~A[1]---+||
A[1]--+|||
~A[0]-+||||
A[0]+|||||
A[0]+|||||
|||||| product formula
010000 ~\A[0]
001001 \A[1]~\A[2]
@ -43,4 +43,4 @@ values.
.. autocellgroup:: logic
:members:
:source:
:linenos:
:linenos:

6
docs/source/cmd/index_internal.rst
View file

@ -88,7 +88,7 @@ Dumping command help to json
by ``Pass::experimental()``)
* also title (``short_help`` argument in ``Pass::Pass``), group, and class
name
+ dictionary of group name to list of commands in that group
- used by sphinx autodoc to generate help content
@ -106,7 +106,7 @@ Dumping command help to json
code block is formatted as ``yoscrypt`` (e.g. `synth_ice40`). The caveat
here is that if the ``script()`` calls ``run()`` on any commands *prior* to
the first ``check_label`` then the auto detection will break and revert to
unformatted code (e.g. `synth_fabulous`).
unformatted code (e.g. `synth_fabulous`).
Command line rendering
~~~~~~~~~~~~~~~~~~~~~~
@ -114,7 +114,7 @@ Command line rendering
- if ``Pass::formatted_help()`` returns true, will call
``PrettyHelp::log_help()``
+ traverse over the children of the root node and render as plain text
+ traverse over the children of the root node and render as plain text
+ effectively the reverse of converting unformatted ``Pass::help()`` text
+ lines are broken at 80 characters while maintaining indentation (controlled
by ``MAX_LINE_LEN`` in :file:`kernel/log_help.cc`)

2
docs/source/code_examples/fifo/Makefile
View file

@ -2,7 +2,7 @@ include ../../../common.mk
DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean
DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc rdata_coarse
MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
MAPDOT_NAMES = rdata_map_ram rdata_map_ffram rdata_map_gates
MAPDOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells
DOTS := $(addsuffix .dot,$(DOT_NAMES))

4
docs/source/code_examples/fifo/fifo.v
View file

@ -1,5 +1,5 @@
// address generator/counter
module addr_gen
module addr_gen
#( parameter MAX_DATA=256,
localparam AWIDTH = $clog2(MAX_DATA)
) ( input en, clk, rst,
@ -21,7 +21,7 @@ module addr_gen
endmodule //addr_gen
// Define our top level fifo entity
module fifo
module fifo
#( parameter MAX_DATA=256,
localparam AWIDTH = $clog2(MAX_DATA)
) ( input wen, ren, clk, rst,

2
docs/source/code_examples/fifo/fifo.ys
View file

@ -2,7 +2,7 @@
# throw in some extra text to match what we expect if we were opening an
# interactive terminal
log $ yosys fifo.v
log
log
log -- Parsing `fifo.v' using frontend ` -vlog2k' --
read_verilog -defer fifo.v

1
docs/source/code_examples/intro/mycells.v
View file

@ -20,4 +20,3 @@ output reg Q;
always @(posedge C)
Q <= D;
endmodule

1
docs/source/code_examples/macc/Makefile
View file

@ -16,4 +16,3 @@ macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
.PHONY: clean
clean:
@rm -f *.dot

1
docs/source/code_examples/macc/macc_xilinx_test.ys
View file

@ -50,4 +50,3 @@ show -prefix macc_xilinx_test2e -format dot -notitle test2
design -load __macc_xilinx_xmap
show -prefix macc_xilinx_xmap -format dot -notitle

3
docs/source/code_examples/macro_commands/synth_ice40.ys
View file

@ -54,7 +54,7 @@ map_gates:
ice40_wrapcarry
techmap
opt -fast
abc -dff -D 1
abc -dff -D 1
ice40_opt
map_ffs:
@ -89,4 +89,3 @@ check:
stat
check -noinit
blackbox =A:whitebox

2
docs/source/code_examples/opt/opt_expr.ys
View file

@ -3,7 +3,7 @@ read_verilog <<EOT
module uut(
input a,
output y, z
);
);
assign y = a == a;
assign z = a != a;
endmodule

1
docs/source/code_examples/opt/opt_merge.ys
View file

@ -15,4 +15,3 @@ opt_merge after
clean
show -format dot -prefix opt_merge_full -notitle -color cornflowerblue uut

3
docs/source/code_examples/opt/opt_muxtree.ys
View file

@ -3,7 +3,7 @@ read_verilog <<EOT
module uut(
input a, b, c, d,
output y
);
);
assign y = a ? (a ? b : c) : d;
endmodule
@ -14,4 +14,3 @@ opt_muxtree after
clean
show -format dot -prefix opt_muxtree_full -notitle -color cornflowerblue uut

1
docs/source/code_examples/scrambler/scrambler.ys
View file

@ -19,4 +19,3 @@ eval -set in 1 -show out
eval -set in 270369 -show out
sat -set out 632435482

4
docs/source/code_examples/show/cmos.ys
View file

@ -2,7 +2,7 @@
read_verilog cmos.v
prep -top cmos_demo
techmap
abc -liberty ../intro/mycells.lib;;
abc -liberty ../intro/mycells.lib;;
show -format dot -prefix cmos_00
# reset
@ -13,5 +13,5 @@ read_verilog cmos.v
prep -top cmos_demo
techmap
splitnets -ports
abc -liberty ../intro/mycells.lib;;
abc -liberty ../intro/mycells.lib;;
show -lib ../intro/mycells.v -format dot -prefix cmos_01

1
docs/source/code_examples/synth_flow/Makefile
View file

@ -17,4 +17,3 @@ examples:
.PHONY: clean
clean:
@rm -f *.dot

12
docs/source/getting_started/example_synth.rst
View file

@ -199,7 +199,7 @@ opt_expr <adv_opt_expr>`.
.. todo:: consider a brief glossary for terms like adff
.. seealso:: Advanced usage docs for
- :doc:`/using_yosys/synthesis/proc`
- :doc:`/using_yosys/synthesis/opt`
@ -321,7 +321,7 @@ and merged with the ``raddr`` wire feeding into the `$memrd` cell. This wire
merging happened during the call to `clean` which we can see in the
:ref:`flat_clean`.
.. note::
.. note::
`flatten` and `clean` would normally be combined into a
single :yoterm:`yosys> flatten;;` output, but they appear separately here as
@ -394,7 +394,7 @@ highlighted below:
``rdata`` output after `opt_dff`
.. seealso:: Advanced usage docs for
- :doc:`/using_yosys/synthesis/fsm`
- :doc:`/using_yosys/synthesis/opt`
@ -461,7 +461,7 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and
``SRST=1'0``) inputs.
.. seealso:: Advanced usage docs for
- :doc:`/using_yosys/synthesis/opt`
- :doc:`/using_yosys/synthesis/techmap_synth`
- :doc:`/using_yosys/synthesis/memory`
@ -659,7 +659,7 @@ into flip flops (the ``logic fallback``) with `memory_map`.
complex.
.. seealso:: Advanced usage docs for
- :doc:`/using_yosys/synthesis/techmap_synth`
- :doc:`/using_yosys/synthesis/memory`
@ -757,7 +757,7 @@ cells.
``rdata`` output after :ref:`map_cells`
.. seealso:: Advanced usage docs for
- :doc:`/using_yosys/synthesis/techmap_synth`
- :doc:`/using_yosys/synthesis/abc`

2
docs/source/getting_started/installation.rst
View file

@ -152,7 +152,7 @@ Installing all prerequisites:
recommended to use Windows Subsystem for Linux (WSL) and follow the
instructions for Ubuntu.
..
..
tab:: MSYS2 (MINGW64)
.. code:: console

4
docs/source/getting_started/scripting_intro.rst
View file

@ -149,11 +149,11 @@ represent, see :ref:`interactive_show` and the
Calling :yoscrypt:`show addr_gen` after `hierarchy`
.. note::
.. note::
The `show` command requires a working installation of `GraphViz`_ and `xdot`_
for displaying the actual circuit diagrams.
.. _GraphViz: http://www.graphviz.org/
.. _xdot: https://github.com/jrfonseca/xdot.py

22
docs/source/introduction.rst
View file

@ -125,7 +125,7 @@ The first version of the Yosys documentation was published as a bachelor thesis
at the Vienna University of Technology :cite:p:`BACC`.
:Abstract:
Most of today's digital design is done in HDL code (mostly Verilog or
Most of today's digital design is done in HDL code (mostly Verilog or
VHDL) and with the help of HDL synthesis tools.
In special cases such as synthesis for coarse-grain cell libraries or
@ -164,14 +164,14 @@ for specialised tasks.
Benefits of open source HDL synthesis
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Cost (also applies to ``free as in free beer`` solutions):
- Cost (also applies to ``free as in free beer`` solutions):
Today the cost for a mask set in 180nm technology is far less than the cost
for the design tools needed to design the mask layouts. Open Source ASIC flows
are an important enabler for ASIC-level Open Source Hardware.
- Availability and Reproducibility:
- Availability and Reproducibility:
If you are a researcher who is publishing, you want to use tools that everyone
else can also use. Even if most universities have access to all major
commercial tools, you usually do not have easy access to the version that was
@ -179,14 +179,14 @@ Benefits of open source HDL synthesis
can even release the source code of the tool you have used alongside your
data.
- Framework:
- Framework:
Yosys is not only a tool. It is a framework that can be used as basis for
other developments, so researchers and hackers alike do not need to re-invent
the basic functionality. Extensibility was one of Yosys' design goals.
- All-in-one:
- All-in-one:
Because of the framework characteristics of Yosys, an increasing number of
features become available in one tool. Yosys not only can be used for circuit
synthesis but also for formal equivalence checking, SAT solving, and for
@ -194,8 +194,8 @@ Benefits of open source HDL synthesis
proprietary software one needs to learn a new tool for each of these
applications.
- Educational Tool:
- Educational Tool:
Proprietary synthesis tools are at times very secretive about their inner
workings. They often are ``black boxes``. Yosys is very open about its
internals and it is easy to observe the different steps of synthesis.

66
docs/source/literature.bib
View file

@ -66,24 +66,24 @@
year = {1996}
}
@ARTICLE{Verilog2005,
@ARTICLE{Verilog2005,
journal={IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001)},
title={IEEE Standard for Verilog Hardware Description Language},
title={IEEE Standard for Verilog Hardware Description Language},
author={IEEE Standards Association and others},
year={2006},
year={2006},
doi={10.1109/IEEESTD.2006.99495}
}
@ARTICLE{VerilogSynth,
@ARTICLE{VerilogSynth,
journal={IEEE Std 1364.1-2002},
title={IEEE Standard for Verilog Register Transfer Level Synthesis},
title={IEEE Standard for Verilog Register Transfer Level Synthesis},
author={IEEE Standards Association and others},
year={2002},
year={2002},
doi={10.1109/IEEESTD.2002.94220}
}
@ARTICLE{VHDL,
journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)},
journal={IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002)},
title={IEEE Standard VHDL Language Reference Manual},
author={IEEE Standards Association and others},
year={2009},
@ -92,20 +92,20 @@
}
@ARTICLE{VHDLSynth,
journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)},
journal={IEEE Std 1076.6-2004 (Revision of IEEE Std 1076.6-1999)},
title={IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis},
author={IEEE Standards Association and others},
year={2004},
doi={10.1109/IEEESTD.2004.94802}
}
@ARTICLE{IP-XACT,
journal={IEEE Std 1685-2009},
title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
@ARTICLE{IP-XACT,
journal={IEEE Std 1685-2009},
title={IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tools Flows},
author={IEEE Standards Association and others},
year={2010},
pages={C1-360},
keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
year={2010},
pages={C1-360},
keywords={abstraction definitions, address space specification, bus definitions, design environment, EDA, electronic design automation, electronic system level, ESL, implementation constraints, IP-XACT, register transfer level, RTL, SCRs, semantic consistency rules, TGI, tight generator interface, tool and data interoperability, use models, XML design meta-data, XML schema},
doi={10.1109/IEEESTD.2010.5417309}
}
@ -116,7 +116,7 @@
isbn = {0-201-10088-6},
publisher = {Addison-Wesley Longman Publishing Co., Inc.},
address = {Boston, MA, USA}
}
}
@INPROCEEDINGS{Cummings00,
author = {Clifford E. Cummings and Sunburst Design Inc},
@ -132,26 +132,26 @@
year={August 1967}
}
@INPROCEEDINGS{fsmextract,
author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
year={2010},
pages={2610-2613},
keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
@INPROCEEDINGS{fsmextract,
author={Yiqiong Shi and Chan Wai Ting and Bah-Hwee Gwee and Ye Ren},
booktitle={Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on},
title={A highly efficient method for extracting FSMs from flattened gate-level netlist},
year={2010},
pages={2610-2613},
keywords={circuit CAD;finite state machines;microcontrollers;FSM;control-intensive circuits;finite state machines;flattened gate-level netlist;state register elimination technique;Automata;Circuit synthesis;Continuous wavelet transforms;Design automation;Digital circuits;Hardware design languages;Logic;Microcontrollers;Registers;Signal processing},
doi={10.1109/ISCAS.2010.5537093},
}
@ARTICLE{MultiLevelLogicSynth,
author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
journal={Proceedings of the IEEE},
title={Multilevel logic synthesis},
year={1990},
volume={78},
number={2},
pages={264-300},
keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
doi={10.1109/5.52213},
@ARTICLE{MultiLevelLogicSynth,
author={Brayton, R.K. and Hachtel, G.D. and Sangiovanni-Vincentelli, A.L.},
journal={Proceedings of the IEEE},
title={Multilevel logic synthesis},
year={1990},
volume={78},
number={2},
pages={264-300},
keywords={circuit layout CAD;integrated logic circuits;logic CAD;capsule summaries;definitions;detailed analysis;in-depth background;logic decomposition;logic minimisation;logic synthesis;logic synthesis techniques;multilevel combinational logic;multilevel logic synthesis;notation;perspective;survey;synthesis methods;technology mapping;testing;Application specific integrated circuits;Design automation;Integrated circuit synthesis;Logic design;Logic devices;Logic testing;Network synthesis;Programmable logic arrays;Signal synthesis;Silicon},
doi={10.1109/5.52213},
ISSN={0018-9219},
}
@ -171,7 +171,7 @@
acmid = {321925},
publisher = {ACM},
address = {New York, NY, USA},
}
}
@article{een2003temporal,
title={Temporal induction by incremental SAT solving},

2
docs/source/using_yosys/more_scripting/data_flow_tracking.rst
View file

@ -111,4 +111,4 @@ For example, an AND gate will propagate a given tag on one input, if the other
input is either 1 or carries a tag of the same group. So if one input is ``0,
"key:a"`` and the other is ``0, "key:b"`` the result would be ``0, "key:a",
"key:b"``, rather than simply ``0``. Note that if we add an unrelated
``"overflow"`` tag to the first input, it would still not be propagated.
``"overflow"`` tag to the first input, it would still not be propagated.

32
docs/source/using_yosys/more_scripting/interactive_investigation.rst
View file

@ -56,7 +56,7 @@ is shown.
.. figure:: /_images/code_examples/show/example_first.*
:class: width-helper invert-helper
Output of the first `show` command in :numref:`example_ys`
The first output shows the design directly after being read by the Verilog
@ -88,7 +88,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram:
.. figure:: /_images/code_examples/show/example_second.*
:class: width-helper invert-helper
Output of the second `show` command in :numref:`example_ys`
The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
@ -106,14 +106,14 @@ operations, it is therefore recommended to always call `clean` before calling
`show`.
In this script we directly call `opt` as the next step, which finally leads us
to the third diagram:
to the third diagram:
.. figure:: /_images/code_examples/show/example_third.*
:class: width-helper invert-helper
:name: example_out
Output of the third `show` command in :ref:`example_ys`
Here we see that the `opt` command not only has removed the artifacts left
behind by `proc`, but also determined correctly that it can remove the first
`$mux` cell without changing the behavior of the circuit.
@ -167,7 +167,7 @@ mapped to a cell library:
:class: width-helper invert-helper
:name: first_pitfall
A half-adder built from simple CMOS gates, demonstrating common pitfalls when
A half-adder built from simple CMOS gates, demonstrating common pitfalls when
using `show`
.. literalinclude:: /code_examples/show/cmos.ys
@ -176,7 +176,7 @@ mapped to a cell library:
:end-at: cmos_00
:name: pitfall_code
:caption: Generating :numref:`first_pitfall`
First, Yosys did not have access to the cell library when this diagram was
generated, resulting in all cell ports defaulting to being inputs. This is why
all ports are drawn on the left side the cells are awkwardly arranged in a large
@ -248,7 +248,7 @@ command already fails to verify, it is better to troubleshoot the coarse-grain
version of the circuit before `techmap` than the gate-level circuit after
`techmap`.
.. Note::
.. Note::
It is generally recommended to verify the internal state of a design by
writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
@ -327,7 +327,7 @@ tools).
- :cmd:title:`dump`.
- :cmd:title:`add` and :cmd:title:`delete` can be used to modify and reorganize
a design dynamically.
The code used is included in the Yosys code base under
|code_examples/scrambler|_.
@ -438,7 +438,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
.. figure:: /_images/code_examples/selections/memdemo_00.*
:class: width-helper invert-helper
``memdemo``
Because this produces a rather large circuit, it can be useful to split it into
@ -459,18 +459,18 @@ below.
.. figure:: /_images/code_examples/selections/submod_02.*
:class: width-helper invert-helper
``outstage``
.. figure:: /_images/code_examples/selections/submod_03.*
:class: width-helper invert-helper
:name: selstage
``selstage``
.. figure:: /_images/code_examples/selections/submod_01.*
:class: width-helper invert-helper
``scramble``
Evaluation of combinatorial circuits
@ -541,9 +541,9 @@ to solve this kind of problems.
.. _MiniSAT: http://minisat.se/
.. note::
While it is possible to perform model checking directly in Yosys, it
.. note::
While it is possible to perform model checking directly in Yosys, it
is highly recommended to use SBY or EQY for formal hardware verification.
The `sat` command works very similar to the `eval` command. The main difference

2
docs/source/using_yosys/more_scripting/load_design.rst
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@ -81,7 +81,7 @@ Yosys frontends
'Frontend' here means that the command is implemented as a sub-class of
``RTLIL::Frontend``, as opposed to the usual ``RTLIL::Pass``.
.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under
.. todo:: link note to as-yet non-existent section on ``RTLIL::Pass`` under
:doc:`/yosys_internals/extending_yosys/index`
The `read_verilog` command

20
docs/source/using_yosys/more_scripting/selections.rst
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@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar.
If no `select` command has been made, then the "current selection" will be the
whole design.
.. note:: Many of the examples on this page make use of the `show`
command to visually demonstrate the effect of selections. For a more
.. note:: Many of the examples on this page make use of the `show`
command to visually demonstrate the effect of selections. For a more
detailed look at this command, refer to :ref:`interactive_show`.
How to make a selection
@ -106,7 +106,7 @@ glance. When it is called with multiple arguments, each argument is evaluated
and pushed separately on a stack. After all arguments have been processed it
simply creates the union of all elements on the stack. So :yoscrypt:`select
t:$add a:foo` will select all `$add` cells and all objects with the ``foo``
attribute set:
attribute set:
.. literalinclude:: /code_examples/selections/foobaraddsub.v
:caption: Test module for operations on selections
@ -130,7 +130,7 @@ select all `$add` cells that have the ``foo`` attribute set:
.. code-block::
:caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub`
yosys> select t:$add a:foo %i -list
foobaraddsub/$add$foobaraddsub.v:4$1
@ -282,7 +282,7 @@ provided :file:`memdemo.v` is in the same directory. We can now change to the
.. figure:: /_images/code_examples/selections/memdemo_00.*
:class: width-helper invert-helper
:name: memdemo_00
Complete circuit diagram for the design shown in :numref:`memdemo_src`
There's a lot going on there, but maybe we are only interested in the tree of
@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`:
.. figure:: /_images/code_examples/selections/memdemo_01.*
:class: width-helper invert-helper
:name: memdemo_01
Output of :yoscrypt:`show y %ci2`
From this we would learn that ``y`` is driven by a `$dff` cell, that ``y`` is
@ -305,7 +305,7 @@ start of the name). Let's go a bit further now and try :yoscrypt:`show y %ci5`:
.. figure:: /_images/code_examples/selections/memdemo_02.*
:class: width-helper invert-helper
:name: memdemo_02
Output of :yoscrypt:`show y %ci5`
That's starting to get a bit messy, so maybe we want to ignore the mux select
@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`:
.. figure:: /_images/code_examples/selections/memdemo_03.*
:class: width-helper invert-helper
:name: memdemo_03
Output of :yoscrypt:`show y %ci5:-$mux[S]`
We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D]
@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells:
.. figure:: /_images/code_examples/selections/memdemo_05.*
:class: width-helper invert-helper
:name: memdemo_05
Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following
@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``:
.. figure:: /_images/code_examples/selections/memdemo_04.*
:class: width-helper invert-helper
:name: memdemo_04
Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts

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@ -178,4 +178,3 @@ of carry chains and DSPs, it avoids optimising for a path that isn't the actual
critical path, while the generally-longer paths result in ABC9 being able to
reduce design area by mapping other logic to slower cells with greater logic
density.

4
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@ -18,7 +18,7 @@ detail in the :doc:`/getting_started/example_synth` document.
The :file:`counter.ys` script includes the commands used to generate the
images in this document. Code snippets in this document skip these commands;
including line numbers to allow the reader to follow along with the source.
To learn more about these commands, check out :ref:`interactive_show`.
.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
@ -37,7 +37,7 @@ First, let's quickly look at the design:
This is a simple counter with reset and enable. If the reset signal, ``rst``,
is high then the counter will reset to 0. Otherwise, if the enable signal,
``en``, is high then the ``count`` register will increment by 1 each rising edge
of the clock, ``clk``.
of the clock, ``clk``.
Loading the design
~~~~~~~~~~~~~~~~~~

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@ -24,7 +24,7 @@ Example code can be found in |code_examples/macc|_.
.. figure:: /_images/code_examples/macc/macc_simple_test_00a.*
:class: width-helper invert-helper
before `extract`
.. literalinclude:: /code_examples/macc/macc_simple_test.ys
@ -33,7 +33,7 @@ Example code can be found in |code_examples/macc|_.
.. figure:: /_images/code_examples/macc/macc_simple_test_00b.*
:class: width-helper invert-helper
after `extract`
.. literalinclude:: /code_examples/macc/macc_simple_test.v
@ -228,4 +228,4 @@ Unwrap in ``test2``:
:end-before: end part e
.. figure:: /_images/code_examples/macc/macc_xilinx_test2e.*
:class: width-helper invert-helper
:class: width-helper invert-helper

2
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@ -92,7 +92,7 @@ transition table. For each state:
3. Set the state signal to the current state
4. Try to evaluate the next state and control output
5. If step 4 was not successful:
- Recursively goto step 4 with the offending stop-signal set to 0.
- Recursively goto step 4 with the offending stop-signal set to 1.

1
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@ -31,4 +31,3 @@ for commands such as `abc`\ /`abc9`, `simplemap`, `dfflegalize`, and
extract
abc
cell_libs

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@ -122,7 +122,7 @@ to four memory primitive classes available for selection:
- Can handle arbitrary number and kind of read ports
- LUT RAM (aka distributed RAM): uses LUT storage as RAM
- Supported on most FPGAs (with notable exception of ice40)
- Usually has one synchronous write port, one or more asynchronous read ports
- Small
@ -141,7 +141,7 @@ to four memory primitive classes available for selection:
- Huge RAM:
- Only supported on several targets:
- Some Xilinx UltraScale devices (UltraRAM)
- Two ports, both with mutually exclusive synchronous read and write
@ -154,7 +154,7 @@ to four memory primitive classes available for selection:
- Does not support initial data
- Nexus (large RAM)
- Two ports, both with mutually exclusive synchronous read and write
- Single clock
@ -304,7 +304,7 @@ Synchronous SDP with undefined collision behavior
if (read_enable) begin
read_data <= mem[read_addr];
if (write_enable && read_addr == write_addr)
// this if block
read_data <= 'x;
@ -322,7 +322,7 @@ Synchronous SDP with undefined collision behavior
if (write_enable)
mem[write_addr] <= write_data;
if (read_enable)
if (read_enable)
read_data <= mem[read_addr];
end
@ -446,7 +446,7 @@ Synchronous single-port RAM with write-first behavior
if (read_enable)
if (write_enable)
read_data <= write_data;
else
else
read_data <= mem[addr];
end
@ -787,4 +787,3 @@ Asynchronous writes
end
assign read_data = mem[read_addr];

2
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@ -1,4 +1,4 @@
Technology mapping
Technology mapping
==================
.. todo:: less academic, check text is coherent

2
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@ -240,7 +240,7 @@ the design at each log header.
A worked example
~~~~~~~~~~~~~~~~
Say you did all the minimization and found that an error in `synth_xilinx`
occurs when a call to ``techmap -map +/xilinx/cells_map.v`` with
``MIN_MUX_INPUTS`` defined parses a `$_MUX16_` with all inputs set to ``1'x``.

2
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@ -68,7 +68,7 @@ with, and lists off the current design's modules.
:language: c++
:lines: 1, 4, 6, 7-20
:caption: Example command :yoscrypt:`my_cmd` from :file:`my_cmd.cc`
Note that we are making a global instance of a class derived from
``Yosys::Pass``, which we get by including :file:`kernel/yosys.h`.

1
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@ -14,4 +14,3 @@ of interest for developers looking to customise Yosys builds.
advanced_bugpoint
contributing
test_suites

43
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@ -16,6 +16,20 @@ tests.
cmake -B build .
cmake --build build --target test --parallel $(nproc)
.. warning::
There are limitations when using `Ninja` as generator, so we suggest using
`Unix Makefiles` to make running tests in parallel possible. However, it is
possible to use it directly by running:
.. code:: console
cd tests
make -j9
Please note that in this case default build directory is `build` but can be
overwritten by providing `BUILD_DIR` variable.
Vanilla tests
~~~~~~~~~~~~~
@ -76,15 +90,19 @@ If you don't have one of the :ref:`getting_started/installation:CAD suite(s)`
installed, you should also install Z3 `following their
instructions <https://github.com/Z3Prover/z3>`_.
.. TODO:: CMAKE_TODO
Functional tests are disabled by default, to enable them use next code snippet
and run tests as usual:
How does this work under CMake? Is it only via ``make -C tests
ENABLE_FUNCTIONAL_TESTS=1`` and then manually setting ``BUILD_DIR`` and
``PROGRAM_PREFIX``? And possibly also setting ``YOSYS`` et al if there is a
``.exe``. Previous instructions:
.. code:: console
Then, set the :makevar:`ENABLE_FUNCTIONAL_TESTS` make variable when calling
``make test`` and the functional tests will be run as well.
cmake -B build . -DYOSYS_ENABLE_FUNCTIONAL_TESTS=ON
cmake --build build --target test --parallel $(nproc)
Or run just functional tests with:
.. code:: console
cmake --build build --target test-functional
Docs tests
~~~~~~~~~~
@ -164,6 +182,9 @@ compiler versions. For up to date information, including OS versions, refer to
test for ``kernel/celledges.cc``, you will need to create a file like this:
``tests/unit/kernel/celledgesTest.cc``;
* Implement your unit test
* Add unit test to file list in `CMakeLists.txt`
In case unit tests are added to new directory, note that you need also to
create new `CmakeList.txt` file and add ``yosys_gtest(dir-name unit-test.cc)```
Run unit tests
~~~~~~~~~~~~~~
@ -172,10 +193,4 @@ compiler versions. For up to date information, including OS versions, refer to
.. code-block:: console
make unit-test
If you want to remove all unit test files, type:
.. code-block:: console
make clean-unit-test
cmake --build build --target test-unit

3
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@ -10,10 +10,9 @@ These scripts contain three types of commands:
- **Backends**, that write the design in memory to a file (various formats are
available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).
.. toctree::
.. toctree::
:maxdepth: 3
overview
control_and_data
verilog_frontend

10
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@ -432,12 +432,12 @@ variables:
initialization of ``AST_INTERNAL::ProcessGenerator`` these two variables are
empty.
- | ``subst_lvalue_from`` and ``subst_lvalue_to``
- | ``subst_lvalue_from`` and ``subst_lvalue_to``
| These two variables contain the mapping from left-hand-side signals (``\
<name>``) to the current temporary signal for the same thing (initially
``$0\ <name>``).
- | ``current_case``
- | ``current_case``
| A pointer to a ``RTLIL::CaseRule`` object. Initially this is the root case
of the generated ``RTLIL::Process``.
@ -603,13 +603,13 @@ behavioural model in ``RTLIL::Process`` representation. The actual conversion
from a behavioural model to an RTL representation is performed by the `proc`
pass and the passes it launches:
- | `proc_clean` and `proc_rmdead`
- | `proc_clean` and `proc_rmdead`
| These two passes just clean up the ``RTLIL::Process`` structure. The
`proc_clean` pass removes empty parts (eg. empty assignments) from the
process and `proc_rmdead` detects and removes unreachable branches from the
process's decision trees.
- | `proc_arst`
- | `proc_arst`
| This pass detects processes that describe d-type flip-flops with
asynchronous resets and rewrites the process to better reflect what they
are modelling: Before this pass, an asynchronous reset has two
@ -617,7 +617,7 @@ pass and the passes it launches:
reset path. After this pass the sync rule for the reset is level-sensitive
and the top-level ``RTLIL::SwitchRule`` has been removed.
- | `proc_mux`
- | `proc_mux`
| This pass converts the ``RTLIL::CaseRule``/\ ``RTLIL::SwitchRule``-tree to
a tree of multiplexers per written signal. After this, the
``RTLIL::Process`` structure only contains the ``RTLIL::SyncRule`` s that

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@ -48,7 +48,7 @@ RTLIL and fail to run when unsupported high-level constructs are used. In such
cases a pass that transforms the higher-level constructs to lower-level
constructs must be called from the synthesis script first.
.. toctree::
.. toctree::
:maxdepth: 3
rtlil_rep
@ -56,4 +56,3 @@ constructs must be called from the synthesis script first.
.. [1]
In Yosys the term pass is only used to refer to commands that operate on the
RTLIL data structure.

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@ -158,8 +158,8 @@ An ``RTLIL::Wire`` object has the following properties:
- The wire name
- A list of attributes
- A width (buses are just wires with a width more than 1)
- Bus direction (MSB to LSB or vice versa)
- Lowest valid bit index (LSB or MSB depending on bus direction)
- Bus direction (MSb to LSb or vice versa)
- Lowest valid bit index (LSb or MSb depending on bus direction)
- If the wire is a port: port number and direction (input/output/inout)
As with modules, the attributes can be Verilog attributes imported by the
@ -171,8 +171,8 @@ signals. This makes some aspects of RTLIL more complex but enables Yosys to be
used for coarse grain synthesis where the cells of the target architecture
operate on entire signal vectors instead of single bit wires.
In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
In Verilog and VHDL, busses may have arbitrary bounds, and LSb can have either
the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSb;
however, information from the HDL frontend is preserved so that the bus will be
correctly indexed in error messages, backend output, constraint files, etc.