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This commit is contained in:
Emil J. Tywoniak 2024-06-13 22:50:21 +02:00
parent 4c9f68216a
commit eeb15ea2a2
17 changed files with 121 additions and 38 deletions
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10
passes/techmap/abc9_ops.cc
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@ -590,7 +590,7 @@ void break_scc(RTLIL::Module *module)
cell->attributes.erase(it);
if (!r.second)
continue;
for (auto &c : cell->connections_) {
for (auto c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
@ -1353,12 +1353,12 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto jt = mapped_cell->connections_.find(ID(i));
log_assert(jt != mapped_cell->connections_.end());
SigSpec inputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
SigSpec inputs = std::move((*jt).second);
mapped_cell->connections_.erase((*jt).first);
jt = mapped_cell->connections_.find(ID(o));
log_assert(jt != mapped_cell->connections_.end());
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
SigSpec outputs = std::move((*jt).second);
mapped_cell->connections_.erase((*jt).first);
auto abc9_flop = box_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop) {