diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 553eb23d6..db873e4b7 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -473,7 +473,7 @@ struct EdifBackend : public Backend { *f << stringf(" (instance %s\n", EDIF_DEF(cell->name)); *f << stringf(" (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); - for (auto &p : cell->parameters) + for (auto p : cell->parameters) add_prop(p.first, p.second); if (attr_properties) for (auto &p : cell->attributes) diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 47a524e0a..635478890 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -175,7 +175,7 @@ struct IntersynthBackend : public Backend { node_code += stringf(" %s %s", log_id(port.first), netname(conntypes_code, celltypes_code, constcells_code, sig).c_str()); } } - for (auto &¶m : cell->parameters) { + for (auto param : cell->parameters) { celltype_code += stringf(" cfg:%d %s", int(param.second.bits.size()), log_id(param.first)); if (param.second.bits.size() != 32) { node_code += stringf(" %s '", log_id(param.first)); diff --git a/backends/rtlil/rtlil_backend.cc b/backends/rtlil/rtlil_backend.cc index fa54e035f..f4f71f01e 100644 --- a/backends/rtlil/rtlil_backend.cc +++ b/backends/rtlil/rtlil_backend.cc @@ -165,7 +165,7 @@ void RTLIL_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL:: f << stringf("\n"); } f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str()); - for (auto &&it : cell->parameters) { + for (auto it : cell->parameters) { f << stringf("%s parameter%s%s %s ", indent.c_str(), (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", (it.second.flags & RTLIL::CONST_FLAG_REAL) != 0 ? " real" : "", diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 70b63109d..7d46a5c0a 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1087,7 +1087,7 @@ namespace { void check_expected(bool check_matched_sign = false) { - for (auto &¶ : cell->parameters) + for (auto para : cell->parameters) if (expected_params.count(para.first) == 0) error(__LINE__); for (auto conn : cell->connections_) @@ -1973,14 +1973,14 @@ void RTLIL::Module::check() log_assert(it.first == it.second->name); log_assert(!it.first.empty()); log_assert(!it.second->type.empty()); - for (auto &&it2 : it.second->connections_) { + for (auto it2 : it.second->connections_) { log_assert(!it2.first.empty()); it2.second.check(this); } // TODO // for (auto &&it2 : it.second->attributes) // log_assert(!it2.first.empty()); - for (auto &&it2 : it.second->parameters) + for (auto it2 : it.second->parameters) log_assert(!it2.first.empty()); InternalOldCellChecker checker(this, it.second); checker.check(); @@ -2493,9 +2493,9 @@ RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Pro add ## _func(name, sig_a, sig_y, is_signed, src); \ return sig_y; \ } -DEF_METHOD(Not, sig_a.size(), ID($not)) -DEF_METHOD(Pos, sig_a.size(), ID($pos)) -DEF_METHOD(Neg, sig_a.size(), ID($neg)) +// DEF_METHOD(Not, sig_a.size(), ID($not)) +// DEF_METHOD(Pos, sig_a.size(), ID($pos)) +// DEF_METHOD(Neg, sig_a.size(), ID($neg)) DEF_METHOD(ReduceAnd, 1, ID($reduce_and)) DEF_METHOD(ReduceOr, 1, ID($reduce_or)) DEF_METHOD(ReduceXor, 1, ID($reduce_xor)) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 833bd3b54..47d0e7cb2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1690,6 +1690,31 @@ public: const RTLIL::Const& at(RTLIL::IdString name) const { return parent->getParam(name); } + const RTLIL::Const& at(RTLIL::IdString name, const RTLIL::Const& def) const { + if (parent->hasParam(name)) + return parent->getParam(name); + else + return def; + } + dict as_dict() const { + if (parent->is_legacy()) + return parent->legacy->parameters; + + auto d = dict(); + if (parent->type == ID($not)) { + for (auto conn: parent->not_.parameters()) + d[conn.first] = conn.second; + } else if (parent->type == ID($pos)) { + for (auto conn: parent->pos.parameters()) + d[conn.first] = conn.second; + } else if (parent->type == ID($neg)) { + for (auto conn: parent->neg.parameters()) + d[conn.first] = conn.second; + } else { + throw std::out_of_range("Cell::getParam()"); + } + return d; + } void sort() {} void reserve(int n) { (void)n; } // Watch out! This is different semantics than what dict has! @@ -1880,6 +1905,11 @@ public: const_iterator begin() const { return const_iterator(parent, 0); } + const_iterator find(const IdString name) const { + auto it = const_iterator(parent, 0); + for (; it != end() && (*it).first != name; ++it) {} + return it; + } const_iterator end() const { if (parent->is_legacy()) { return const_iterator(parent, parent->legacy->connections_.size()); @@ -1896,12 +1926,37 @@ public: }; struct FakeConns { RTLIL::Cell* parent; - // RTLIL::SigSpec at(RTLIL::IdString name) { - // return parent->getPort(name); - // } + RTLIL::SigSpec at(RTLIL::IdString name) { + return parent->getMutPort(name); + } const RTLIL::SigSpec& at(RTLIL::IdString name) const { return parent->getPort(name); } + const RTLIL::SigSpec& at(RTLIL::IdString name, const RTLIL::SigSpec& def) const { + if (parent->hasPort(name)) + return parent->getPort(name); + else + return def; + } + dict as_dict() const { + if (parent->is_legacy()) + return parent->legacy->connections_; + + auto d = dict(); + if (parent->type == ID($not)) { + for (auto conn: parent->not_.connections()) + d[conn.first] = conn.second; + } else if (parent->type == ID($pos)) { + for (auto conn: parent->pos.connections()) + d[conn.first] = conn.second; + } else if (parent->type == ID($neg)) { + for (auto conn: parent->neg.connections()) + d[conn.first] = conn.second; + } else { + throw std::out_of_range("Cell::getParam()"); + } + return d; + } void sort() {} void reserve(int n) { (void)n; } // Watch out! This is different semantics than what dict has! @@ -1924,6 +1979,24 @@ public: throw std::out_of_range("Cell::getParam()"); } } + bool operator==(const FakeConns& other) const { + auto this_it = this->begin(); + auto other_it = other.begin(); + while (this_it != this->end() && other_it != other.end()) { + if (*this_it != *other_it) + return false; + ++this_it; + ++other_it; + } + if (this_it != this->end() || other_it != other.end()) { + // One has more params than the other + return false; + } + return true; + } + bool operator!=(const FakeConns& other) const { + return !operator==(other); + } int count(RTLIL::IdString portname) const { try { parent->getPort(portname); @@ -2076,6 +2149,11 @@ public: const_iterator begin() const { return const_iterator(parent, 0); } + const_iterator find(const IdString name) const { + auto it = const_iterator(parent, 0); + for (; it != end() && (*it).first != name; ++it) {} + return it; + } const_iterator end() const { if (parent->is_legacy()) { return const_iterator(parent, parent->legacy->connections_.size()); @@ -2163,12 +2241,12 @@ public: // functor(it.second); // } // TODO fix!!! - for (auto &&it : connections_) + for (auto it : connections_) functor(it.second); } template void rewrite_sigspecs(T &functor) { - for (auto &&it : connections_) + for (auto it : connections_) functor(it.second); } void sort() { diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 1a1cadee4..6a7978d27 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -33,7 +33,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); for (auto cell : module->cells()) - for (auto &&port : cell->connections_) + for (auto port : cell->connections_) if (ct.cell_output(cell->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index fc3f24dd8..ba735cbb4 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -245,7 +245,7 @@ struct SetundefPass : public Pass { if (params_mode) { for (auto *cell : module->selected_cells()) { - for (auto &¶meter : cell->parameters) { + for (auto parameter : cell->parameters) { for (auto &bit : parameter.second.bits) { if (bit > RTLIL::State::S1) bit = worker.next_bit(); diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 4b737d728..16577a344 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -162,7 +162,7 @@ struct EquivStructWorker Cell *cell = module->cell(cell_name); key.type = cell->type; - for (auto &&it : cell->parameters) + for (auto it : cell->parameters) key.parameters.push_back(it); std::sort(key.parameters.begin(), key.parameters.end()); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a6b8da2eb..b54d75e84 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -70,7 +70,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, portnames.insert(conn.first); portwidths[conn.first] = max(portwidths[conn.first], conn.second.size()); } - for (auto &¶ : cell->parameters) + for (auto para : cell->parameters) parameters.insert(para.first); } diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index 5f9491cb4..743d2af0a 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -42,7 +42,8 @@ struct OptMergeWorker CellTypes ct; int total_count; - static void sort_pmux_conn(dict &conn) + template + static void sort_pmux_conn(SmellsLikeDict &conn) { SigSpec sig_s = conn.at(ID::S); SigSpec sig_b = conn.at(ID::B); @@ -82,7 +83,8 @@ struct OptMergeWorker vector hash_conn_strings; std::string hash_string = cell->type.str() + "\n"; - const dict *conn = &cell->connections(); + auto tmp = cell->connections_.as_dict(); + dict* conn = &tmp; dict alt_conn; if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul), @@ -140,7 +142,7 @@ struct OptMergeWorker hash_conn_strings.push_back(s + "\n"); } - for (auto &&it : cell->parameters) + for (auto it : cell->parameters) hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n"); std::sort(hash_conn_strings.begin(), hash_conn_strings.end()); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 090a48f5d..64e9fb27e 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -481,11 +481,11 @@ struct ShareWorker return true; } - for (auto &it : c1->parameters) + for (auto it : c1->parameters) if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second) return false; - for (auto &it : c2->parameters) + for (auto it : c2->parameters) if (c1->parameters.count(it.first) == 0 || c1->parameters.at(it.first) != it.second) return false; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5a44048d6..62a2f8b1d 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -722,7 +722,7 @@ struct FreduceWorker RTLIL::Cell *drv = drivers.at(grp[i].bit).first; RTLIL::Wire *dummy_wire = module->addWire(NEW_ID); - for (auto &port : drv->connections_) + for (auto port : drv->connections_) if (ct.cell_output(drv->type, port.first)) sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second); diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index edb5d4485..a645dfbb1 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1336,7 +1336,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin if (c->type.in(ID(_const0_), ID(_const1_))) { RTLIL::SigSig conn; - conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name)); + auto it = c->connections().begin(); + conn.first = module->wire(remap_name((*it).second.as_wire()->name)); conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1); module->connect(conn); continue; diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index fb350ad1e..7c6474dd6 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -590,7 +590,7 @@ void break_scc(RTLIL::Module *module) cell->attributes.erase(it); if (!r.second) continue; - for (auto &c : cell->connections_) { + for (auto c : cell->connections_) { if (c.second.is_fully_const()) continue; if (cell->output(c.first)) { Wire *w = module->addWire(NEW_ID, GetSize(c.second)); @@ -1353,12 +1353,12 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) auto jt = mapped_cell->connections_.find(ID(i)); log_assert(jt != mapped_cell->connections_.end()); - SigSpec inputs = std::move(jt->second); - mapped_cell->connections_.erase(jt); + SigSpec inputs = std::move((*jt).second); + mapped_cell->connections_.erase((*jt).first); jt = mapped_cell->connections_.find(ID(o)); log_assert(jt != mapped_cell->connections_.end()); - SigSpec outputs = std::move(jt->second); - mapped_cell->connections_.erase(jt); + SigSpec outputs = std::move((*jt).second); + mapped_cell->connections_.erase((*jt).first); auto abc9_flop = box_module->get_bool_attribute(ID::abc9_flop); if (abc9_flop) { diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index b801c2b3f..14a3fd68c 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -339,8 +339,10 @@ struct ParamapPass : public Pass { extra_args(args, argidx, design); for (auto module : design->selected_modules()) - for (auto cell : module->selected_cells()) - attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters); + for (auto cell : module->selected_cells()) { + auto params = cell->parameters.as_dict(); + attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, params); + } } } ParamapPass; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index c3f83bb5f..db4721df6 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -105,10 +105,10 @@ public: if (!ignore_parameters) { std::map needle_param, haystack_param; - for (auto &it : needleCell->parameters) + for (auto it : needleCell->parameters) if (!ignored_parameters.count(std::pair(needleCell->type, it.first))) needle_param[it.first] = unified_param(needleCell->type, it.first, it.second); - for (auto &it : haystackCell->parameters) + for (auto it : haystackCell->parameters) if (!ignored_parameters.count(std::pair(haystackCell->type, it.first))) haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second); if (needle_param != haystack_param) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 2eec37dfa..f7ebb5b15 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -490,7 +490,7 @@ struct TechmapWorker { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); - dict parameters(cell->parameters); + dict parameters(cell->parameters.as_dict()); if (tpl->get_blackbox_attribute(ignore_wb)) continue; @@ -514,7 +514,7 @@ struct TechmapWorker { std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); - for (auto &c : cell->parameters) + for (auto c : cell->parameters) m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second)); if (extmapper_name == "wrap") @@ -531,7 +531,7 @@ struct TechmapWorker extmapper_cell->set_src_attribute(cell->get_src_attribute()); int port_counter = 1; - for (auto &c : extmapper_cell->connections_) { + for (auto c : extmapper_cell->connections_) { RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); if (w->name.in(ID::Y, ID::Q)) w->port_output = true; @@ -916,7 +916,7 @@ struct TechmapWorker auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1)); auto it = cell->connections().find(wirename); if (it != cell->connections().end()) { - auto sig = sigmap(it->second); + auto sig = sigmap((*it).second); for (int i = 0; i < sig.size(); i++) if (val[i] == State::S1) initvals.remove_init(sig[i]);