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This commit is contained in:
Emil J. Tywoniak 2024-06-13 22:50:21 +02:00
parent 4c9f68216a
commit eeb15ea2a2
17 changed files with 121 additions and 38 deletions
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passes/techmap/abc.cc
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@ -1336,7 +1336,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (c->type.in(ID(_const0_), ID(_const1_))) {
RTLIL::SigSig conn;
conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
auto it = c->connections().begin();
conn.first = module->wire(remap_name((*it).second.as_wire()->name));
conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
module->connect(conn);
continue;