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This commit is contained in:
Emil J. Tywoniak 2024-06-13 22:50:21 +02:00
parent 4c9f68216a
commit eeb15ea2a2
17 changed files with 121 additions and 38 deletions
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3
passes/techmap/abc.cc
View file

@ -1336,7 +1336,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (c->type.in(ID(_const0_), ID(_const1_))) {
RTLIL::SigSig conn;
conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
auto it = c->connections().begin();
conn.first = module->wire(remap_name((*it).second.as_wire()->name));
conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
module->connect(conn);
continue;

10
passes/techmap/abc9_ops.cc
View file

@ -590,7 +590,7 @@ void break_scc(RTLIL::Module *module)
cell->attributes.erase(it);
if (!r.second)
continue;
for (auto &c : cell->connections_) {
for (auto c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
@ -1353,12 +1353,12 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto jt = mapped_cell->connections_.find(ID(i));
log_assert(jt != mapped_cell->connections_.end());
SigSpec inputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
SigSpec inputs = std::move((*jt).second);
mapped_cell->connections_.erase((*jt).first);
jt = mapped_cell->connections_.find(ID(o));
log_assert(jt != mapped_cell->connections_.end());
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
SigSpec outputs = std::move((*jt).second);
mapped_cell->connections_.erase((*jt).first);
auto abc9_flop = box_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop) {

6
passes/techmap/attrmap.cc
View file

@ -339,8 +339,10 @@ struct ParamapPass : public Pass {
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters);
for (auto cell : module->selected_cells()) {
auto params = cell->parameters.as_dict();
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, params);
}
}
} ParamapPass;

4
passes/techmap/extract.cc
View file

@ -105,10 +105,10 @@ public:
if (!ignore_parameters) {
std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
for (auto &it : needleCell->parameters)
for (auto it : needleCell->parameters)
if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
for (auto &it : haystackCell->parameters)
for (auto it : haystackCell->parameters)
if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
if (needle_param != haystack_param)

8
passes/techmap/techmap.cc
View file

@ -490,7 +490,7 @@ struct TechmapWorker
{
IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->module(tpl_name);
dict<IdString, RTLIL::Const> parameters(cell->parameters);
dict<IdString, RTLIL::Const> parameters(cell->parameters.as_dict());
if (tpl->get_blackbox_attribute(ignore_wb))
continue;
@ -514,7 +514,7 @@ struct TechmapWorker
{
std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
for (auto &c : cell->parameters)
for (auto c : cell->parameters)
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
if (extmapper_name == "wrap")
@ -531,7 +531,7 @@ struct TechmapWorker
extmapper_cell->set_src_attribute(cell->get_src_attribute());
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
for (auto c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (w->name.in(ID::Y, ID::Q))
w->port_output = true;
@ -916,7 +916,7 @@ struct TechmapWorker
auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
auto it = cell->connections().find(wirename);
if (it != cell->connections().end()) {
auto sig = sigmap(it->second);
auto sig = sigmap((*it).second);
for (int i = 0; i < sig.size(); i++)
if (val[i] == State::S1)
initvals.remove_init(sig[i]);