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This commit is contained in:
Emil J. Tywoniak 2024-06-13 22:50:21 +02:00
parent 4c9f68216a
commit eeb15ea2a2
17 changed files with 121 additions and 38 deletions
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2
passes/cmds/connect.cc
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@ -33,7 +33,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
for (auto cell : module->cells())
for (auto &&port : cell->connections_)
for (auto port : cell->connections_)
if (ct.cell_output(cell->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second);

2
passes/cmds/setundef.cc
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@ -245,7 +245,7 @@ struct SetundefPass : public Pass {
if (params_mode)
{
for (auto *cell : module->selected_cells()) {
for (auto &&parameter : cell->parameters) {
for (auto parameter : cell->parameters) {
for (auto &bit : parameter.second.bits) {
if (bit > RTLIL::State::S1)
bit = worker.next_bit();