73%

passes/cmds/connect.cc

@@ -33,7 +33,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 	RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
 
 	for (auto cell : module->cells())
-	for (auto &&port : cell->connections_)
+	for (auto port : cell->connections_)
 		if (ct.cell_output(cell->type, port.first))
 			sigmap(port.second).replace(sig, dummy_wire, &port.second);
 

passes/cmds/setundef.cc

@@ -245,7 +245,7 @@ struct SetundefPass : public Pass {
 			if (params_mode)
 			{
 				for (auto *cell : module->selected_cells()) {
-					for (auto &&parameter : cell->parameters) {
+					for (auto parameter : cell->parameters) {
 						for (auto &bit : parameter.second.bits) {
 							if (bit > RTLIL::State::S1)
 								bit = worker.next_bit();

passes/equiv/equiv_struct.cc

@@ -162,7 +162,7 @@ struct EquivStructWorker
 			Cell *cell = module->cell(cell_name);
 			key.type = cell->type;
 
-			for (auto &&it : cell->parameters)
+			for (auto it : cell->parameters)
 				key.parameters.push_back(it);
 			std::sort(key.parameters.begin(), key.parameters.end());
 

passes/hierarchy/hierarchy.cc

@@ -70,7 +70,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 						portnames.insert(conn.first);
 					portwidths[conn.first] = max(portwidths[conn.first], conn.second.size());
 				}
-				for (auto &&para : cell->parameters)
+				for (auto para : cell->parameters)
 					parameters.insert(para.first);
 			}
 

passes/opt/opt_merge.cc

@@ -42,7 +42,8 @@ struct OptMergeWorker
 	CellTypes ct;
 	int total_count;
 
-	static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
+	template <typename SmellsLikeDict>
+	static void sort_pmux_conn(SmellsLikeDict &conn)
 	{
 		SigSpec sig_s = conn.at(ID::S);
 		SigSpec sig_b = conn.at(ID::B);
@@ -82,7 +83,8 @@ struct OptMergeWorker
 		vector<string> hash_conn_strings;
 		std::string hash_string = cell->type.str() + "\n";
 
-		const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
+		auto tmp = cell->connections_.as_dict();
+		dict<RTLIL::IdString, RTLIL::SigSpec>* conn = &tmp;
 		dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
 
 		if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
@@ -140,7 +142,7 @@ struct OptMergeWorker
 			hash_conn_strings.push_back(s + "\n");
 		}
 
-		for (auto &&it : cell->parameters)
+		for (auto it : cell->parameters)
 			hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
 
 		std::sort(hash_conn_strings.begin(), hash_conn_strings.end());

passes/opt/share.cc

@@ -481,11 +481,11 @@ struct ShareWorker
 			return true;
 		}
 
-		for (auto &it : c1->parameters)
+		for (auto it : c1->parameters)
 			if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second)
 				return false;
 
-		for (auto &it : c2->parameters)
+		for (auto it : c2->parameters)
 			if (c1->parameters.count(it.first) == 0 || c1->parameters.at(it.first) != it.second)
 				return false;
 

passes/sat/freduce.cc

@@ -722,7 +722,7 @@ struct FreduceWorker
 
 				RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
 				RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
-				for (auto &port : drv->connections_)
+				for (auto port : drv->connections_)
 					if (ct.cell_output(drv->type, port.first))
 						sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
 

passes/techmap/abc.cc

@@ -1336,7 +1336,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 			if (c->type.in(ID(_const0_), ID(_const1_))) {
 				RTLIL::SigSig conn;
-				conn.first = module->wire(remap_name(c->connections().begin()->second.as_wire()->name));
+				auto it = c->connections().begin();
+				conn.first = module->wire(remap_name((*it).second.as_wire()->name));
 				conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
 				module->connect(conn);
 				continue;

passes/techmap/abc9_ops.cc

@@ -590,7 +590,7 @@ void break_scc(RTLIL::Module *module)
 		cell->attributes.erase(it);
 		if (!r.second)
 			continue;
-		for (auto &c : cell->connections_) {
+		for (auto c : cell->connections_) {
 			if (c.second.is_fully_const()) continue;
 			if (cell->output(c.first)) {
 				Wire *w = module->addWire(NEW_ID, GetSize(c.second));
@@ -1353,12 +1353,12 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 
 			auto jt = mapped_cell->connections_.find(ID(i));
 			log_assert(jt != mapped_cell->connections_.end());
-			SigSpec inputs = std::move(jt->second);
-			mapped_cell->connections_.erase(jt);
+			SigSpec inputs = std::move((*jt).second);
+			mapped_cell->connections_.erase((*jt).first);
 			jt = mapped_cell->connections_.find(ID(o));
 			log_assert(jt != mapped_cell->connections_.end());
-			SigSpec outputs = std::move(jt->second);
-			mapped_cell->connections_.erase(jt);
+			SigSpec outputs = std::move((*jt).second);
+			mapped_cell->connections_.erase((*jt).first);
 
 			auto abc9_flop = box_module->get_bool_attribute(ID::abc9_flop);
 			if (abc9_flop) {

passes/techmap/attrmap.cc

@@ -339,8 +339,10 @@ struct ParamapPass : public Pass {
 		extra_args(args, argidx, design);
 
 		for (auto module : design->selected_modules())
-		for (auto cell : module->selected_cells())
-			attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->parameters);
+		for (auto cell : module->selected_cells()) {
+			auto params = cell->parameters.as_dict();
+			attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, params);
+		}
 	}
 } ParamapPass;
 

passes/techmap/extract.cc

@@ -105,10 +105,10 @@ public:
 
 		if (!ignore_parameters) {
 			std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
-			for (auto &it : needleCell->parameters)
+			for (auto it : needleCell->parameters)
 				if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
 					needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
-			for (auto &it : haystackCell->parameters)
+			for (auto it : haystackCell->parameters)
 				if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
 					haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
 			if (needle_param != haystack_param)

passes/techmap/techmap.cc

@@ -490,7 +490,7 @@ struct TechmapWorker
 			{
 				IdString derived_name = tpl_name;
 				RTLIL::Module *tpl = map->module(tpl_name);
-				dict<IdString, RTLIL::Const> parameters(cell->parameters);
+				dict<IdString, RTLIL::Const> parameters(cell->parameters.as_dict());
 
 				if (tpl->get_blackbox_attribute(ignore_wb))
 					continue;
@@ -514,7 +514,7 @@ struct TechmapWorker
 					{
 						std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
 
-						for (auto &c : cell->parameters)
+						for (auto c : cell->parameters)
 							m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
 
 						if (extmapper_name == "wrap")
@@ -531,7 +531,7 @@ struct TechmapWorker
 							extmapper_cell->set_src_attribute(cell->get_src_attribute());
 
 							int port_counter = 1;
-							for (auto &c : extmapper_cell->connections_) {
+							for (auto c : extmapper_cell->connections_) {
 								RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
 								if (w->name.in(ID::Y, ID::Q))
 									w->port_output = true;
@@ -916,7 +916,7 @@ struct TechmapWorker
 							auto wirename = RTLIL::escape_id(it.first.substr(21, it.first.size() - 21 - 1));
 							auto it = cell->connections().find(wirename);
 							if (it != cell->connections().end()) {
-								auto sig = sigmap(it->second);
+								auto sig = sigmap((*it).second);
 								for (int i = 0; i < sig.size(); i++)
 									if (val[i] == State::S1)
 										initvals.remove_init(sig[i]);