From c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:06:12 +0200 Subject: [PATCH 1/8] Moved all tests in arch sub directory --- Makefile | 10 +++++----- tests/{ => arch}/anlogic/.gitignore | 0 tests/{ => arch}/anlogic/add_sub.v | 0 tests/{ => arch}/anlogic/add_sub.ys | 0 tests/{ => arch}/anlogic/counter.v | 0 tests/{ => arch}/anlogic/counter.ys | 0 tests/{ => arch}/anlogic/dffs.v | 0 tests/{ => arch}/anlogic/dffs.ys | 0 tests/{ => arch}/anlogic/fsm.v | 0 tests/{ => arch}/anlogic/fsm.ys | 0 tests/{ => arch}/anlogic/latches.v | 0 tests/{ => arch}/anlogic/latches.ys | 0 tests/{ => arch}/anlogic/memory.v | 0 tests/{ => arch}/anlogic/memory.ys | 0 tests/{ => arch}/anlogic/mux.v | 0 tests/{ => arch}/anlogic/mux.ys | 0 tests/{ => arch}/anlogic/run-test.sh | 0 tests/{ => arch}/anlogic/shifter.v | 0 tests/{ => arch}/anlogic/shifter.ys | 0 tests/{ => arch}/anlogic/tribuf.v | 0 tests/{ => arch}/anlogic/tribuf.ys | 0 tests/{ => arch}/ecp5/.gitignore | 0 tests/{ => arch}/ecp5/add_sub.v | 0 tests/{ => arch}/ecp5/add_sub.ys | 0 tests/{ => arch}/ecp5/adffs.v | 0 tests/{ => arch}/ecp5/adffs.ys | 0 tests/{ => arch}/ecp5/counter.v | 0 tests/{ => arch}/ecp5/counter.ys | 0 tests/{ => arch}/ecp5/dffs.v | 0 tests/{ => arch}/ecp5/dffs.ys | 0 tests/{ => arch}/ecp5/dpram.v | 0 tests/{ => arch}/ecp5/dpram.ys | 0 tests/{ => arch}/ecp5/fsm.v | 0 tests/{ => arch}/ecp5/fsm.ys | 0 tests/{ => arch}/ecp5/latches.v | 0 tests/{ => arch}/ecp5/latches.ys | 0 tests/{ => arch}/ecp5/logic.v | 0 tests/{ => arch}/ecp5/logic.ys | 0 tests/{ => arch}/ecp5/macc.v | 0 tests/{ => arch}/ecp5/macc.ys | 0 tests/{ => arch}/ecp5/memory.v | 0 tests/{ => arch}/ecp5/memory.ys | 0 tests/{ => arch}/ecp5/mul.v | 0 tests/{ => arch}/ecp5/mul.ys | 0 tests/{ => arch}/ecp5/mux.v | 0 tests/{ => arch}/ecp5/mux.ys | 0 tests/{ => arch}/ecp5/rom.v | 0 tests/{ => arch}/ecp5/rom.ys | 0 tests/{ => arch}/ecp5/run-test.sh | 0 tests/{ => arch}/ecp5/shifter.v | 0 tests/{ => arch}/ecp5/shifter.ys | 0 tests/{ => arch}/ecp5/tribuf.v | 0 tests/{ => arch}/ecp5/tribuf.ys | 0 tests/{ => arch}/efinix/.gitignore | 0 tests/{ => arch}/efinix/add_sub.v | 0 tests/{ => arch}/efinix/add_sub.ys | 0 tests/{ => arch}/efinix/adffs.v | 0 tests/{ => arch}/efinix/adffs.ys | 0 tests/{ => arch}/efinix/counter.v | 0 tests/{ => arch}/efinix/counter.ys | 0 tests/{ => arch}/efinix/dffs.v | 0 tests/{ => arch}/efinix/dffs.ys | 0 tests/{ => arch}/efinix/fsm.v | 0 tests/{ => arch}/efinix/fsm.ys | 0 tests/{ => arch}/efinix/latches.v | 0 tests/{ => arch}/efinix/latches.ys | 0 tests/{ => arch}/efinix/logic.v | 0 tests/{ => arch}/efinix/logic.ys | 0 tests/{ => arch}/efinix/memory.v | 0 tests/{ => arch}/efinix/memory.ys | 0 tests/{ => arch}/efinix/mux.v | 0 tests/{ => arch}/efinix/mux.ys | 0 tests/{ => arch}/efinix/run-test.sh | 0 tests/{ => arch}/efinix/shifter.v | 0 tests/{ => arch}/efinix/shifter.ys | 0 tests/{ => arch}/efinix/tribuf.v | 0 tests/{ => arch}/efinix/tribuf.ys | 0 tests/{ => arch}/ice40/.gitignore | 0 tests/{ => arch}/ice40/add_sub.v | 0 tests/{ => arch}/ice40/add_sub.ys | 0 tests/{ => arch}/ice40/adffs.v | 0 tests/{ => arch}/ice40/adffs.ys | 0 tests/{ => arch}/ice40/alu.v | 0 tests/{ => arch}/ice40/alu.ys | 0 tests/{ => arch}/ice40/counter.v | 0 tests/{ => arch}/ice40/counter.ys | 0 tests/{ => arch}/ice40/dffs.v | 0 tests/{ => arch}/ice40/dffs.ys | 0 tests/{ => arch}/ice40/div_mod.v | 0 tests/{ => arch}/ice40/div_mod.ys | 0 tests/{ => arch}/ice40/dpram.v | 0 tests/{ => arch}/ice40/dpram.ys | 0 tests/{ => arch}/ice40/fsm.v | 0 tests/{ => arch}/ice40/fsm.ys | 0 tests/{ => arch}/ice40/ice40_opt.ys | 0 tests/{ => arch}/ice40/latches.v | 0 tests/{ => arch}/ice40/latches.ys | 0 tests/{ => arch}/ice40/logic.v | 0 tests/{ => arch}/ice40/logic.ys | 0 tests/{ => arch}/ice40/macc.v | 0 tests/{ => arch}/ice40/macc.ys | 0 tests/{ => arch}/ice40/memory.v | 0 tests/{ => arch}/ice40/memory.ys | 0 tests/{ => arch}/ice40/mul.v | 0 tests/{ => arch}/ice40/mul.ys | 0 tests/{ => arch}/ice40/mux.v | 0 tests/{ => arch}/ice40/mux.ys | 0 tests/{ => arch}/ice40/rom.v | 0 tests/{ => arch}/ice40/rom.ys | 0 tests/{ => arch}/ice40/run-test.sh | 0 tests/{ => arch}/ice40/shifter.v | 0 tests/{ => arch}/ice40/shifter.ys | 0 tests/{ => arch}/ice40/tribuf.v | 0 tests/{ => arch}/ice40/tribuf.ys | 0 tests/{ => arch}/ice40/wrapcarry.ys | 0 tests/{ => arch}/xilinx/.gitignore | 0 tests/{ => arch}/xilinx/add_sub.v | 0 tests/{ => arch}/xilinx/add_sub.ys | 0 tests/{ => arch}/xilinx/adffs.v | 0 tests/{ => arch}/xilinx/adffs.ys | 0 tests/{ => arch}/xilinx/counter.v | 0 tests/{ => arch}/xilinx/counter.ys | 0 tests/{ => arch}/xilinx/dffs.v | 0 tests/{ => arch}/xilinx/dffs.ys | 0 tests/{ => arch}/xilinx/dsp_simd.ys | 0 tests/{ => arch}/xilinx/fsm.v | 0 tests/{ => arch}/xilinx/fsm.ys | 0 tests/{ => arch}/xilinx/latches.v | 0 tests/{ => arch}/xilinx/latches.ys | 0 tests/{ => arch}/xilinx/logic.v | 0 tests/{ => arch}/xilinx/logic.ys | 0 tests/{ => arch}/xilinx/macc.sh | 0 tests/{ => arch}/xilinx/macc.v | 0 tests/{ => arch}/xilinx/macc.ys | 0 tests/{ => arch}/xilinx/macc_tb.v | 0 tests/{ => arch}/xilinx/memory.v | 0 tests/{ => arch}/xilinx/memory.ys | 0 tests/{ => arch}/xilinx/mul.v | 0 tests/{ => arch}/xilinx/mul.ys | 0 tests/{ => arch}/xilinx/mul_unsigned.v | 0 tests/{ => arch}/xilinx/mul_unsigned.ys | 0 tests/{ => arch}/xilinx/mux.v | 0 tests/{ => arch}/xilinx/mux.ys | 0 tests/{ => arch}/xilinx/pmgen_xilinx_srl.ys | 0 tests/{ => arch}/xilinx/run-test.sh | 0 tests/{ => arch}/xilinx/shifter.v | 0 tests/{ => arch}/xilinx/shifter.ys | 0 tests/{ => arch}/xilinx/tribuf.v | 0 tests/{ => arch}/xilinx/tribuf.ys | 0 tests/{ => arch}/xilinx/xilinx_srl.v | 0 tests/{ => arch}/xilinx/xilinx_srl.ys | 0 151 files changed, 5 insertions(+), 5 deletions(-) rename tests/{ => arch}/anlogic/.gitignore (100%) rename tests/{ => arch}/anlogic/add_sub.v (100%) rename tests/{ => arch}/anlogic/add_sub.ys (100%) rename tests/{ => arch}/anlogic/counter.v (100%) rename tests/{ => arch}/anlogic/counter.ys (100%) rename tests/{ => arch}/anlogic/dffs.v (100%) rename tests/{ => arch}/anlogic/dffs.ys (100%) rename tests/{ => arch}/anlogic/fsm.v (100%) rename tests/{ => arch}/anlogic/fsm.ys (100%) rename tests/{ => arch}/anlogic/latches.v (100%) rename tests/{ => arch}/anlogic/latches.ys (100%) rename tests/{ => arch}/anlogic/memory.v (100%) rename tests/{ => arch}/anlogic/memory.ys (100%) rename tests/{ => arch}/anlogic/mux.v (100%) rename tests/{ => arch}/anlogic/mux.ys (100%) rename tests/{ => arch}/anlogic/run-test.sh (100%) rename tests/{ => arch}/anlogic/shifter.v (100%) rename tests/{ => arch}/anlogic/shifter.ys (100%) rename tests/{ => arch}/anlogic/tribuf.v (100%) rename tests/{ => arch}/anlogic/tribuf.ys (100%) rename tests/{ => arch}/ecp5/.gitignore (100%) rename tests/{ => arch}/ecp5/add_sub.v (100%) rename tests/{ => arch}/ecp5/add_sub.ys (100%) rename tests/{ => arch}/ecp5/adffs.v (100%) rename tests/{ => arch}/ecp5/adffs.ys (100%) rename tests/{ => arch}/ecp5/counter.v (100%) rename tests/{ => arch}/ecp5/counter.ys (100%) rename tests/{ => arch}/ecp5/dffs.v (100%) rename tests/{ => arch}/ecp5/dffs.ys (100%) rename tests/{ => arch}/ecp5/dpram.v (100%) rename tests/{ => arch}/ecp5/dpram.ys (100%) rename tests/{ => arch}/ecp5/fsm.v (100%) rename tests/{ => arch}/ecp5/fsm.ys (100%) rename tests/{ => arch}/ecp5/latches.v (100%) rename tests/{ => arch}/ecp5/latches.ys (100%) rename tests/{ => arch}/ecp5/logic.v (100%) rename tests/{ => arch}/ecp5/logic.ys (100%) rename tests/{ => arch}/ecp5/macc.v (100%) rename tests/{ => arch}/ecp5/macc.ys (100%) rename tests/{ => arch}/ecp5/memory.v (100%) rename tests/{ => arch}/ecp5/memory.ys (100%) rename tests/{ => arch}/ecp5/mul.v (100%) rename tests/{ => arch}/ecp5/mul.ys (100%) rename tests/{ => arch}/ecp5/mux.v (100%) rename tests/{ => arch}/ecp5/mux.ys (100%) rename tests/{ => arch}/ecp5/rom.v (100%) rename tests/{ => arch}/ecp5/rom.ys (100%) rename tests/{ => arch}/ecp5/run-test.sh (100%) rename tests/{ => arch}/ecp5/shifter.v (100%) rename tests/{ => arch}/ecp5/shifter.ys (100%) rename tests/{ => arch}/ecp5/tribuf.v (100%) rename tests/{ => arch}/ecp5/tribuf.ys (100%) rename tests/{ => arch}/efinix/.gitignore (100%) rename tests/{ => arch}/efinix/add_sub.v (100%) rename tests/{ => arch}/efinix/add_sub.ys (100%) rename tests/{ => arch}/efinix/adffs.v (100%) rename tests/{ => arch}/efinix/adffs.ys (100%) rename tests/{ => arch}/efinix/counter.v (100%) rename tests/{ => arch}/efinix/counter.ys (100%) rename tests/{ => arch}/efinix/dffs.v (100%) rename tests/{ => arch}/efinix/dffs.ys (100%) rename tests/{ => arch}/efinix/fsm.v (100%) rename tests/{ => arch}/efinix/fsm.ys (100%) rename tests/{ => arch}/efinix/latches.v (100%) rename tests/{ => arch}/efinix/latches.ys (100%) rename tests/{ => arch}/efinix/logic.v (100%) rename tests/{ => arch}/efinix/logic.ys (100%) rename tests/{ => arch}/efinix/memory.v (100%) rename tests/{ => arch}/efinix/memory.ys (100%) rename tests/{ => arch}/efinix/mux.v (100%) rename tests/{ => arch}/efinix/mux.ys (100%) rename tests/{ => arch}/efinix/run-test.sh (100%) rename tests/{ => arch}/efinix/shifter.v (100%) rename tests/{ => arch}/efinix/shifter.ys (100%) rename tests/{ => arch}/efinix/tribuf.v (100%) rename tests/{ => arch}/efinix/tribuf.ys (100%) rename tests/{ => arch}/ice40/.gitignore (100%) rename tests/{ => arch}/ice40/add_sub.v (100%) rename tests/{ => arch}/ice40/add_sub.ys (100%) rename tests/{ => arch}/ice40/adffs.v (100%) rename tests/{ => arch}/ice40/adffs.ys (100%) rename tests/{ => arch}/ice40/alu.v (100%) rename tests/{ => arch}/ice40/alu.ys (100%) rename tests/{ => arch}/ice40/counter.v (100%) rename tests/{ => arch}/ice40/counter.ys (100%) rename tests/{ => arch}/ice40/dffs.v (100%) rename tests/{ => arch}/ice40/dffs.ys (100%) rename tests/{ => arch}/ice40/div_mod.v (100%) rename tests/{ => arch}/ice40/div_mod.ys (100%) rename tests/{ => arch}/ice40/dpram.v (100%) rename tests/{ => arch}/ice40/dpram.ys (100%) rename tests/{ => arch}/ice40/fsm.v (100%) rename tests/{ => arch}/ice40/fsm.ys (100%) rename tests/{ => arch}/ice40/ice40_opt.ys (100%) rename tests/{ => arch}/ice40/latches.v (100%) rename tests/{ => arch}/ice40/latches.ys (100%) rename tests/{ => arch}/ice40/logic.v (100%) rename tests/{ => arch}/ice40/logic.ys (100%) rename tests/{ => arch}/ice40/macc.v (100%) rename tests/{ => arch}/ice40/macc.ys (100%) rename tests/{ => arch}/ice40/memory.v (100%) rename tests/{ => arch}/ice40/memory.ys (100%) rename tests/{ => arch}/ice40/mul.v (100%) rename tests/{ => arch}/ice40/mul.ys (100%) rename tests/{ => arch}/ice40/mux.v (100%) rename tests/{ => arch}/ice40/mux.ys (100%) rename tests/{ => arch}/ice40/rom.v (100%) rename tests/{ => arch}/ice40/rom.ys (100%) rename tests/{ => arch}/ice40/run-test.sh (100%) rename tests/{ => arch}/ice40/shifter.v (100%) rename tests/{ => arch}/ice40/shifter.ys (100%) rename tests/{ => arch}/ice40/tribuf.v (100%) rename tests/{ => arch}/ice40/tribuf.ys (100%) rename tests/{ => arch}/ice40/wrapcarry.ys (100%) rename tests/{ => arch}/xilinx/.gitignore (100%) rename tests/{ => arch}/xilinx/add_sub.v (100%) rename tests/{ => arch}/xilinx/add_sub.ys (100%) rename tests/{ => arch}/xilinx/adffs.v (100%) rename tests/{ => arch}/xilinx/adffs.ys (100%) rename tests/{ => arch}/xilinx/counter.v (100%) rename tests/{ => arch}/xilinx/counter.ys (100%) rename tests/{ => arch}/xilinx/dffs.v (100%) rename tests/{ => arch}/xilinx/dffs.ys (100%) rename tests/{ => arch}/xilinx/dsp_simd.ys (100%) rename tests/{ => arch}/xilinx/fsm.v (100%) rename tests/{ => arch}/xilinx/fsm.ys (100%) rename tests/{ => arch}/xilinx/latches.v (100%) rename tests/{ => arch}/xilinx/latches.ys (100%) rename tests/{ => arch}/xilinx/logic.v (100%) rename tests/{ => arch}/xilinx/logic.ys (100%) rename tests/{ => arch}/xilinx/macc.sh (100%) rename tests/{ => arch}/xilinx/macc.v (100%) rename tests/{ => arch}/xilinx/macc.ys (100%) rename tests/{ => arch}/xilinx/macc_tb.v (100%) rename tests/{ => arch}/xilinx/memory.v (100%) rename tests/{ => arch}/xilinx/memory.ys (100%) rename tests/{ => arch}/xilinx/mul.v (100%) rename tests/{ => arch}/xilinx/mul.ys (100%) rename tests/{ => arch}/xilinx/mul_unsigned.v (100%) rename tests/{ => arch}/xilinx/mul_unsigned.ys (100%) rename tests/{ => arch}/xilinx/mux.v (100%) rename tests/{ => arch}/xilinx/mux.ys (100%) rename tests/{ => arch}/xilinx/pmgen_xilinx_srl.ys (100%) rename tests/{ => arch}/xilinx/run-test.sh (100%) rename tests/{ => arch}/xilinx/shifter.v (100%) rename tests/{ => arch}/xilinx/shifter.ys (100%) rename tests/{ => arch}/xilinx/tribuf.v (100%) rename tests/{ => arch}/xilinx/tribuf.ys (100%) rename tests/{ => arch}/xilinx/xilinx_srl.v (100%) rename tests/{ => arch}/xilinx/xilinx_srl.ys (100%) diff --git a/Makefile b/Makefile index 70d683c34..a24f19b6a 100644 --- a/Makefile +++ b/Makefile @@ -713,12 +713,12 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh - +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/xilinx && bash run-test.sh $(SEEDOPT) + +cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/efinix && bash run-test.sh $(SEEDOPT) + +cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh - +cd tests/efinix && bash run-test.sh $(SEEDOPT) - +cd tests/anlogic && bash run-test.sh $(SEEDOPT) - +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) - +cd tests/xilinx && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/anlogic/.gitignore b/tests/arch/anlogic/.gitignore similarity index 100% rename from tests/anlogic/.gitignore rename to tests/arch/anlogic/.gitignore diff --git a/tests/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v similarity index 100% rename from tests/anlogic/add_sub.v rename to tests/arch/anlogic/add_sub.v diff --git a/tests/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys similarity index 100% rename from tests/anlogic/add_sub.ys rename to tests/arch/anlogic/add_sub.ys diff --git a/tests/anlogic/counter.v b/tests/arch/anlogic/counter.v similarity index 100% rename from tests/anlogic/counter.v rename to tests/arch/anlogic/counter.v diff --git a/tests/anlogic/counter.ys b/tests/arch/anlogic/counter.ys similarity index 100% rename from tests/anlogic/counter.ys rename to tests/arch/anlogic/counter.ys diff --git a/tests/anlogic/dffs.v b/tests/arch/anlogic/dffs.v similarity index 100% rename from tests/anlogic/dffs.v rename to tests/arch/anlogic/dffs.v diff --git a/tests/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys similarity index 100% rename from tests/anlogic/dffs.ys rename to tests/arch/anlogic/dffs.ys diff --git a/tests/anlogic/fsm.v b/tests/arch/anlogic/fsm.v similarity index 100% rename from tests/anlogic/fsm.v rename to tests/arch/anlogic/fsm.v diff --git a/tests/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys similarity index 100% rename from tests/anlogic/fsm.ys rename to tests/arch/anlogic/fsm.ys diff --git a/tests/anlogic/latches.v b/tests/arch/anlogic/latches.v similarity index 100% rename from tests/anlogic/latches.v rename to tests/arch/anlogic/latches.v diff --git a/tests/anlogic/latches.ys b/tests/arch/anlogic/latches.ys similarity index 100% rename from tests/anlogic/latches.ys rename to tests/arch/anlogic/latches.ys diff --git a/tests/anlogic/memory.v b/tests/arch/anlogic/memory.v similarity index 100% rename from tests/anlogic/memory.v rename to tests/arch/anlogic/memory.v diff --git a/tests/anlogic/memory.ys b/tests/arch/anlogic/memory.ys similarity index 100% rename from tests/anlogic/memory.ys rename to tests/arch/anlogic/memory.ys diff --git a/tests/anlogic/mux.v b/tests/arch/anlogic/mux.v similarity index 100% rename from tests/anlogic/mux.v rename to tests/arch/anlogic/mux.v diff --git a/tests/anlogic/mux.ys b/tests/arch/anlogic/mux.ys similarity index 100% rename from tests/anlogic/mux.ys rename to tests/arch/anlogic/mux.ys diff --git a/tests/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh similarity index 100% rename from tests/anlogic/run-test.sh rename to tests/arch/anlogic/run-test.sh diff --git a/tests/anlogic/shifter.v b/tests/arch/anlogic/shifter.v similarity index 100% rename from tests/anlogic/shifter.v rename to tests/arch/anlogic/shifter.v diff --git a/tests/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys similarity index 100% rename from tests/anlogic/shifter.ys rename to tests/arch/anlogic/shifter.ys diff --git a/tests/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v similarity index 100% rename from tests/anlogic/tribuf.v rename to tests/arch/anlogic/tribuf.v diff --git a/tests/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys similarity index 100% rename from tests/anlogic/tribuf.ys rename to tests/arch/anlogic/tribuf.ys diff --git a/tests/ecp5/.gitignore b/tests/arch/ecp5/.gitignore similarity index 100% rename from tests/ecp5/.gitignore rename to tests/arch/ecp5/.gitignore diff --git a/tests/ecp5/add_sub.v b/tests/arch/ecp5/add_sub.v similarity index 100% rename from tests/ecp5/add_sub.v rename to tests/arch/ecp5/add_sub.v diff --git a/tests/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys similarity index 100% rename from tests/ecp5/add_sub.ys rename to tests/arch/ecp5/add_sub.ys diff --git a/tests/ecp5/adffs.v b/tests/arch/ecp5/adffs.v similarity index 100% rename from tests/ecp5/adffs.v rename to tests/arch/ecp5/adffs.v diff --git a/tests/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys similarity index 100% rename from tests/ecp5/adffs.ys rename to tests/arch/ecp5/adffs.ys diff --git a/tests/ecp5/counter.v b/tests/arch/ecp5/counter.v similarity index 100% rename from tests/ecp5/counter.v rename to tests/arch/ecp5/counter.v diff --git a/tests/ecp5/counter.ys b/tests/arch/ecp5/counter.ys similarity index 100% rename from tests/ecp5/counter.ys rename to tests/arch/ecp5/counter.ys diff --git a/tests/ecp5/dffs.v b/tests/arch/ecp5/dffs.v similarity index 100% rename from tests/ecp5/dffs.v rename to tests/arch/ecp5/dffs.v diff --git a/tests/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys similarity index 100% rename from tests/ecp5/dffs.ys rename to tests/arch/ecp5/dffs.ys diff --git a/tests/ecp5/dpram.v b/tests/arch/ecp5/dpram.v similarity index 100% rename from tests/ecp5/dpram.v rename to tests/arch/ecp5/dpram.v diff --git a/tests/ecp5/dpram.ys b/tests/arch/ecp5/dpram.ys similarity index 100% rename from tests/ecp5/dpram.ys rename to tests/arch/ecp5/dpram.ys diff --git a/tests/ecp5/fsm.v b/tests/arch/ecp5/fsm.v similarity index 100% rename from tests/ecp5/fsm.v rename to tests/arch/ecp5/fsm.v diff --git a/tests/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys similarity index 100% rename from tests/ecp5/fsm.ys rename to tests/arch/ecp5/fsm.ys diff --git a/tests/ecp5/latches.v b/tests/arch/ecp5/latches.v similarity index 100% rename from tests/ecp5/latches.v rename to tests/arch/ecp5/latches.v diff --git a/tests/ecp5/latches.ys b/tests/arch/ecp5/latches.ys similarity index 100% rename from tests/ecp5/latches.ys rename to tests/arch/ecp5/latches.ys diff --git a/tests/ecp5/logic.v b/tests/arch/ecp5/logic.v similarity index 100% rename from tests/ecp5/logic.v rename to tests/arch/ecp5/logic.v diff --git a/tests/ecp5/logic.ys b/tests/arch/ecp5/logic.ys similarity index 100% rename from tests/ecp5/logic.ys rename to tests/arch/ecp5/logic.ys diff --git a/tests/ecp5/macc.v b/tests/arch/ecp5/macc.v similarity index 100% rename from tests/ecp5/macc.v rename to tests/arch/ecp5/macc.v diff --git a/tests/ecp5/macc.ys b/tests/arch/ecp5/macc.ys similarity index 100% rename from tests/ecp5/macc.ys rename to tests/arch/ecp5/macc.ys diff --git a/tests/ecp5/memory.v b/tests/arch/ecp5/memory.v similarity index 100% rename from tests/ecp5/memory.v rename to tests/arch/ecp5/memory.v diff --git a/tests/ecp5/memory.ys b/tests/arch/ecp5/memory.ys similarity index 100% rename from tests/ecp5/memory.ys rename to tests/arch/ecp5/memory.ys diff --git a/tests/ecp5/mul.v b/tests/arch/ecp5/mul.v similarity index 100% rename from tests/ecp5/mul.v rename to tests/arch/ecp5/mul.v diff --git a/tests/ecp5/mul.ys b/tests/arch/ecp5/mul.ys similarity index 100% rename from tests/ecp5/mul.ys rename to tests/arch/ecp5/mul.ys diff --git a/tests/ecp5/mux.v b/tests/arch/ecp5/mux.v similarity index 100% rename from tests/ecp5/mux.v rename to tests/arch/ecp5/mux.v diff --git a/tests/ecp5/mux.ys b/tests/arch/ecp5/mux.ys similarity index 100% rename from tests/ecp5/mux.ys rename to tests/arch/ecp5/mux.ys diff --git a/tests/ecp5/rom.v b/tests/arch/ecp5/rom.v similarity index 100% rename from tests/ecp5/rom.v rename to tests/arch/ecp5/rom.v diff --git a/tests/ecp5/rom.ys b/tests/arch/ecp5/rom.ys similarity index 100% rename from tests/ecp5/rom.ys rename to tests/arch/ecp5/rom.ys diff --git a/tests/ecp5/run-test.sh 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a/tests/xilinx/fsm.v b/tests/arch/xilinx/fsm.v similarity index 100% rename from tests/xilinx/fsm.v rename to tests/arch/xilinx/fsm.v diff --git a/tests/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys similarity index 100% rename from tests/xilinx/fsm.ys rename to tests/arch/xilinx/fsm.ys diff --git a/tests/xilinx/latches.v b/tests/arch/xilinx/latches.v similarity index 100% rename from tests/xilinx/latches.v rename to tests/arch/xilinx/latches.v diff --git a/tests/xilinx/latches.ys b/tests/arch/xilinx/latches.ys similarity index 100% rename from tests/xilinx/latches.ys rename to tests/arch/xilinx/latches.ys diff --git a/tests/xilinx/logic.v b/tests/arch/xilinx/logic.v similarity index 100% rename from tests/xilinx/logic.v rename to tests/arch/xilinx/logic.v diff --git a/tests/xilinx/logic.ys b/tests/arch/xilinx/logic.ys similarity index 100% rename from tests/xilinx/logic.ys rename to tests/arch/xilinx/logic.ys diff --git a/tests/xilinx/macc.sh b/tests/arch/xilinx/macc.sh similarity index 100% rename from tests/xilinx/macc.sh rename to tests/arch/xilinx/macc.sh diff --git a/tests/xilinx/macc.v b/tests/arch/xilinx/macc.v similarity index 100% rename from tests/xilinx/macc.v rename to tests/arch/xilinx/macc.v diff --git a/tests/xilinx/macc.ys b/tests/arch/xilinx/macc.ys similarity index 100% rename from tests/xilinx/macc.ys rename to tests/arch/xilinx/macc.ys diff --git a/tests/xilinx/macc_tb.v b/tests/arch/xilinx/macc_tb.v similarity index 100% rename from tests/xilinx/macc_tb.v rename to tests/arch/xilinx/macc_tb.v diff --git a/tests/xilinx/memory.v b/tests/arch/xilinx/memory.v similarity index 100% rename from tests/xilinx/memory.v rename to tests/arch/xilinx/memory.v diff --git a/tests/xilinx/memory.ys b/tests/arch/xilinx/memory.ys similarity index 100% rename from tests/xilinx/memory.ys rename to tests/arch/xilinx/memory.ys diff --git a/tests/xilinx/mul.v b/tests/arch/xilinx/mul.v similarity index 100% rename from tests/xilinx/mul.v rename to tests/arch/xilinx/mul.v diff --git a/tests/xilinx/mul.ys b/tests/arch/xilinx/mul.ys similarity index 100% rename from tests/xilinx/mul.ys rename to tests/arch/xilinx/mul.ys diff --git a/tests/xilinx/mul_unsigned.v b/tests/arch/xilinx/mul_unsigned.v similarity index 100% rename from tests/xilinx/mul_unsigned.v rename to tests/arch/xilinx/mul_unsigned.v diff --git a/tests/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys similarity index 100% rename from tests/xilinx/mul_unsigned.ys rename to tests/arch/xilinx/mul_unsigned.ys diff --git a/tests/xilinx/mux.v b/tests/arch/xilinx/mux.v similarity index 100% rename from tests/xilinx/mux.v rename to tests/arch/xilinx/mux.v diff --git a/tests/xilinx/mux.ys b/tests/arch/xilinx/mux.ys similarity index 100% rename from tests/xilinx/mux.ys rename to tests/arch/xilinx/mux.ys diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys similarity index 100% rename from tests/xilinx/pmgen_xilinx_srl.ys rename to tests/arch/xilinx/pmgen_xilinx_srl.ys diff --git a/tests/xilinx/run-test.sh b/tests/arch/xilinx/run-test.sh similarity index 100% rename from tests/xilinx/run-test.sh rename to tests/arch/xilinx/run-test.sh diff --git a/tests/xilinx/shifter.v b/tests/arch/xilinx/shifter.v similarity index 100% rename from tests/xilinx/shifter.v rename to tests/arch/xilinx/shifter.v diff --git a/tests/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys similarity index 100% rename from tests/xilinx/shifter.ys rename to tests/arch/xilinx/shifter.ys diff --git a/tests/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v similarity index 100% rename from tests/xilinx/tribuf.v rename to tests/arch/xilinx/tribuf.v diff --git a/tests/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys similarity index 100% rename from tests/xilinx/tribuf.ys rename to tests/arch/xilinx/tribuf.ys diff --git a/tests/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v similarity index 100% rename from tests/xilinx/xilinx_srl.v rename to tests/arch/xilinx/xilinx_srl.v diff --git a/tests/xilinx/xilinx_srl.ys b/tests/arch/xilinx/xilinx_srl.ys similarity index 100% rename from tests/xilinx/xilinx_srl.ys rename to tests/arch/xilinx/xilinx_srl.ys From 56f94826753c1f26c9026493a40ecef14806d779 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:12:03 +0200 Subject: [PATCH 2/8] Fix path to yosys --- tests/arch/anlogic/run-test.sh | 2 +- tests/arch/ecp5/run-test.sh | 2 +- tests/arch/efinix/run-test.sh | 2 +- tests/arch/ice40/run-test.sh | 2 +- tests/arch/xilinx/run-test.sh | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/arch/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/anlogic/run-test.sh +++ b/tests/arch/anlogic/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/ecp5/run-test.sh b/tests/arch/ecp5/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/ecp5/run-test.sh +++ b/tests/arch/ecp5/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/efinix/run-test.sh b/tests/arch/efinix/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/efinix/run-test.sh +++ b/tests/arch/efinix/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/ice40/run-test.sh b/tests/arch/ice40/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/ice40/run-test.sh +++ b/tests/arch/ice40/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/xilinx/run-test.sh b/tests/arch/xilinx/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/xilinx/run-test.sh +++ b/tests/arch/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then From ab98f2dccf52a1bba396fe313ea0670603dc45ca Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:18:53 +0200 Subject: [PATCH 3/8] fix yosys path --- tests/arch/xilinx/macc.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 86e4c2bb6..2272679ee 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,3 @@ -../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v -iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v +../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v +iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: [PATCH 4/8] Share common tests --- tests/arch/anlogic/add_sub.ys | 2 +- tests/arch/anlogic/counter.ys | 2 +- tests/arch/anlogic/dffs.ys | 2 +- tests/arch/anlogic/fsm.ys | 2 +- tests/arch/anlogic/latches.ys | 2 +- tests/arch/anlogic/logic.ys | 11 +++ tests/arch/anlogic/mux.ys | 2 +- tests/arch/anlogic/shifter.ys | 2 +- tests/arch/anlogic/tribuf.v | 8 -- tests/arch/anlogic/tribuf.ys | 2 +- tests/arch/{anlogic => common}/add_sub.v | 0 tests/arch/{ecp5 => common}/adffs.v | 0 tests/arch/{anlogic => common}/counter.v | 0 tests/arch/{anlogic => common}/dffs.v | 0 tests/arch/{anlogic => common}/fsm.v | 0 tests/arch/{anlogic => common}/latches.v | 0 tests/arch/{ecp5 => common}/logic.v | 0 tests/arch/{ecp5 => common}/mul.v | 0 tests/arch/{anlogic => common}/mux.v | 0 tests/arch/{anlogic => common}/shifter.v | 0 tests/arch/{efinix => common}/tribuf.v | 0 tests/arch/ecp5/add_sub.v | 13 --- tests/arch/ecp5/add_sub.ys | 2 +- tests/arch/ecp5/adffs.ys | 2 +- tests/arch/ecp5/counter.v | 17 ---- tests/arch/ecp5/counter.ys | 2 +- tests/arch/ecp5/dffs.v | 15 ---- tests/arch/ecp5/dffs.ys | 2 +- tests/arch/ecp5/fsm.v | 55 ------------- tests/arch/ecp5/fsm.ys | 2 +- tests/arch/ecp5/latches.v | 24 ------ tests/arch/ecp5/latches.ys | 3 +- tests/arch/ecp5/logic.ys | 2 +- tests/arch/ecp5/mul.ys | 2 +- tests/arch/ecp5/mux.v | 66 --------------- tests/arch/ecp5/mux.ys | 2 +- tests/arch/ecp5/shifter.v | 16 ---- tests/arch/ecp5/shifter.ys | 2 +- tests/arch/ecp5/tribuf.v | 8 -- tests/arch/ecp5/tribuf.ys | 2 +- tests/arch/efinix/add_sub.v | 13 --- tests/arch/efinix/add_sub.ys | 2 +- tests/arch/efinix/adffs.v | 47 ----------- tests/arch/efinix/adffs.ys | 2 +- tests/arch/efinix/counter.v | 17 ---- tests/arch/efinix/counter.ys | 2 +- tests/arch/efinix/dffs.v | 15 ---- tests/arch/efinix/dffs.ys | 2 +- tests/arch/efinix/fsm.v | 55 ------------- tests/arch/efinix/fsm.ys | 2 +- tests/arch/efinix/latches.v | 24 ------ tests/arch/efinix/latches.ys | 2 +- tests/arch/efinix/logic.v | 18 ---- tests/arch/efinix/logic.ys | 2 +- tests/arch/efinix/mux.v | 65 --------------- tests/arch/efinix/mux.ys | 2 +- tests/arch/efinix/shifter.v | 16 ---- tests/arch/efinix/shifter.ys | 2 +- tests/arch/efinix/tribuf.ys | 2 +- tests/arch/ice40/add_sub.v | 13 --- tests/arch/ice40/add_sub.ys | 2 +- tests/arch/ice40/adffs.v | 87 -------------------- tests/arch/ice40/adffs.ys | 46 +++++++++-- tests/arch/ice40/counter.v | 17 ---- tests/arch/ice40/counter.ys | 2 +- tests/arch/ice40/dffs.v | 37 --------- tests/arch/ice40/dffs.ys | 19 +++-- tests/arch/ice40/fsm.v | 73 ----------------- tests/arch/ice40/fsm.ys | 6 +- tests/arch/ice40/latches.v | 58 ------------- tests/arch/ice40/latches.ys | 35 ++++++-- tests/arch/ice40/logic.v | 18 ---- tests/arch/ice40/logic.ys | 2 +- tests/arch/ice40/mul.v | 11 --- tests/arch/ice40/mul.ys | 2 +- tests/arch/ice40/mux.v | 100 ----------------------- tests/arch/ice40/mux.ys | 40 ++++++++- tests/arch/ice40/shifter.v | 22 ----- tests/arch/ice40/shifter.ys | 2 +- tests/arch/ice40/tribuf.v | 23 ------ tests/arch/ice40/tribuf.ys | 8 +- tests/arch/xilinx/add_sub.v | 13 --- tests/arch/xilinx/add_sub.ys | 2 +- tests/arch/xilinx/adffs.v | 47 ----------- tests/arch/xilinx/adffs.ys | 2 +- tests/arch/xilinx/counter.v | 17 ---- tests/arch/xilinx/counter.ys | 2 +- tests/arch/xilinx/dffs.v | 15 ---- tests/arch/xilinx/dffs.ys | 2 +- tests/arch/xilinx/fsm.v | 55 ------------- tests/arch/xilinx/fsm.ys | 2 +- tests/arch/xilinx/latches.v | 24 ------ tests/arch/xilinx/latches.ys | 2 +- tests/arch/xilinx/logic.v | 18 ---- tests/arch/xilinx/logic.ys | 2 +- tests/arch/xilinx/mul.v | 11 --- tests/arch/xilinx/mul.ys | 2 +- tests/arch/xilinx/mux.v | 65 --------------- tests/arch/xilinx/mux.ys | 2 +- tests/arch/xilinx/shifter.v | 16 ---- tests/arch/xilinx/shifter.ys | 2 +- tests/arch/xilinx/tribuf.v | 8 -- tests/arch/xilinx/tribuf.ys | 2 +- 103 files changed, 179 insertions(+), 1317 deletions(-) create mode 100644 tests/arch/anlogic/logic.ys delete mode 100644 tests/arch/anlogic/tribuf.v rename tests/arch/{anlogic => common}/add_sub.v (100%) rename tests/arch/{ecp5 => common}/adffs.v (100%) rename tests/arch/{anlogic => common}/counter.v (100%) rename tests/arch/{anlogic => common}/dffs.v (100%) rename tests/arch/{anlogic => common}/fsm.v (100%) rename tests/arch/{anlogic => common}/latches.v (100%) rename tests/arch/{ecp5 => common}/logic.v (100%) rename tests/arch/{ecp5 => common}/mul.v (100%) rename tests/arch/{anlogic => common}/mux.v (100%) rename tests/arch/{anlogic => common}/shifter.v (100%) rename tests/arch/{efinix => common}/tribuf.v (100%) delete mode 100644 tests/arch/ecp5/add_sub.v delete mode 100644 tests/arch/ecp5/counter.v delete mode 100644 tests/arch/ecp5/dffs.v delete mode 100644 tests/arch/ecp5/fsm.v delete mode 100644 tests/arch/ecp5/latches.v delete mode 100644 tests/arch/ecp5/mux.v delete mode 100644 tests/arch/ecp5/shifter.v delete mode 100644 tests/arch/ecp5/tribuf.v delete mode 100644 tests/arch/efinix/add_sub.v delete mode 100644 tests/arch/efinix/adffs.v delete mode 100644 tests/arch/efinix/counter.v delete mode 100644 tests/arch/efinix/dffs.v delete mode 100644 tests/arch/efinix/fsm.v delete mode 100644 tests/arch/efinix/latches.v delete mode 100644 tests/arch/efinix/logic.v delete mode 100644 tests/arch/efinix/mux.v delete mode 100644 tests/arch/efinix/shifter.v delete mode 100644 tests/arch/ice40/add_sub.v delete mode 100644 tests/arch/ice40/adffs.v delete mode 100644 tests/arch/ice40/counter.v delete mode 100644 tests/arch/ice40/dffs.v delete mode 100644 tests/arch/ice40/fsm.v delete mode 100644 tests/arch/ice40/latches.v delete mode 100644 tests/arch/ice40/logic.v delete mode 100644 tests/arch/ice40/mul.v delete mode 100644 tests/arch/ice40/mux.v delete mode 100644 tests/arch/ice40/shifter.v delete mode 100644 tests/arch/ice40/tribuf.v delete mode 100644 tests/arch/xilinx/add_sub.v delete mode 100644 tests/arch/xilinx/adffs.v delete mode 100644 tests/arch/xilinx/counter.v delete mode 100644 tests/arch/xilinx/dffs.v delete mode 100644 tests/arch/xilinx/fsm.v delete mode 100644 tests/arch/xilinx/latches.v delete mode 100644 tests/arch/xilinx/logic.v delete mode 100644 tests/arch/xilinx/mul.v delete mode 100644 tests/arch/xilinx/mux.v delete mode 100644 tests/arch/xilinx/shifter.v delete mode 100644 tests/arch/xilinx/tribuf.v diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys index b8b67cc46..5396ce7ec 100644 --- a/tests/arch/anlogic/add_sub.ys +++ b/tests/arch/anlogic/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys index 036fdba46..d363ec24e 100644 --- a/tests/arch/anlogic/counter.ys +++ b/tests/arch/anlogic/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys index 9cbe5fce7..d3281ab89 100644 --- a/tests/arch/anlogic/dffs.ys +++ b/tests/arch/anlogic/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index 452ef9251..f45951b13 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc #flatten diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys index c00c7a25d..8d66f77b3 100644 --- a/tests/arch/anlogic/latches.ys +++ b/tests/arch/anlogic/latches.ys @@ -1,4 +1,4 @@ -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys new file mode 100644 index 000000000..125ee5d0f --- /dev/null +++ b/tests/arch/anlogic/logic.ys @@ -0,0 +1,11 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:AL_MAP_LUT1 +select -assert-count 6 t:AL_MAP_LUT2 +select -assert-count 2 t:AL_MAP_LUT4 +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys index 64ed2a2bd..3d5fe7c9a 100644 --- a/tests/arch/anlogic/mux.ys +++ b/tests/arch/anlogic/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys index 5eaed30a3..12df44b2a 100644 --- a/tests/arch/anlogic/shifter.ys +++ b/tests/arch/anlogic/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/arch/anlogic/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys index 0eb1338ac..eaa073750 100644 --- a/tests/arch/anlogic/tribuf.ys +++ b/tests/arch/anlogic/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/common/add_sub.v similarity index 100% rename from tests/arch/anlogic/add_sub.v rename to tests/arch/common/add_sub.v diff --git a/tests/arch/ecp5/adffs.v b/tests/arch/common/adffs.v similarity index 100% rename from tests/arch/ecp5/adffs.v rename to tests/arch/common/adffs.v diff --git a/tests/arch/anlogic/counter.v b/tests/arch/common/counter.v similarity index 100% rename from tests/arch/anlogic/counter.v rename to tests/arch/common/counter.v diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/common/dffs.v similarity index 100% rename from tests/arch/anlogic/dffs.v rename to tests/arch/common/dffs.v diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/common/fsm.v similarity index 100% rename from tests/arch/anlogic/fsm.v rename to tests/arch/common/fsm.v diff --git a/tests/arch/anlogic/latches.v b/tests/arch/common/latches.v similarity index 100% rename from tests/arch/anlogic/latches.v rename to tests/arch/common/latches.v diff --git a/tests/arch/ecp5/logic.v b/tests/arch/common/logic.v similarity index 100% rename from tests/arch/ecp5/logic.v rename to tests/arch/common/logic.v diff --git a/tests/arch/ecp5/mul.v b/tests/arch/common/mul.v similarity index 100% rename from tests/arch/ecp5/mul.v rename to tests/arch/common/mul.v diff --git a/tests/arch/anlogic/mux.v b/tests/arch/common/mux.v similarity index 100% rename from tests/arch/anlogic/mux.v rename to tests/arch/common/mux.v diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/common/shifter.v similarity index 100% rename from tests/arch/anlogic/shifter.v rename to tests/arch/common/shifter.v diff --git a/tests/arch/efinix/tribuf.v b/tests/arch/common/tribuf.v similarity index 100% rename from tests/arch/efinix/tribuf.v rename to tests/arch/common/tribuf.v diff --git a/tests/arch/ecp5/add_sub.v b/tests/arch/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys index ee72d732f..d85ce792e 100644 --- a/tests/arch/ecp5/add_sub.ys +++ b/tests/arch/ecp5/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/arch/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys index c6780e565..01605df70 100644 --- a/tests/arch/ecp5/adffs.ys +++ b/tests/arch/ecp5/adffs.ys @@ -1,4 +1,4 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/ecp5/counter.v b/tests/arch/ecp5/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/ecp5/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index 8ef70778f..f9f60fbff 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/ecp5/dffs.v b/tests/arch/ecp5/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/ecp5/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys index a4f45d2fb..be97972db 100644 --- a/tests/arch/ecp5/dffs.ys +++ b/tests/arch/ecp5/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/ecp5/fsm.v b/tests/arch/ecp5/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/ecp5/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys index ded91e5f7..f834a4c6b 100644 --- a/tests/arch/ecp5/fsm.ys +++ b/tests/arch/ecp5/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/ecp5/latches.v b/tests/arch/ecp5/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/ecp5/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/ecp5/latches.ys b/tests/arch/ecp5/latches.ys index fc15a6910..3d011d74f 100644 --- a/tests/arch/ecp5/latches.ys +++ b/tests/arch/ecp5/latches.ys @@ -1,5 +1,4 @@ - -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/ecp5/logic.ys b/tests/arch/ecp5/logic.ys index 4f113a130..3298b198f 100644 --- a/tests/arch/ecp5/logic.ys +++ b/tests/arch/ecp5/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/arch/ecp5/mul.ys b/tests/arch/ecp5/mul.ys index 0a91f892e..2105be52c 100644 --- a/tests/arch/ecp5/mul.ys +++ b/tests/arch/ecp5/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top proc # Blocked by issue #1358 (Missing ECP5 simulation models) diff --git a/tests/arch/ecp5/mux.v b/tests/arch/ecp5/mux.v deleted file mode 100644 index 782424a9b..000000000 --- a/tests/arch/ecp5/mux.v +++ /dev/null @@ -1,66 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 8cfbd541b..92463aa32 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/ecp5/shifter.v b/tests/arch/ecp5/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/arch/ecp5/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys index e1901e1a8..3f0079f4a 100644 --- a/tests/arch/ecp5/shifter.ys +++ b/tests/arch/ecp5/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/ecp5/tribuf.v b/tests/arch/ecp5/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/arch/ecp5/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/arch/ecp5/tribuf.ys b/tests/arch/ecp5/tribuf.ys index a6e9c9598..0118705a2 100644 --- a/tests/arch/ecp5/tribuf.ys +++ b/tests/arch/ecp5/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten diff --git a/tests/arch/efinix/add_sub.v b/tests/arch/efinix/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/efinix/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys index 8bd28c68e..20523c059 100644 --- a/tests/arch/efinix/add_sub.ys +++ b/tests/arch/efinix/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check diff --git a/tests/arch/efinix/adffs.v b/tests/arch/efinix/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/arch/efinix/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys index 1069c6c5c..49dc7f256 100644 --- a/tests/arch/efinix/adffs.ys +++ b/tests/arch/efinix/adffs.ys @@ -1,4 +1,4 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/efinix/counter.v b/tests/arch/efinix/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/efinix/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys index 82e61d39b..d20b8ae27 100644 --- a/tests/arch/efinix/counter.ys +++ b/tests/arch/efinix/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/efinix/dffs.v b/tests/arch/efinix/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/efinix/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys index cdd288233..af787ab67 100644 --- a/tests/arch/efinix/dffs.ys +++ b/tests/arch/efinix/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/efinix/fsm.v b/tests/arch/efinix/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/efinix/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys index 2ec75215d..a8ba70fdb 100644 --- a/tests/arch/efinix/fsm.ys +++ b/tests/arch/efinix/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/efinix/latches.v b/tests/arch/efinix/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/efinix/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys index 899d024ce..1b1c00023 100644 --- a/tests/arch/efinix/latches.ys +++ b/tests/arch/efinix/latches.ys @@ -1,4 +1,4 @@ -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/efinix/logic.v b/tests/arch/efinix/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/efinix/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys index fdedb337b..76e98e079 100644 --- a/tests/arch/efinix/logic.ys +++ b/tests/arch/efinix/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check diff --git a/tests/arch/efinix/mux.v b/tests/arch/efinix/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/arch/efinix/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index 71a9681de..b46f641e1 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/efinix/shifter.v b/tests/arch/efinix/shifter.v deleted file mode 100644 index ce2c81dd2..000000000 --- a/tests/arch/efinix/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out << 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/efinix/shifter.ys b/tests/arch/efinix/shifter.ys index 1a6b5565c..54f71167f 100644 --- a/tests/arch/efinix/shifter.ys +++ b/tests/arch/efinix/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys index 2e2ab9e65..47904f2d5 100644 --- a/tests/arch/efinix/tribuf.ys +++ b/tests/arch/efinix/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc tribuf diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/ice40/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys index 4a998d98d..578ec0803 100644 --- a/tests/arch/ice40/add_sub.ys +++ b/tests/arch/ice40/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v deleted file mode 100644 index 09dc36001..000000000 --- a/tests/arch/ice40/adffs.v +++ /dev/null @@ -1,87 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre ) - if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys index 548060b66..e5dbabb43 100644 --- a/tests/arch/ice40/adffs.ys +++ b/tests/arch/ice40/adffs.ys @@ -1,11 +1,39 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff proc -flatten -equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNS -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFS -select -assert-count 2 t:SB_LUT4 -select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-none t:SB_DFFR %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFSS +select -assert-none t:SB_DFFSS %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNSR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/ice40/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index c65c21622..f112eb97d 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/arch/ice40/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys index ee7f884b1..b28a5a91f 100644 --- a/tests/arch/ice40/dffs.ys +++ b/tests/arch/ice40/dffs.ys @@ -1,10 +1,19 @@ -read_verilog dffs.v -hierarchy -top top +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFFE -select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D +select -assert-none t:SB_DFFE %% t:* %D \ No newline at end of file diff --git a/tests/arch/ice40/fsm.v b/tests/arch/ice40/fsm.v deleted file mode 100644 index 0605bd102..000000000 --- a/tests/arch/ice40/fsm.v +++ /dev/null @@ -1,73 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - -endmodule diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 4cc8629d6..5aacc6c73 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -1,10 +1,10 @@ -read_verilog fsm.v -hierarchy -top top +read_verilog ../common/fsm.v +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 2 t:SB_DFFESR select -assert-count 2 t:SB_DFFSR diff --git a/tests/arch/ice40/latches.v b/tests/arch/ice40/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/arch/ice40/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys index 708734e44..b06dd630b 100644 --- a/tests/arch/ice40/latches.ys +++ b/tests/arch/ice40/latches.ys @@ -1,12 +1,33 @@ -read_verilog latches.v +read_verilog ../common/latches.v +design -save read +hierarchy -top latchp proc -flatten # Can't run any sort of equivalence check because latches are blown to LUTs -#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check - -#design -load preopt synth_ice40 -cd top -select -assert-count 4 t:SB_LUT4 +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/logic.v b/tests/arch/ice40/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/ice40/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/ice40/logic.ys b/tests/arch/ice40/logic.ys index fc5e5b1d8..7432f5b1f 100644 --- a/tests/arch/ice40/logic.ys +++ b/tests/arch/ice40/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/mul.v b/tests/arch/ice40/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/arch/ice40/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 8a0822a84..9891b77d6 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/mux.v b/tests/arch/ice40/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/arch/ice40/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 182b49499..99822391d 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -1,8 +1,40 @@ -read_verilog mux.v +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 19 t:SB_LUT4 +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v deleted file mode 100644 index c55632552..000000000 --- a/tests/arch/ice40/shifter.v +++ /dev/null @@ -1,22 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin -`ifndef BUG - out <= out >> 1; - out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif - end - -endmodule diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys index 47d95d298..08ea64f3d 100644 --- a/tests/arch/ice40/shifter.ys +++ b/tests/arch/ice40/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/arch/ice40/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys index d1e1b3108..10cded954 100644 --- a/tests/arch/ice40/tribuf.ys +++ b/tests/arch/ice40/tribuf.ys @@ -1,9 +1,11 @@ -read_verilog tribuf.v -hierarchy -top top +read_verilog ../common/tribuf.v +hierarchy -top tristate proc +tribuf flatten +synth equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/xilinx/add_sub.v b/tests/arch/xilinx/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/xilinx/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index f06e7fa01..9dbddce47 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/arch/xilinx/adffs.v b/tests/arch/xilinx/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/arch/xilinx/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index 1923b9802..12c34415e 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -1,4 +1,4 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/xilinx/counter.v b/tests/arch/xilinx/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/xilinx/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 459541656..57b645d19 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/xilinx/dffs.v b/tests/arch/xilinx/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/xilinx/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index f1716dabb..0bba4858f 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/xilinx/fsm.v b/tests/arch/xilinx/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/xilinx/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index a9e94c2c0..d2b481421 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/xilinx/latches.v b/tests/arch/xilinx/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/xilinx/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index 3eb550a42..fe7887e8d 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -1,4 +1,4 @@ -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/xilinx/logic.v b/tests/arch/xilinx/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/xilinx/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index 9ae5993aa..c0f6da302 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/arch/xilinx/mul.v b/tests/arch/xilinx/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/arch/xilinx/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index 66a06efdc..d76814966 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/arch/xilinx/mux.v b/tests/arch/xilinx/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/arch/xilinx/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 420dece4e..821d0fab7 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/xilinx/shifter.v b/tests/arch/xilinx/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/arch/xilinx/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys index 84e16f41e..455437f18 100644 --- a/tests/arch/xilinx/shifter.ys +++ b/tests/arch/xilinx/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/arch/xilinx/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index c9cfb8546..4697703ca 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc tribuf From 477702b8c91bb7780ac80b25c8ad659cd40b445d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:20:35 +0200 Subject: [PATCH 5/8] Remove not needed tests --- tests/arch/ice40/alu.v | 19 ------------------- tests/arch/ice40/alu.ys | 11 ----------- tests/arch/ice40/div_mod.v | 13 ------------- tests/arch/ice40/div_mod.ys | 9 --------- 4 files changed, 52 deletions(-) delete mode 100644 tests/arch/ice40/alu.v delete mode 100644 tests/arch/ice40/alu.ys delete mode 100644 tests/arch/ice40/div_mod.v delete mode 100644 tests/arch/ice40/div_mod.ys diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/arch/ice40/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/arch/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/arch/ice40/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/arch/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D From 12383f37b2e1d72784e01db0431efc8882f25430 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:33:35 +0200 Subject: [PATCH 6/8] Common memory test now shared --- tests/arch/anlogic/memory.ys | 2 +- tests/arch/{anlogic => common}/memory.v | 0 tests/arch/ecp5/memory.v | 21 --------------------- tests/arch/ecp5/memory.ys | 2 +- tests/arch/efinix/memory.v | 21 --------------------- tests/arch/efinix/memory.ys | 2 +- tests/arch/ice40/memory.v | 21 --------------------- tests/arch/ice40/memory.ys | 2 +- tests/arch/xilinx/memory.v | 21 --------------------- tests/arch/xilinx/memory.ys | 2 +- 10 files changed, 5 insertions(+), 89 deletions(-) rename tests/arch/{anlogic => common}/memory.v (100%) delete mode 100644 tests/arch/ecp5/memory.v delete mode 100644 tests/arch/efinix/memory.v delete mode 100644 tests/arch/ice40/memory.v delete mode 100644 tests/arch/xilinx/memory.v diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys index 8c0ce844e..87b93c2fe 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/anlogic/memory.v b/tests/arch/common/memory.v similarity index 100% rename from tests/arch/anlogic/memory.v rename to tests/arch/common/memory.v diff --git a/tests/arch/ecp5/memory.v b/tests/arch/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/memory.ys index 9b475f122..c82b7b405 100644 --- a/tests/arch/ecp5/memory.ys +++ b/tests/arch/ecp5/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v deleted file mode 100644 index 5634d6507..000000000 --- a/tests/arch/efinix/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [8:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys index fe24b0a9b..6f6acdcde 100644 --- a/tests/arch/efinix/memory.ys +++ b/tests/arch/efinix/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ice40/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys index a66afbae6..c356e67fb 100644 --- a/tests/arch/ice40/memory.ys +++ b/tests/arch/ice40/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/xilinx/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys index 5402513a2..da1ed0e49 100644 --- a/tests/arch/xilinx/memory.ys +++ b/tests/arch/xilinx/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap From 9bd9db56c8ef8ca413f97086fd53609c50df343b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:50:24 +0200 Subject: [PATCH 7/8] Unify verilog style --- tests/arch/common/add_sub.v | 15 +++--- tests/arch/common/adffs.v | 54 ++++++++++---------- tests/arch/common/counter.v | 16 ++---- tests/arch/common/dffs.v | 18 +++---- tests/arch/common/fsm.v | 98 ++++++++++++++++++------------------- tests/arch/common/latches.v | 9 ++-- tests/arch/common/logic.v | 28 +++++------ tests/arch/common/mul.v | 12 ++--- tests/arch/common/mux.v | 75 +++++++++++++--------------- tests/arch/common/shifter.v | 9 +--- tests/arch/common/tribuf.v | 6 +-- 11 files changed, 153 insertions(+), 187 deletions(-) diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v index 177c32e30..77e5f5745 100644 --- a/tests/arch/common/add_sub.v +++ b/tests/arch/common/add_sub.v @@ -1,13 +1,12 @@ module top ( - input [3:0] x, - input [3:0] y, + input [3:0] x, + input [3:0] y, - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; + output [3:0] A, + output [3:0] B +); + assign A = x + y; + assign B = x - y; endmodule diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v index 223b52d21..576bd81a6 100644 --- a/tests/arch/common/adffs.v +++ b/tests/arch/common/adffs.v @@ -1,47 +1,43 @@ -module adff - ( input d, clk, clr, output reg q ); +module adff( input d, clk, clr, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; endmodule -module adffn - ( input d, clk, clr, output reg q ); +module adffn( input d, clk, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; endmodule -module dffs - ( input d, clk, pre, clr, output reg q ); +module dffs( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; endmodule -module ndffnr - ( input d, clk, pre, clr, output reg q ); +module ndffnr( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; endmodule diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 52852f8ac..97604d3d8 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -1,17 +1,11 @@ -module top ( -out, -clk, -reset -); +module top ( out, clk, reset ); output [7:0] out; input clk, reset; reg [7:0] out; always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - + if (reset) + out <= 8'b0; + end + out <= out + 1; endmodule diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v index 3418787c9..636252d16 100644 --- a/tests/arch/common/dffs.v +++ b/tests/arch/common/dffs.v @@ -1,15 +1,13 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; +module dff ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; endmodule -module dffe - ( input d, clk, en, output reg q ); +module dffe( input d, clk, en, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk ) - if ( en ) - q <= d; + always @( posedge clk ) + if ( en ) + q <= d; endmodule diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index 368fbaace..9d3fbb64a 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -1,55 +1,51 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; + module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + parameter SIZE = 3; + parameter IDLE = 3'b001; + parameter GNT0 = 3'b010; + parameter GNT1 = 3'b100; + parameter GNT2 = 3'b101; - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end + else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end endmodule diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v index adb5d5319..60b757103 100644 --- a/tests/arch/common/latches.v +++ b/tests/arch/common/latches.v @@ -1,19 +1,16 @@ -module latchp - ( input d, clk, en, output reg q ); +module latchp ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule -module latchn - ( input d, clk, en, output reg q ); +module latchn ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule -module latchsr - ( input d, clk, en, clr, pre, output reg q ); +module latchsr ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v index e5343cae0..c17899fa0 100644 --- a/tests/arch/common/logic.v +++ b/tests/arch/common/logic.v @@ -1,18 +1,16 @@ module top ( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 +); + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; endmodule diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index d5b48b1d7..437a91cfc 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,11 +1,9 @@ module top ( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; + input [5:0] x, + input [5:0] y, + output [11:0] A, +); + assign A = x * y; endmodule diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v index 27bc0bf0b..71c1ac7f2 100644 --- a/tests/arch/common/mux.v +++ b/tests/arch/common/mux.v @@ -8,51 +8,47 @@ module mux2 (S,A,B,Y); endmodule module mux4 ( S, D, Y ); + input[1:0] S; + input[3:0] D; + output Y; -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end + reg Y; + wire[1:0] S; + wire[3:0] D; + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase + end endmodule module mux8 ( S, D, Y ); + input[2:0] S; + input[7:0] D; + output Y; -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end + reg Y; + wire[2:0] S; + wire[7:0] D; + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase + end endmodule module mux16 (D, S, Y); @@ -60,6 +56,5 @@ module mux16 (D, S, Y); input [3:0] S; output Y; -assign Y = D[S]; - + assign Y = D[S]; endmodule diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index 04ae49d83..cace3b588 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,8 +1,4 @@ -module top ( -out, -clk, -in -); +module top(out, clk, in); output [7:0] out; input signed clk, in; reg signed [7:0] out = 0; @@ -11,6 +7,5 @@ in begin out <= out >> 1; out[7] <= in; - end - + end endmodule diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v index c64468253..e1d701611 100644 --- a/tests/arch/common/tribuf.v +++ b/tests/arch/common/tribuf.v @@ -1,8 +1,8 @@ -module tristate (en, i, o); +module tristate(en, i, o); input en; input i; output reg o; - + always @(en or i) - o <= (en)? i : 1'bZ; + o <= (en)? i : 1'bZ; endmodule From 190b40341abd73ab5edf0e6740b6526e9575253b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 13:15:36 +0200 Subject: [PATCH 8/8] fixed error --- tests/arch/common/counter.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 97604d3d8..9746fd701 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -6,6 +6,6 @@ module top ( out, clk, reset ); always @(posedge clk, posedge reset) if (reset) out <= 8'b0; - end + else out <= out + 1; endmodule