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Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
18 lines
235 B
Verilog
18 lines
235 B
Verilog
module top (
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out,
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clk,
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reset
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);
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output [7:0] out;
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input clk, reset;
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reg [7:0] out;
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always @(posedge clk, posedge reset)
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if (reset) begin
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out <= 8'b0 ;
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end else
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out <= out + 1;
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endmodule
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