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This commit is contained in:
Alain Dargelas 2025-03-10 14:44:14 -07:00
parent 6de80bc6b3
commit e1671b45b6
2 changed files with 48 additions and 2 deletions
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4
passes/opt/peepopt_sub_neg.pmg
View file

@ -20,8 +20,8 @@ code a b sub_y
bool b_signed = sub->getParam(ID::B_SIGNED).as_bool(); bool b_signed = sub->getParam(ID::B_SIGNED).as_bool();
// Fanout of each sub Y bit should be 1 (no bit-split) // Fanout of each sub Y bit should be 1 (no bit-split)
if (nusers(sub_y) != 2) if (nusers(sub_y) != 2)
reject; reject;
// Both operands need to be signed to be swapped // Both operands need to be signed to be swapped
if (!a_signed || !b_signed) if (!a_signed || !b_signed)

46
tests/peepopt/neg_sub.ys
View file

@ -100,3 +100,49 @@ select -assert-any t:$neg
select -assert-any t:$sub select -assert-any t:$sub
design -reset design -reset
log -pop log -pop
log -header "Negative case with disconnected intermediate signal (operator in the middle)"
log -push
design -reset
read_verilog <<EOF
module equation_example (
input signed [7:0] a,
input signed [7:0] b,
output signed [8:0] result
);
wire signed [8:0] difference;
wire signed [8:0] c;
assign difference = a - b;
assign c = ~difference;
assign result = - c;
endmodule
EOF
check -assert
equiv_opt -assert -post peepopt
select -assert-any t:$neg
select -assert-any t:$sub
design -reset
log -pop
log -header "Negative case with disconnected intermediate signal"
log -push
design -reset
read_verilog <<EOF
module equation_example (
input signed [7:0] a,
input signed [7:0] b,
output signed [8:0] result
);
wire signed [8:0] difference;
wire signed [8:0] c;
assign difference = a - b;
assign c = a + b ;
assign result = - c;
endmodule
EOF
check -assert
equiv_opt -assert -post peepopt
select -assert-any t:$neg
select -assert-any t:$sub
design -reset
log -pop