From e1671b45b68ed33d4e5b1ee9df23fc4575d7cdd0 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Mon, 10 Mar 2025 14:44:14 -0700 Subject: [PATCH] Code review --- passes/opt/peepopt_sub_neg.pmg | 4 +-- tests/peepopt/neg_sub.ys | 46 ++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/passes/opt/peepopt_sub_neg.pmg b/passes/opt/peepopt_sub_neg.pmg index 0b23c1ea4..24e617052 100644 --- a/passes/opt/peepopt_sub_neg.pmg +++ b/passes/opt/peepopt_sub_neg.pmg @@ -20,8 +20,8 @@ code a b sub_y bool b_signed = sub->getParam(ID::B_SIGNED).as_bool(); // Fanout of each sub Y bit should be 1 (no bit-split) - if (nusers(sub_y) != 2) - reject; + if (nusers(sub_y) != 2) + reject; // Both operands need to be signed to be swapped if (!a_signed || !b_signed) diff --git a/tests/peepopt/neg_sub.ys b/tests/peepopt/neg_sub.ys index 17980f632..5926f2b6b 100644 --- a/tests/peepopt/neg_sub.ys +++ b/tests/peepopt/neg_sub.ys @@ -100,3 +100,49 @@ select -assert-any t:$neg select -assert-any t:$sub design -reset log -pop + +log -header "Negative case with disconnected intermediate signal (operator in the middle)" +log -push +design -reset +read_verilog <