diff --git a/passes/opt/peepopt_sub_neg.pmg b/passes/opt/peepopt_sub_neg.pmg
index 0b23c1ea4..24e617052 100644
--- a/passes/opt/peepopt_sub_neg.pmg
+++ b/passes/opt/peepopt_sub_neg.pmg
@@ -20,8 +20,8 @@ code a b sub_y
 	bool b_signed = sub->getParam(ID::B_SIGNED).as_bool();
 
 	// Fanout of each sub Y bit should be 1 (no bit-split)
-  if (nusers(sub_y) != 2)
- 		reject;
+	if (nusers(sub_y) != 2)
+		reject;
 
 	// Both operands need to be signed to be swapped
 	if (!a_signed || !b_signed)
diff --git a/tests/peepopt/neg_sub.ys b/tests/peepopt/neg_sub.ys
index 17980f632..5926f2b6b 100644
--- a/tests/peepopt/neg_sub.ys
+++ b/tests/peepopt/neg_sub.ys
@@ -100,3 +100,49 @@ select -assert-any t:$neg
 select -assert-any t:$sub
 design -reset
 log -pop
+
+log -header "Negative case with disconnected intermediate signal (operator in the middle)"
+log -push
+design -reset
+read_verilog <<EOF
+module equation_example (
+  input signed [7:0] a,
+  input signed [7:0] b,
+  output signed [8:0] result
+);
+  wire signed [8:0] difference;
+  wire signed [8:0] c;
+  assign difference = a - b;
+  assign c = ~difference;
+  assign result = - c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert -post peepopt
+select -assert-any t:$neg
+select -assert-any t:$sub
+design -reset
+log -pop
+
+log -header "Negative case with disconnected intermediate signal"
+log -push
+design -reset
+read_verilog <<EOF
+module equation_example (
+  input signed [7:0] a,
+  input signed [7:0] b,
+  output signed [8:0] result
+);
+  wire signed [8:0] difference;
+  wire signed [8:0] c;
+  assign difference = a - b;
+  assign c = a + b ;
+  assign result = - c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert -post peepopt
+select -assert-any t:$neg
+select -assert-any t:$sub
+design -reset
+log -pop