From c30fd46ea32a132b2524acd98d5a45a97528d725 Mon Sep 17 00:00:00 2001
From: Xing Guo <higuoxing@gmail.com>
Date: Fri, 5 Sep 2025 11:10:25 +0800
Subject: [PATCH 1/2] Fix handling of cases that look like sva labels again.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels.  After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:

```
➜  /tmp yosys -p 'read -sv a1.v'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)

-- Running command `read -sv a1.v' --

1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜  /tmp cat a1.v
module test(input wire A);
  localparam TEST = 1;
  always_comb begin
    case (A)
      TEST: assert(1);
    endcase
  end
endmodule
```

We encountered this issue before but with a different error message[^1],

[^1]: https://github.com/YosysHQ/yosys/issues/862
---
 frontends/verilog/verilog_parser.y | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 392d8921a..c77d0a7cf 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -3023,7 +3023,8 @@ case_expr_list:
 		SET_AST_NODE_LOC(node, @1, @1);
 	} |
 	TOK_SVA_LABEL {
-		AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
+		AstNode* node = extra->saveChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
+		node->str = *$1;
 		SET_AST_NODE_LOC(node, @1, @1);
 	} |
 	expr {

From 62120bda0661102ba60801a871ab5c9f336a8aa6 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 5 Sep 2025 12:34:38 +0200
Subject: [PATCH 2/2] verilog: test cases that look like SVA labels #862

---
 tests/verilog/sva-in-case-expr.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/verilog/sva-in-case-expr.ys

diff --git a/tests/verilog/sva-in-case-expr.ys b/tests/verilog/sva-in-case-expr.ys
new file mode 100644
index 000000000..e326e2bfb
--- /dev/null
+++ b/tests/verilog/sva-in-case-expr.ys
@@ -0,0 +1,10 @@
+read_verilog -sv <<EOT
+module test(input wire A);
+  localparam TEST = 1;
+  always_comb begin
+    case (A)
+      TEST: assert(1);
+    endcase
+  end
+endmodule
+EOT