diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 392d8921a..c77d0a7cf 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -3023,7 +3023,8 @@ case_expr_list:
 		SET_AST_NODE_LOC(node, @1, @1);
 	} |
 	TOK_SVA_LABEL {
-		AstNode* node = extra->pushChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
+		AstNode* node = extra->saveChild(std::make_unique<AstNode>(@$, AST_IDENTIFIER));
+		node->str = *$1;
 		SET_AST_NODE_LOC(node, @1, @1);
 	} |
 	expr {
diff --git a/tests/verilog/sva-in-case-expr.ys b/tests/verilog/sva-in-case-expr.ys
new file mode 100644
index 000000000..e326e2bfb
--- /dev/null
+++ b/tests/verilog/sva-in-case-expr.ys
@@ -0,0 +1,10 @@
+read_verilog -sv <<EOT
+module test(input wire A);
+  localparam TEST = 1;
+  always_comb begin
+    case (A)
+      TEST: assert(1);
+    endcase
+  end
+endmodule
+EOT