Cleanups and improvements in examples/cmos/

examples/cmos/.gitignore

@@ -0,0 +1,4 @@
+counter_tb
+counter_tb.vcd
+synth.sp
+synth.v

examples/cmos/README

@@ -1,7 +1,7 @@
 
-In this directory you will find out, how to generate a spice output
+In this directory contains an example for generating a spice output using two
-operating in two modes, analog or event-driven mode supported by ngspice
+different spice modes, normal analog transient simulation and event-driven
-xspice sub-module.
+digital simulation as supported by ngspice xspice sub-module.
 
 Each test bench can be run separately by either running:
 
@@ -9,4 +9,5 @@ Each test bench can be run separately by either running:
 - testbench_digital.sh for mixed-signal digital simulation.
 
 The later case also includes pure verilog simulation using the iverilog
-and gtkwave to represent the results.
+and gtkwave for comparison.
+

examples/cmos/counter_tb.gtkw

@@ -0,0 +1,5 @@
+[dumpfile] "counter_tb.vcd"
+counter_tb.clk
+counter_tb.count[2:0]
+counter_tb.en
+counter_tb.reset

examples/cmos/testbench.sh

@@ -5,6 +5,3 @@ set -ex
 ../../yosys counter.ys
 ngspice testbench.sp
 
-# requires ngspice with xspice support enabled:
-#ngspice testbench_digital.sp
-

examples/cmos/testbench_digital.sh

@@ -1,15 +1,15 @@
 #!/bin/bash
 
+set -ex
+
 # iverlog simulation
 echo "Doing Verilog simulation with iverilog"
-iverilog -o dsn counter.v counter_tb.v 
+iverilog -o counter_tb counter.v counter_tb.v 
-./dsn -lxt2
+./counter_tb; gtkwave counter_tb.gtkw &
-gtkwave counter_tb.vcd &
 
 # yosys synthesis
-set -ex
-
 ../../yosys counter_digital.ys
 
 # requires ngspice with xspice support enabled:
 ngspice testbench_digital.sp
+