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https://github.com/YosysHQ/yosys
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16 lines
305 B
Bash
16 lines
305 B
Bash
#!/bin/bash
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set -ex
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# iverlog simulation
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echo "Doing Verilog simulation with iverilog"
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iverilog -o counter_tb counter.v counter_tb.v
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./counter_tb; gtkwave counter_tb.gtkw &
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# yosys synthesis
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../../yosys counter_digital.ys
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# requires ngspice with xspice support enabled:
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ngspice testbench_digital.sp
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