mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
bit split initial splitfanout call
This commit is contained in:
parent
4b598e317b
commit
d4e4ece9fe
1 changed files with 11 additions and 3 deletions
|
@ -704,8 +704,12 @@ struct AnnotateCellFanout : public ScriptPass {
|
||||||
RTLIL::SigSpec actual = conn.second;
|
RTLIL::SigSpec actual = conn.second;
|
||||||
if (cell->output(portName)) {
|
if (cell->output(portName)) {
|
||||||
RTLIL::SigSpec cellOutSig = sigmap(actual);
|
RTLIL::SigSpec cellOutSig = sigmap(actual);
|
||||||
fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, cellOutSig, fanout,
|
for (int i = 0; i < cellOutSig.size(); i++) {
|
||||||
limit, debug);
|
SigSpec bit_sig = cellOutSig.extract(i, 1);
|
||||||
|
int bitfanout = sig2CellsInFanout[bit_sig].size();
|
||||||
|
fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, bit_sig,
|
||||||
|
bitfanout, limit, debug);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
fixedFanout = true;
|
fixedFanout = true;
|
||||||
|
@ -759,7 +763,11 @@ struct AnnotateCellFanout : public ScriptPass {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
for (auto sig : sigsToFix) {
|
for (auto sig : sigsToFix) {
|
||||||
fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, sig.first, sig.second, limit, debug);
|
for (int i = 0; i < sig.first.size(); i++) {
|
||||||
|
SigSpec bit_sig = sig.first.extract(i, 1);
|
||||||
|
int bitfanout = sig2CellsInFanout[bit_sig].size();
|
||||||
|
fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, bit_sig, bitfanout, limit, debug);
|
||||||
|
}
|
||||||
fixedFanout = true;
|
fixedFanout = true;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue