From d4e4ece9fe3b0513aba9608c0e808b549a431134 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Thu, 6 Mar 2025 10:47:27 -0800 Subject: [PATCH] bit split initial splitfanout call --- passes/silimate/annotate_cell_fanout.cc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/passes/silimate/annotate_cell_fanout.cc b/passes/silimate/annotate_cell_fanout.cc index 490750bf0..e268e31ff 100644 --- a/passes/silimate/annotate_cell_fanout.cc +++ b/passes/silimate/annotate_cell_fanout.cc @@ -704,8 +704,12 @@ struct AnnotateCellFanout : public ScriptPass { RTLIL::SigSpec actual = conn.second; if (cell->output(portName)) { RTLIL::SigSpec cellOutSig = sigmap(actual); - fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, cellOutSig, fanout, - limit, debug); + for (int i = 0; i < cellOutSig.size(); i++) { + SigSpec bit_sig = cellOutSig.extract(i, 1); + int bitfanout = sig2CellsInFanout[bit_sig].size(); + fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, bit_sig, + bitfanout, limit, debug); + } } } fixedFanout = true; @@ -759,7 +763,11 @@ struct AnnotateCellFanout : public ScriptPass { } } for (auto sig : sigsToFix) { - fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, sig.first, sig.second, limit, debug); + for (int i = 0; i < sig.first.size(); i++) { + SigSpec bit_sig = sig.first.extract(i, 1); + int bitfanout = sig2CellsInFanout[bit_sig].size(); + fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, bit_sig, bitfanout, limit, debug); + } fixedFanout = true; } }