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https://github.com/YosysHQ/yosys
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getfanout factor
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f65d822935
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@ -77,6 +77,18 @@ RTLIL::IdString generateSigSpecName(Module *module, const RTLIL::SigSpec &sigspe
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return RTLIL::IdString(ss.str());
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}
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// Collect fanout cells of a given sig, collects all bits connections
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void getFanout(dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout, SigMap &sigmap, SigSpec sig, std::set<Cell *> &fanoutcells)
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{
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fanoutcells = sig2CellsInFanout[sig];
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for (int i = 0; i < sig.size(); i++) {
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SigSpec bit_sig = sig.extract(i, 1);
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for (Cell *c : sig2CellsInFanout[sigmap(bit_sig)]) {
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fanoutcells.insert(c);
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}
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}
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}
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// Signal cell driver(s), precompute a cell output signal to a cell map
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void sigCellDrivers(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanout,
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dict<RTLIL::SigSpec, std::set<Cell *>> &sig2CellsInFanin)
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@ -364,13 +376,8 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec, std::
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}
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// Cumulate all cells in the fanout of this cell
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std::set<Cell *> fanoutcells = sig2CellsInFanout[sigToBuffer];
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for (int i = 0; i < sigToBuffer.size(); i++) {
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SigSpec bit_sig = sigToBuffer.extract(i, 1);
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for (Cell *c : sig2CellsInFanout[sigmap(bit_sig)]) {
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fanoutcells.insert(c);
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}
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}
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std::set<Cell *> fanoutcells;
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getFanout(sig2CellsInFanout, sigmap, sigToBuffer, fanoutcells);
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// Fix input connections to cells in fanout of buffer to point to the inserted buffer
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for (Cell *fanoutcell : fanoutcells) {
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@ -635,7 +642,7 @@ struct AnnotateCellFanout : public ScriptPass {
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}
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for (auto module : design->selected_modules()) {
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bool fixedFanout = false;
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std::map<Cell*, Wire*> insertedBuffers;
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std::map<Cell *, Wire *> insertedBuffers;
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{
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// Calculate fanout
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SigMap sigmap(module);
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@ -697,7 +704,8 @@ struct AnnotateCellFanout : public ScriptPass {
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RTLIL::SigSpec actual = conn.second;
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if (cell->output(portName)) {
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RTLIL::SigSpec cellOutSig = sigmap(actual);
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fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, cellOutSig, fanout, limit, debug);
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fixfanout(module, sigmap, sig2CellsInFanout, insertedBuffers, cellOutSig, fanout,
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limit, debug);
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}
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}
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fixedFanout = true;
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@ -769,13 +777,8 @@ struct AnnotateCellFanout : public ScriptPass {
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// Final cleanup, remove buffers of 1
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if ((fanout == 1) && insertedBuffers.find(cell) != insertedBuffers.end()) {
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SigSpec bufferOut = insertedBuffers.find(cell)->second;
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std::set<Cell *> fanoutcells = sig2CellsInFanout[bufferOut];
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for (int i = 0; i < bufferOut.size(); i++) {
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SigSpec bit_sig = bufferOut.extract(i, 1);
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for (Cell *c : sig2CellsInFanout[sigmap(bit_sig)]) {
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fanoutcells.insert(c);
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}
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}
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std::set<Cell *> fanoutcells;
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getFanout(sig2CellsInFanout, sigmap, bufferOut, fanoutcells);
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removeBuffer(module, sigmap, fanoutcells, insertedBuffers, cell, debug);
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continue;
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}
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