diff --git a/tests/various/bug4865.ys b/tests/various/bug4865.ys
index ac5a459d8..b747c59a7 100644
--- a/tests/various/bug4865.ys
+++ b/tests/various/bug4865.ys
@@ -1,5 +1,6 @@
 read_rtlil << EOF
 
+
 autoidx 524
 
 attribute \top 1
@@ -10,8 +11,10 @@ module \main
   attribute \force_downto 1
   wire width 18 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0]
 
-  wire width 14 $delete_wire$514
+  wire width 12 $delete_wire$514
 
+  wire width 4 $test
+  
   attribute \module_not_derived 1
   cell \SB_MAC16 $verific$mult_4$garbage/usb.v:12$388.etc.sliceB[0].mul
     parameter \A_REG 1'0
@@ -36,7 +39,7 @@ module \main
     parameter \TOP_8x8_MULT_REG 1'0
     connect \A 16'x
     connect \B 16'x
-    connect \O { $delete_wire$514 $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:2] 2'x}
+    connect \O {  $test $delete_wire$514 14'x $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0] }
   end
 
   cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.etc.sliceA.last.$add$/home/emil/pulls/yosys/share/mul2dsp.v:216$483
@@ -46,17 +49,17 @@ module \main
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 19
     connect \A 18'x
-    connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [17:16]
+    connect \B $verific$mult_4$garbage/usb.v:12$388.etc.blk.partial[0] [1:0]
     connect \Y 19'x
   end
 
   cell $add $techmap$verific$mult_4$garbage/usb.v:12$388.$add$/home/emil/pulls/yosys/share/mul2dsp.v:173$480
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 14
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 2
     parameter \Y_WIDTH 2
-    connect \A $delete_wire$514
+    connect \A $delete_wire$514 [1:0]
     connect \B 2'x
     connect \Y 2'x
   end