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minor changes

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This commit is contained in:
Artur Swiderski 2020-12-06 12:24:44 +01:00
parent 1452cd88e8
commit cab1f9872b
4 changed files with 18 additions and 40 deletions
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4
techlibs/intel_le/common/mem_sim.v
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@ -5,8 +5,8 @@
module MISTRAL_M9K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 9;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;