From cab1f9872bb44f0cf9b9618ab1c99fe2e87cc686 Mon Sep 17 00:00:00 2001 From: Artur Swiderski Date: Sun, 6 Dec 2020 12:24:44 +0100 Subject: [PATCH] minor changes --- techlibs/intel_le/common/arith_le_map.v | 23 +---------------------- techlibs/intel_le/common/le_sim.v | 12 +++++------- techlibs/intel_le/common/mem_sim.v | 4 ++-- tests/arch/intel_le/mux.ys | 19 ++++++++++--------- 4 files changed, 18 insertions(+), 40 deletions(-) diff --git a/techlibs/intel_le/common/arith_le_map.v b/techlibs/intel_le/common/arith_le_map.v index 07170c4c0..2a3c7cebe 100644 --- a/techlibs/intel_le/common/arith_le_map.v +++ b/techlibs/intel_le/common/arith_le_map.v @@ -39,17 +39,7 @@ generate if (_TECHMAP_CONSTMSK_CI_ == 1) begin assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_; end else begin - /* - MISTRAL_ALUT_ARITH #( - .LUT(16'b1010_1010_1010_1010), // Q = A - ) le_start ( - .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1), - .CI(1'b0), - .SO(), - .CO(LE_CARRY[0]) - ); - */ assign LE_CARRY[0] = CI; end endgenerate @@ -57,21 +47,10 @@ endgenerate // Carry chain genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - /* - MISTRAL_ALUT_ARITH #( - .LUT(16'b0110_0110_0110_0110), // Q = A ? ~B : B - .sum_lutc_input("cin") - ) le_not_i ( - .A(BI), .B(BX[i]), .C(1'b0), .D(1'b0), - .CI(1'b0), - .SO(BTOADDER[i]), - .CO() - ); - */ MISTRAL_ALUT_ARITH #( .LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI - // CARRYi+1 = A and B or A and CI or B and CI + // CARRYi+1 = A and B or A and CI or B and CI ) le_i ( .A(AA[i]), .B(BB[i]), .C(1'b1), .D(1'b1), diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v index 4ac39e617..eeaafaa32 100644 --- a/techlibs/intel_le/common/le_sim.v +++ b/techlibs/intel_le/common/le_sim.v @@ -34,7 +34,7 @@ module MISTRAL_ALUT4(input A, B, C, D, output Q); parameter [15:0] LUT = 16'h0000; -`ifdef cycloneiv +`ifdef cycloneiv specify (A => Q) = 319; (B => Q) = 323; @@ -98,7 +98,7 @@ module MISTRAL_ALUT_ARITH(input A, B, C, D, (* abc9_carry *) input CI, output SO parameter LUT = 16'h0000; -`ifdef cycloneiv +`ifdef cycloneiv specify (A => SO) = 1342; (B => SO) = 1323; @@ -106,11 +106,9 @@ specify (D => SO) = 887; (CI => SO) = 368; - (A => CO) = 1082; - (B => CO) = 1062; - (C => CO) = 813; - (D => CO) = 866; - (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM) + (A => CO) = 376; + (B => CO) = 385; + (CI => CO) = 200; endspecify `endif wire q0, q1; diff --git a/techlibs/intel_le/common/mem_sim.v b/techlibs/intel_le/common/mem_sim.v index 66bc4f82c..b2734b161 100644 --- a/techlibs/intel_le/common/mem_sim.v +++ b/techlibs/intel_le/common/mem_sim.v @@ -5,8 +5,8 @@ module MISTRAL_M9K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); -parameter CFG_ABITS = 10; -parameter CFG_DBITS = 10; +parameter CFG_ABITS = 9; +parameter CFG_DBITS = 9; input CLK1; input [CFG_ABITS-1:0] A1ADDR, B1ADDR; diff --git a/tests/arch/intel_le/mux.ys b/tests/arch/intel_le/mux.ys index 5dd5c8e84..7c4a4bb33 100644 --- a/tests/arch/intel_le/mux.ys +++ b/tests/arch/intel_le/mux.ys @@ -17,8 +17,10 @@ proc equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 3 t:MISTRAL_ALUT3 -select -assert-none t:MISTRAL_ALUT3 %% t:* %D +select -assert-count 1 t:MISTRAL_ALUT3 +select -assert-count 2 t:MISTRAL_ALUT4 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D + design -load read @@ -27,9 +29,9 @@ proc equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:MISTRAL_ALUT3 -select -assert-count 3 t:MISTRAL_ALUT4 -select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D +select -assert-count 2 t:MISTRAL_ALUT2 +select -assert-count 5 t:MISTRAL_ALUT4 +select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D design -load read @@ -38,8 +40,7 @@ proc equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneiv # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT2 -select -assert-max 6 t:MISTRAL_ALUT3 -select -assert-max 7 t:MISTRAL_ALUT4 -select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D +select -assert-max 4 t:MISTRAL_ALUT3 +select -assert-max 9 t:MISTRAL_ALUT4 +select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D