mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 19:35:53 +00:00
Code Activity

minor changes

Browse source
This commit is contained in:
Artur Swiderski 2020-12-06 12:24:44 +01:00
parent 1452cd88e8
commit cab1f9872b
4 changed files with 18 additions and 40 deletions
Download patch file Download diff file Expand all files Collapse all files

23
techlibs/intel_le/common/arith_le_map.v
View file

@ -39,17 +39,7 @@ generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign LE_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
/*
MISTRAL_ALUT_ARITH #(
.LUT(16'b1010_1010_1010_1010), // Q = A
) le_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.SO(),
.CO(LE_CARRY[0])
);
*/
assign LE_CARRY[0] = CI;
end
endgenerate
@ -57,21 +47,10 @@ endgenerate
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
/*
MISTRAL_ALUT_ARITH #(
.LUT(16'b0110_0110_0110_0110), // Q = A ? ~B : B
.sum_lutc_input("cin")
) le_not_i (
.A(BI), .B(BX[i]), .C(1'b0), .D(1'b0),
.CI(1'b0),
.SO(BTOADDER[i]),
.CO()
);
*/
MISTRAL_ALUT_ARITH #(
.LUT(16'b1001_0110_1110_1000), // SUM = A xor B xor CI
// CARRYi+1 = A and B or A and CI or B and CI
// CARRYi+1 = A and B or A and CI or B and CI
) le_i (
.A(AA[i]), .B(BB[i]), .C(1'b1), .D(1'b1),