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Emit latch warning.

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This commit is contained in:
nella 2026-06-17 11:27:43 +02:00
parent a46bc77eeb
commit c814ef35e3
7 changed files with 16 additions and 1 deletions
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1
techlibs/efinix/synth_efinix.cc
View file

@ -190,6 +190,7 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_ffs")) if (check_label("map_ffs"))
{ {
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x"); run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
run("check -nolatches");
run("techmap -D NO_LUT -map +/efinix/cells_map.v"); run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef"); run("opt_expr -mux_undef");
run("simplemap"); run("simplemap");

1
techlibs/fabulous/synth_fabulous.cc
View file

@ -359,6 +359,7 @@ struct SynthPass : public ScriptPass
} else { } else {
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff"); run("dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x", "without -complex-dff");
} }
run("check -nolatches");
run("techmap -map +/fabulous/latches_map.v"); run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v"); run("techmap -map +/fabulous/ff_map.v");
if (help_mode) { if (help_mode) {

1
techlibs/ice40/synth_ice40.cc
View file

@ -406,6 +406,7 @@ struct SynthIce40Pass : public ScriptPass
run("abc", " (only if -abc2)"); run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)"); run("ice40_opt", "(only if -abc2)");
} }
run("check -nolatches");
run("techmap -map +/ice40/latches_map.v"); run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) { if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)"); run("simplemap", " (if -noabc or -flowmap)");

4
techlibs/lattice/synth_lattice.cc
View file

@ -531,8 +531,10 @@ struct SynthLatticePass : public ScriptPass
{ {
if (abc2 || help_mode) if (abc2 || help_mode)
run("abc", " (only if -abc2)"); run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) if (!asyncprld || help_mode) {
run("check -nolatches", "(skip if -asyncprld)");
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
}
if (abc9) { if (abc9) {
std::string abc9_opts; std::string abc9_opts;

1
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -325,6 +325,7 @@ struct SynthNanoXplorePass : public ScriptPass
dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use); dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use);
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge"); run("opt_merge");
run("check -nolatches");
run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v"); run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef"); run("opt_expr -undriven -mux_undef");

1
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -315,6 +315,7 @@ struct SynthQuickLogicPass : public ScriptPass {
} }
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
run("check -nolatches");
run("techmap -map " + lib_path + family + "/latches_map.v"); run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) { if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");

8
tests/various/synth_latch_warning.ys Normal file
View file

@ -0,0 +1,8 @@
read_verilog <<EOT
module top(input d, en, output reg q);
always @* if (en) q = d;
endmodule
EOT
logger -expect warning "is a latch of type" 1
synth_ice40
logger -check-expected