mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-19 15:26:29 +00:00
8 lines
178 B
Text
8 lines
178 B
Text
read_verilog <<EOT
|
|
module top(input d, en, output reg q);
|
|
always @* if (en) q = d;
|
|
endmodule
|
|
EOT
|
|
logger -expect warning "is a latch of type" 1
|
|
synth_ice40
|
|
logger -check-expected
|