mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Revert "verilog: fix string literal regular expression (#5187)"

Browse source 
This reverts commit 834a7294b7.
This commit is contained in:
Emil J. Tywoniak 2025-07-10 21:15:38 +02:00
parent dc204dc909
commit bb08919105
2 changed files with 1 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

5
tests/verilog/bug5160.v
View file

@ -1,5 +0,0 @@
// Regression test for bug mentioned in #5160:
// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
module top;
initial $display( "\\" );
endmodule