yosys/tests/verilog/bug5160.v at dc204dc9095135a16cbb4713e311f08a7ceca629 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-07-19 19:02:04 +00:00

Emil J. Tywoniak dc204dc909 Revert "verilog: add support for SystemVerilog string literals."

This reverts commit 5feb1a1752.

2025-07-10 21:14:38 +02:00

5 lines

169 B

Verilog

Raw Blame History

 // Regression test for bug mentioned in #5160:
 // https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
 module top;
     initial $display( "\\" );
 endmodule