From bb08919105c5e1da4710becb4e4d087c5314003f Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 10 Jul 2025 21:15:38 +0200 Subject: [PATCH] Revert "verilog: fix string literal regular expression (#5187)" This reverts commit 834a7294b7c790612e9d1a686b374130b43d814e. --- frontends/verilog/verilog_lexer.l | 2 +- tests/verilog/bug5160.v | 5 ----- 2 files changed, 1 insertion(+), 6 deletions(-) delete mode 100644 tests/verilog/bug5160.v diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 40162b8d3..8148748d8 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s } \" { BEGIN(STRING); } -([^\\"]|\\.)+ { yymore(); real_location = old_location; } +([^\"]|\\.)+ { yymore(); real_location = old_location; } \" { BEGIN(0); char *yystr = strdup(yytext); diff --git a/tests/verilog/bug5160.v b/tests/verilog/bug5160.v deleted file mode 100644 index 5b141a360..000000000 --- a/tests/verilog/bug5160.v +++ /dev/null @@ -1,5 +0,0 @@ -// Regression test for bug mentioned in #5160: -// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084 -module top; - initial $display( "\\" ); -endmodule