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fixup! messy

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This commit is contained in:
Emil J. Tywoniak 2025-05-26 11:09:43 +02:00
parent 71c64ff142
commit b962aa9171
1 changed files with 3 additions and 5 deletions
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8
tests/arch/microchip/reduce.ys
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@ -22,9 +22,7 @@ module reduce(
assign Y = ^data;
endmodule
EOT
read_verilog -lib -specify +/microchip/cells_sim.v
dump
# synth_microchip -top reduce -family polarfire -noiopad
# select -assert-count 1 t:XOR8
# select -assert-none t:XOR8 %% t:* %D
synth_microchip -top reduce -family polarfire -noiopad
select -assert-count 1 t:XOR8
select -assert-none t:XOR8 %% t:* %D