diff --git a/tests/arch/microchip/reduce.ys b/tests/arch/microchip/reduce.ys
index d00797dc4..ab19f5a35 100644
--- a/tests/arch/microchip/reduce.ys
+++ b/tests/arch/microchip/reduce.ys
@@ -22,9 +22,7 @@ module reduce(
 	assign Y = ^data;
 endmodule
 EOT
-read_verilog -lib -specify +/microchip/cells_sim.v
-dump
-# synth_microchip -top reduce -family polarfire -noiopad
-# select -assert-count 1 t:XOR8
-# select -assert-none t:XOR8 %% t:* %D
+synth_microchip -top reduce -family polarfire -noiopad
+select -assert-count 1 t:XOR8
+select -assert-none t:XOR8 %% t:* %D