From b962aa91711f41ecf53ac7c204bc395c2dc226ad Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 26 May 2025 11:09:43 +0200 Subject: [PATCH] fixup! messy --- tests/arch/microchip/reduce.ys | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/tests/arch/microchip/reduce.ys b/tests/arch/microchip/reduce.ys index d00797dc4..ab19f5a35 100644 --- a/tests/arch/microchip/reduce.ys +++ b/tests/arch/microchip/reduce.ys @@ -22,9 +22,7 @@ module reduce( assign Y = ^data; endmodule EOT -read_verilog -lib -specify +/microchip/cells_sim.v -dump -# synth_microchip -top reduce -family polarfire -noiopad -# select -assert-count 1 t:XOR8 -# select -assert-none t:XOR8 %% t:* %D +synth_microchip -top reduce -family polarfire -noiopad +select -assert-count 1 t:XOR8 +select -assert-none t:XOR8 %% t:* %D