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Update passes/techmap to avoid bits()

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This commit is contained in:
Robert O'Callahan 2025-08-28 03:53:51 +00:00
parent 510eac4ad0
commit a8cc9202b9
6 changed files with 21 additions and 17 deletions
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11
passes/techmap/abc9_ops.cc
View file

@ -1216,7 +1216,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
auto Qi = initmap(Q); auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init); auto it = Qi.wire->attributes.find(ID::init);
if (it != Qi.wire->attributes.end()) if (it != Qi.wire->attributes.end())
it->second.bits()[Qi.offset] = State::Sx; it->second.set(Qi.offset, State::Sx);
} }
else if (cell->type.in(ID($_AND_), ID($_NOT_))) else if (cell->type.in(ID($_AND_), ID($_NOT_)))
module->remove(cell); module->remove(cell);
@ -1526,8 +1526,11 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
log_assert(index < GetSize(A)); log_assert(index < GetSize(A));
int i = 0; int i = 0;
while (i < GetSize(mask)) { while (i < GetSize(mask)) {
for (int j = 0; j < (1 << index); j++) for (int j = 0; j < (1 << index); j++) {
std::swap(mask.bits()[i+j], mask.bits()[i+j+(1 << index)]); State bit = mask[i+j];
mask.set(i+j, mask[i+j+(1 << index)]);
mask.set(i+j+(1 << index), bit);
}
i += 1 << (index+1); i += 1 << (index+1);
} }
A[index] = y_bit; A[index] = y_bit;
@ -1542,7 +1545,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// and get cleaned away // and get cleaned away
clone_lut: clone_lut:
driver_mask = driver_lut->getParam(ID::LUT); driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits()) { for (auto b : driver_mask) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1; if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0; else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
} }

6
passes/techmap/dffinit.cc
View file

@ -118,13 +118,13 @@ struct DffinitPass : public Pass {
for (int i = 0; i < GetSize(sig); i++) { for (int i = 0; i < GetSize(sig); i++) {
if (initval[i] == State::Sx) if (initval[i] == State::Sx)
continue; continue;
while (GetSize(value) <= i) if (GetSize(value) <= i)
value.bits().push_back(State::S0); value.resize(i + 1, State::S0);
if (noreinit && value[i] != State::Sx && value[i] != initval[i]) if (noreinit && value[i] != State::Sx && value[i] != initval[i])
log_error("Trying to assign a different init value for %s.%s.%s which technically " log_error("Trying to assign a different init value for %s.%s.%s which technically "
"have a conflicted init value.\n", "have a conflicted init value.\n",
log_id(module), log_id(cell), log_id(it.second)); log_id(module), log_id(cell), log_id(it.second));
value.bits()[i] = initval[i]; value.set(i, initval[i]);
} }
if (highlow_mode && GetSize(value) != 0) { if (highlow_mode && GetSize(value) != 0) {

8
passes/techmap/dfflegalize.cc
View file

@ -869,17 +869,17 @@ struct DffLegalizePass : public Pass {
if (ff.has_arst) { if (ff.has_arst) {
if (ff.val_arst[i] == State::Sx) { if (ff.val_arst[i] == State::Sx) {
if (!(supported & (mask << 8))) if (!(supported & (mask << 8)))
ff.val_arst.bits()[i] = State::S0; ff.val_arst.set(i, State::S0);
if (!(supported & (mask << 4))) if (!(supported & (mask << 4)))
ff.val_arst.bits()[i] = State::S1; ff.val_arst.set(i, State::S1);
} }
} }
if (ff.has_srst) { if (ff.has_srst) {
if (ff.val_srst[i] == State::Sx) { if (ff.val_srst[i] == State::Sx) {
if (!(supported & (mask << 8))) if (!(supported & (mask << 8)))
ff.val_srst.bits()[i] = State::S0; ff.val_srst.set(i, State::S0);
if (!(supported & (mask << 4))) if (!(supported & (mask << 4)))
ff.val_srst.bits()[i] = State::S1; ff.val_srst.set(i, State::S1);
} }
} }
} }

2
passes/techmap/flowmap.cc
View file

@ -1401,7 +1401,7 @@ struct FlowmapWorker
log_signal(node), log_signal(undef), env.c_str()); log_signal(node), log_signal(undef), env.c_str());
} }
lut_table.bits()[i] = value.as_bool() ? State::S1 : State::S0; lut_table.set(i, value.as_bool() ? State::S1 : State::S0);
ce.pop(); ce.pop();
} }

9
passes/techmap/techmap.cc
View file

@ -680,15 +680,16 @@ struct TechmapWorker
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) { if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first))) != 0) {
RTLIL::Const value; SigSpec sm = sigmap(conn.second);
for (auto &bit : sigmap(conn.second)) { RTLIL::Const::Builder builder(GetSize(sm) * bits);
for (auto &bit : sm) {
int val = unique_bit_id.at(bit); int val = unique_bit_id.at(bit);
for (int i = 0; i < bits; i++) { for (int i = 0; i < bits; i++) {
value.bits().push_back((val & 1) != 0 ? State::S1 : State::S0); builder.push_back((val & 1) != 0 ? State::S1 : State::S0);
val = val >> 1; val = val >> 1;
} }
} }
parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), value); parameters.emplace(stringf("\\_TECHMAP_CONNMAP_%s_", log_id(conn.first)), builder.build());
} }
} }

2
passes/techmap/zinit.cc
View file

@ -76,7 +76,7 @@ struct ZinitPass : public Pass {
if (ff.val_init[i] == State::S1) if (ff.val_init[i] == State::S1)
bits.insert(i); bits.insert(i);
else if (ff.val_init[i] != State::S0 && all_mode) else if (ff.val_init[i] != State::S0 && all_mode)
ff.val_init.bits()[i] = State::S0; ff.val_init.set(i, State::S0);
} }
ff.flip_bits(bits); ff.flip_bits(bits);
ff.emit(); ff.emit();