mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-13 21:21:27 +00:00
Code Activity

Update passes/sat to avoid bits()

Browse source
This commit is contained in:
Robert O'Callahan 2025-08-28 03:53:42 +00:00
parent 32b53f177c
commit 510eac4ad0
4 changed files with 35 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/sat/eval.cc
View file

@ -256,7 +256,7 @@ struct VlogHammerReporter
for (int j = input_widths[i]-1; j >= 0; j--) {
ce.set(RTLIL::SigSpec(wire, j), bits.back());
recorded_set_vars.append(RTLIL::SigSpec(wire, j));
recorded_set_vals.bits().push_back(bits.back());
recorded_set_vars.append(RTLIL::Const(bits.back()));
bits.pop_back();
}
if (module == modules.front()) {
@ -346,7 +346,7 @@ struct VlogHammerReporter
log_error("Pattern %s is to short!\n", pattern.c_str());
patterns.push_back(sig.as_const());
if (invert_pattern) {
for (auto &bit : patterns.back().bits())
for (auto bit : patterns.back())
if (bit == RTLIL::State::S0)
bit = RTLIL::State::S1;
else if (bit == RTLIL::State::S1)

2
passes/sat/formalff.cc
View file

@ -851,7 +851,7 @@ struct FormalFfPass : public Pass {
auto before = ff.val_init;
for (int i = 0; i < ff.width; i++)
if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
ff.val_init.bits()[i] = State::S0;
ff.val_init.set(i, State::S0);
if (ff.val_init != before) {
log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",

29
passes/sat/sat.cc
View file

@ -620,14 +620,18 @@ struct SatHelper
int last_timestep = -2;
for (auto &info : modelInfo)
{
RTLIL::Const value;
bool found_undef = false;
RTLIL::Const::Builder value_builder(info.width);
for (int i = 0; i < info.width; i++) {
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits().back() = RTLIL::State::Sx, found_undef = true;
RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0;
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i)) {
bit = RTLIL::State::Sx;
found_undef = true;
}
value_builder.push_back(bit);
}
RTLIL::Const value = value_builder.build();
if (info.timestep != last_timestep) {
const char *hline = "---------------------------------------------------------------------------------------------------"
@ -732,13 +736,14 @@ struct SatHelper
int last_timestep = -2;
for (auto &info : modelInfo)
{
RTLIL::Const value;
RTLIL::Const::Builder value_builder(info.width);
for (int i = 0; i < info.width; i++) {
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0;
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits().back() = RTLIL::State::Sx;
bit = RTLIL::State::Sx;
value_builder.push_back(bit);
}
RTLIL::Const value = value_builder.build();
if (info.timestep != last_timestep) {
if(last_timestep == 0)
@ -779,12 +784,14 @@ struct SatHelper
for (auto &info : modelInfo)
{
Const value;
RTLIL::Const::Builder value_builder(info.width);
for (int i = 0; i < info.width; i++) {
value.bits().push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
RTLIL::State bit = modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0;
if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
value.bits().back() = RTLIL::State::Sx;
bit = RTLIL::State::Sx;
value_builder.push_back(bit);
}
Const value = value_builder.build();
wavedata[info.description].first = info.width;
wavedata[info.description].second[info.timestep] = value;

32
passes/sat/sim.cc
View file

@ -127,16 +127,11 @@ struct SimShared
bool initstate = true;
};
void zinit(State &v)
{
if (v != State::S1)
v = State::S0;
}
void zinit(Const &v)
{
for (auto &bit : v.bits())
zinit(bit);
for (auto bit : v)
if (bit != State::S1)
bit = State::S0;
}
struct SimInstance
@ -419,16 +414,17 @@ struct SimInstance
Const get_state(SigSpec sig)
{
Const value;
Const::Builder builder(GetSize(sig));
for (auto bit : sigmap(sig))
if (bit.wire == nullptr)
value.bits().push_back(bit.data);
builder.push_back(bit.data);
else if (state_nets.count(bit))
value.bits().push_back(state_nets.at(bit));
builder.push_back(state_nets.at(bit));
else
value.bits().push_back(State::Sz);
builder.push_back(State::Sz);
Const value = builder.build();
if (shared->debug)
log("[%s] get %s: %s\n", hiername().c_str(), log_signal(sig), log_signal(value));
return value;
@ -488,7 +484,7 @@ struct SimInstance
for (int i = 0; i < GetSize(data); i++)
if (0 <= i+offset && i+offset < state.mem->size * state.mem->width && data[i] != State::Sa)
if (state.data[i+offset] != data[i])
dirty = true, state.data.bits()[i+offset] = data[i];
dirty = true, state.data.set(i+offset, data[i]);
if (dirty)
dirty_memories.insert(memid);
@ -500,7 +496,7 @@ struct SimInstance
if (offset >= state.mem->size * state.mem->width)
log_error("Addressing out of bounds bit %d/%d of memory %s\n", offset, state.mem->size * state.mem->width, log_id(memid));
if (state.data[offset] != data) {
state.data.bits()[offset] = data;
state.data.set(offset, data);
dirty_memories.insert(memid);
}
}
@ -717,10 +713,10 @@ struct SimInstance
for(int i=0;i<ff.past_d.size();i++) {
if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
current_q.bits()[i] = State::S0;
current_q.set(i, State::S0);
}
else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
current_q.bits()[i] = State::S1;
current_q.set(i, State::S1);
}
}
}
@ -770,7 +766,7 @@ struct SimInstance
if (index >= 0 && index < mem.size)
for (int i = 0; i < (mem.width << port.wide_log2); i++)
if (enable[i] == State::S1 && mdb.data.at(index*mem.width+i) != data[i]) {
mdb.data.bits().at(index*mem.width+i) = data[i];
mdb.data.set(index*mem.width+i, data[i]);
dirty_memories.insert(mem.memid);
did_something = true;
}
@ -971,7 +967,7 @@ struct SimInstance
if (w->attributes.count(ID::init) == 0)
w->attributes[ID::init] = Const(State::Sx, GetSize(w));
w->attributes[ID::init].bits()[sig_q[i].offset] = initval[i];
w->attributes[ID::init].set(sig_q[i].offset, initval[i]);
}
}